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RF circuit design: BasicsAkira MatsuzawaTokyo Institute of Technology1

Contents Building blocks in RF system and basicperformances Device characteristics in RF application Low noise amplifier design Mixer design Oscillator design2

Basic RF circuit blockRF systems are composed of limited circuits blocks.LNA, Mixer, and Oscillator will be discussed in my talk.Receiver1)LowImpedance NoiseMatching Amp.Transmitter2) Mixer Filter3) OscillatorPowerAmp.3

Basic functions of RF building blocksAmplifier, frequency converter (mixer oscillator), and filerare basic function blocks in RF system.2) Mixer OscillatorUndesiredDown conversiondB3) FilterdBDesired1) AmplifierFrequency conversionLog (f)Up conversionLog (f)4

RF Amplifier Gain: Amplify small signal or generate large signal. Noise: Smaller noise and larger SNR. Linearity: Smaller non-linearity.Non-linearity generates undesired frequency components.vout (t ) α1vin (t ) α 2 vin2 (t ) α 3vin3 (t ) .(cos(ω1t ) cos(ω2t ))2 2 cos(2ω1t ) cos(2ω2t ) cos((ω1 ω2 )t ) cos((ω1 ω2 )t )(cos(ω1t ) cos(ω2t ))311 cos((2ω1 ω2 )t ) cos((2ω2 ω1 )t ) .225

Input and output characteristicsDistortion and noise are important factors in RF amplifier, as well as power and pe 1NoiseFloorSNR minSlope 3SNR minSFDRBDRNoiseMDSFloorPinCP1dBIIP36

Dynamic rangeNoise Floor 174dBm NF 10 log BWkT limitationBandwidthSFDR: Spurious free dynamic rangeThe input power range over which third order inter-modulation productsare below the minimum detectable signal level.SFDR 2(IIP3 Noise Floor ) SNR min3BDR: Blocking dynamic rangeBDR P1dB Noise Floor SNR minMDS: Minimum detectable signal level Noise Floor SNRmin7

Non-linearityCP1dB: The input level at which the small signal gain has dropped by 1dB.CP1dB 0.145α1α3IMD3: The third order inter modulation termIP3: The metric third order intercept point. It is the point where the amplitude ofthird order inter modulation is equal to the that of fundamental.AIP 3 4 α13 α3IIP3: Input referred intercept pointOIP3: Output referred intercept pointPout IMD3 2 (IIP3 Pin )8

MOS transistorIntrinsic gate voltage and gm are the most important factors in RF CMOS.DrainGateGBodySourceMOS Transistorrg vg’ CgdCgsrdsgmvg’DCdsS, BEquivalent Circuit9

Cutoff frequency: fTFor higher fT, increase gm and decrease Cin.IiIofT: Frequency at which the current gain is unity.GDCinIiVigmViSIi Iio sin(ωt )IioVi cos(ωt )ωCinInput currentGate voltagegmIio cos(ωt )Io gmVi ωCingm fT 2πCinOutput currentProportional to gmInversely proportional to Cin10

Amplifier gainFor higher voltage gain, increase gm, fT, ro (Q), and decrease input and gate resistanceIgrsVs VgIdCinLog (G)ωg gmVgro1rsCinG G gmr0ωT ωT r 0 ω rsω0 For the larger gaingmror0 ωTrsCinrs1Fundamentally larger gmr0 G gmro Higher fT and lower rsgmCinIds Veff 2Log (f) roVeff is difficult to reduceLarger Ids or roLarger QQQro Qω0L ω0CÆ Distortion and Cin increase11

Characteristics of gm (Basic)Gm is proportional to the Ids and inversely proportional to the Veff.Veff is proportional to square root of Ids and inversely proportional tosquare root of (W/L) ratio.Square law regionμCOX W μCOX W (Vgs VT ) Veff2n L 2n L dIμCOX W gm ds VeffdVgsn L Ids gm 22 μCOX W Idsn L Veff L21Idsgm, gm Veff Ids Veff 2 2 Veff Ids L JdsW2n1 L Idsμ Cox WScalingW/L ratioVeff is proportional to square root of drain current density.12

Non-ideal effects to square low regionAt larger Veff and lower Veff, two non-ideal effects are not negligible .Sub-threshold region VgsIds Iso exp nU TIdsgm nU T25.083 ( Weak inversion) gm1eff( 0.4 , 10 , Veff) eff( 0.2 , 5 , Veff)Ids nU TGm/Ids (S/A)Low Veff30gm1 constIds nUT2520gm2 Ids Veff1510High Veffμ Mobility degradationμ0μ, θ θ0 01 θVeffvcL51.30200.20.200.20.4VeffVeff (V)0.60.81This effect becomes larger at large Veff and short channel length.13

DistortionLower Veff gives higher gm, bur results in higher distortion.To obtain lower distortion ( higher IIP3), we must increase Veff.Higher gm and lower distortion means higher Ids.31 d 3 Ids a3 6 dVeff 34 a1IIP 3 3 a3L 0.1umL 0.2umL 0.4umIIP3gm/Ids (S/A)100101-0.1Veff (V)101IIP3 (V)Ids a1Veff a 2Veff a 3Veff20.100.10.20.30.40.5Veff (V)14

LC resonatorLC resonator can be regarded as resistance at the resonance frequency.QCLSubstrateω0 r01LCQro Qω 0 L ω 0C15

Substrate effectSubstrate should be treated as resistive network.This substrate resistance causes RF power loss and noise generation.Shielding can reduce this effect.GateRF power loss and noise generationGatePADSDSDSSDSDSPADShield layer16

Power loss in substrateVery low resistance or high resistance realizes low power loss.CGpRpHigher C and moderate Rsubresults in higher power loss.CpEquivalentGCϖppp 1R p C ω ϖp ω1 ϖ 1 ω1 ϖ 1R pCp 2 p2Gp(mS)12Cp(pF)1MOS: 10ΩcmGaAs: 1GΩcm10100Rp(Ω）0.11K10K17

GHz operation by CMOSThe cutoff frequency of MOS becomes higher than that of Bipolar.Over several GHz operations have attained in CMOS technology0.13um100G0.18um0.25um50GFrequency (Hz)0.35umfT : CMOSfT : Bipolar (w/o SiGe)fT /10 (CMOS )20GRF circuits10G5GCellularPhoneCDMA5GHz W-LANfT /60 (CMOS )gmfT 2πCinvsatfTpeak 2πLeffDigital circuits2G1GIEEE 1394D R/C for HDD500M200M100M199520002005Year18

Effect of parasitic capacitance to fTfT of actual circuit is reduced by a parasitic capacitance.There is an optimum gate width to obtain highest fT.10606 .10105.786 .10gmfT 2π (Cgs Cgd Cp )CinVi4 .104010fti 0.2, W , 5 .10gmVi3,0fti 0.2 , W , 5 .103, 0.1 .1012fti 0.2 , W , 5 .103, 0.5 .1012fT (GHz)CpIds 5mAL 0.2umCp 0Cp 0.1pF(1)102 .1020(2)Cin Cgs CgdCp 0.5pFRegion(1); Increased by increasing1.576gm.109Region(2); Decreased by increasing Cin00 010200400600WW(um)80010001 .10319

fT: MOS vs. BipolarEven if fT of MOS is the same as that of Bipolar,fT of MOS is easily lowered by a parasitic capacitance.Because, gm of MOS is ½ to ¼ of that of Bipolar at the same current.Small parasitic capacitance is a key for RF CMOS design.MOSgmfT 2πCinIdsgm Veff 2 Veff min 2nU TIcgm UTUT n: 1.4Veff/2: 50-100mV(actual ckt.)BipolarkT 26mVqgmCMOS 1 1, gmBip （Same operating current）2 4CinCMOS 1 1, CinBip2 4（Same fT）20

VT mismatchVT mismatch degrades accuracy; ADC, OP amp, and Mixer.Larger gate area is needed for small VT mismatch.Scaling and proper channel structure improves mismatch.ΔVT (σ:mV)15ToxΔVT LW0.4um NchLarger gate area0.13um Nch Boron w. Halo*Tox Scaling100.4um PchChannel engineering50.13um Nch In w/o Halo*000.10.20.30.41( μm 1 )LW0.50.60.70.8* Morifuji, et al., IEDM 2000.21

VT mismatch: Fluctuation of dopingCourtesy of Prof. Taniguchi, Osaka Univ.ΔVT ΔQdeplCox AtoxLWd depl N AQ d depl - - -- - - - - --基板LW1NA A′tox4NALW AVTtoxLWAVT 1VddeplL W 0.25μ m, tox 5nmΔVT 20mVT.Mizuno, J.Okamura and A.Toriumi, ”Experimental study o f threshold voltagefluctuation due to statistical variation of channel dopant number in MOSFETs,”IEEE Trans. On Electron Devices, ED-41, 2216 (1994)22

1/f noise1/f noise of MOS is larger than that of bipolar.For the lower 1/f noise, the larger gate area is needed.Svf Δf,LW fSvf Tox2Nch 0.4um/1.0um1E-13W/L 800/0.4Vdd 3VId 1mA1E-141E-15nMOS1E-161E-17pMOS1E-181E-191E 02Bipolar1E 031E 041E 051E 06Frequency (Hz)1E 07Input referred noise voltage (V2/Hz)Input referred noise voltage (V2/Hz)Nch/Pch 0.4um1E-13nMOSVdd 3VId 1mA1E-141E-15L 0.4um1E-161E-17L 1.0um2Vnf2 1E-18Bipolar1E-191E 021E 031E 041E 051E 061E 07Frequency (Hz)23

Noise figure: GeneralThe lower Rnv and Gni realizes the better for a lower noise figure.ZsVn,rsVngNoiselessCircuitIngVsZs Rs jXsVng 2 4kTRnv , Ing 2 4kTGniVn2,rs (Vng ZsIng )2F Rsopt Vn2,rsVngRnv GniIng 1 Rnv Rs2Zs GniRs 1 Rnv RsGniRsF min 1 2 RnvGni24

Noise figure: MOS transistorRnvF 1 RsGniRsRnv Rg RgsW1Rg Rsr totL 3N 21gm ω 0 RsF 1 Rs5 gm5 ωT 1Rgs 5 gm2Rsopt Gni gm ω 0 5 ωT 21 ωT 1 gm ω 0 Cgsω 0F min 1 2ω0ωT25

Low noise amplifier designNarrowband LNA uses inductor degeneration for impedance matching.Impedance matching1 gm Zin s(Ls Lg ) L s ωT L ssCgs Cgs ω0 1Cgs (Ls Lg )Z0M2LgrgM1CpiRsubCgs rgsLs26

Low NF designrgs rgrgs rg ω0 F 1 4γgmZ 0 1 Z0Z0 ωT 2rgs Low noise figurerg Rsr1) Lower the gate resistanceReduce parasitic capacitanceUse shield technique to the input bonding PAD.4) Increase Z0, if possible.(Veff )1rgs 5 gm 10 IdsWtotLRsr: Sheet resistanceN：The # of divisionDivide the gate2) Reduce substrate lossUse high resistive substrate, if possible.Wtot 1L 3N 2rg RsrDived the gate or lower the gate sheet resistance3) Increase drain current15 gmSDSDSDS27

Ids and Veff optimizationAdjust the Ids and Veff for optimization of gain, noise and distortion.Dynamic range of LNA is proportional to Ids.IIP3LNADRLNA gmZ 0Veff IdsZ 0 IIP3 VeffF 1Higher IdsLower IdsNFdBGain3rd distortionVeff VeffIdsW28

NF progress in MOS LNANF of MOS LNA is reaching 1dB.8.07.06.0NF (dB)5.04.03.02.01.00.010.50.350.250.1Gate length (μm)29

MixerMixer converts frequency, but image signal is converted to the same frequency.Vs As cos(ωst )VsVoVo As2πcos((ωs ωLO )t )If VLO 4Veff (Full swing)VLOVLO ALO cos(ωLOt )RF spectrumIF spectrumFLOdBdBFimageFdesFreqFreqFIF FIFFIF30

Image-reject mixersThe quadrature mixing realizes image-suppression.Gain and phase matching is needed.LPFVin (t)45 cos(ωLOt ) sin (ωLOt )LPFVout(t) 45 Vin (t ) Ades cos(ωdest ) Aim cos(ωimt )Vout (t ) AdesAc cos(ωIFt ) AimAcIR cos(ωIFt )Ac: Conversion gain, IR: Image rejectionIR 0 if I/Q phase difference is 90 and Channel conversion gains are equal.31

Gain mismatch and phase errorPspur 1 γ 2 2γ cos φ Pdesired 1 γ 2 2γ cos φγ: Gain ratioφ:Phase errorA. Rofougaran, et al.,IEEE J.S.C. Vol.33, No.4,April 1998. PP. 515-534.32

Passive FET mixerMOS can realize a passive mixer easily.Ultimately low power, but take care of isolation.Passive FET mixerVinLoLoVoVoLoLoLow powerHigh linearityNo 1/F noiseNo conversion gainNo isolation, Bi-directionalVin33

Active mixersSingle balanced mixerDouble balanced mixerVery small direct feed through and even order distortionVoZLLoZLVoM2M3ZLVoLoM2 M3LoVinM1ZsZLVoM2’ M3’LoVinLoVinM1ZsM1’Zs34

Active mixer designThe larger Ids is needed for high dynamic rangeand shorter switching time for low 1/f noise.Mixer gainGmix 2πgm1ZL , or 2 ZLπ Zswhen Zs is usedR : Resistive component in ZLLThermal noise v 8kTRL 1 2γIRL γgm1RL 8kTR 2γgm1L πALO v on2γVeff2222ππγkTkTSSBvin 2Idsgm1 2 1LgmR π A larger dynamic range needs larger currentIIP3 Veff1/F noise2on1) Switch transistor (M2, M3)vn , o 4Tsvn , swTLO1vn2 , sw WL 1CgsTsTLOPhase modulationShorter switching time or larger Ts/TLo ratio2) Load transistorsDirectly produces35

OscillatorThere is an optimum Ids for low phase noise.VddVoLLVoLQ-1/gmCCr0-1/gmCVc1) Amplitude conditionM3M2OscillationamplitudeVbI M1Vosc ro Qω 0 L 4 IroHeadroomlimitππVdd πVddωoC Iopt 2 roQQω 0C2Vdd(a)2) Oscillation conditiongm 2,3 2,roI ωoCVeff , 2,3Q36

Phase noise of oscillatorPhase-frequency relation and resonator characteristics determine phase noise.v(t ) A cos[ω 0t φ (t )]12QL Bw ω 0RZ ( jω )dφ jωφdtωmSω (ωm) ωm2 Sφ (ωm )Sω (ωm):Noise spectrum densityon offset angular frequencySφ (ωm ):Noise spectrum densityon phaseωm Bw0.7RΔθ ωφdφ 2QLω0ωω0dωωmBw 2QLω02ωm ω0 SΔθ (ωm )Sω (ωm) 2QL 2ΔθSΔθ (ωm ): Offset angular frequencyPhase error between in and out:Noise spectrum densityon phase errorωm Bw2 ω0 1 ω0 2 SΔθ (ωm ) SΔθ (ωm )Sφ (ωm) 2QL ωm 2QLωm 37

Phase noise of oscillatorZ (ω 0 ωm ) jLQC-1/gm-1/gmr0ω0L(Filter action) ω0 vn2in22 Z 4kTro Δf Δf 2Qωm R0.7RQ ωm ω 0r 0ω 0Z (ω 0 ωm ) 2Qωm12Q Bw ω 0Z ( jω )r0ω0Lωm2ω0Bw2Noise spectrum densityω 2kTL{ωm} 10 log PsigPhase noise ω0 2Qωm 2 38

Frequency characteristics of Phase noise in oscillator1/f noise and thermal noise is converted to 1/f3 and1/f2, respectively.Phase noise spectrumSφ (ωm )2 ω0 1 a 3 2QL ωm-9dB/oct(Slope -3)SΔθ (ωm ) 2 ω 0 2 FkT 1 22LQ Ps ωm(Slope -2)ThermalωcoBw ωmSΔθ (ωm ) 2 FkTPs2 FkTPs-6dB/oct1/f noise2 1 ω0 SΔθ (ωm )Sφ (ωm) Lm2Qω aThermal2QLω0ωm39