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Allegro PCB Design SolutionManaging complexity for faster, more cost-effective implementationsSystems companies are impacted by new devices and design methodologies offered by the semiconductorindustry. New devices often bring more challenges, like increasing pin counts packaged in shrinking pinpitch ball grid arrays (BGAs). Additionally, new devices use evolving standards-based interfaces, such asDDR3, DDR4, PCI Express (PCIe ) Gen3, USB 3.0, and others, that may require learning new ways toimplement them on the board. Coupled with these increasingly complex technologies is the desire bycompanies to differentiate their offerings and get them to market faster, cheaper, with more functionalityand in reduced end product size. As a result, many companies now outsource to or partner with companiesin low-cost geographies. To manage such increasing complexities, PCB designers need a solution thataddresses their technological and methodological challenges.Allegro PCBDesign SolutionCadence Allegro PCB Designeris a scalable, proven PCB designenvironment that addressestechnological and methodological challenges while makingthe design cycles shorter andpredictable. Available in baseplus options configuration, thePCB design solution containseverything needed to createa PCB layout with a fully integrated design flow. The base—Allegro PCB Designer—includesa common, consistent constraintmanagement solution, PCBEditor, an auto-interactiverouter, as well as interfaces formanufacturing and mechaniFigure 1: Allegro PCB design solution brings together all the tools needed to design simple-tocal CAD. PCB Editor provides acomplex PCBscomplete placement and routing environment—from basic Eliminates unnecessary iterations Features a common, consistentfloorplanning, placement, andthrough constraint-driven PCBconstraint-management systemrouting to placement replication anddesign flowfor creation, management, andadvanced interconnect planning—forvalidation of constraints from frontsimple to complex PCB designs. Supports a comprehensive ruleto backset for physical, spacing, designBenefitsfor fabrication (DFF), design for Open environment for third-partyassembly (DFA), and design for testapplication improves productivity Offers a proven, scalable,(DFT), high-density interconnectwhile providing access to best-ofcost-effective PCB editing and(HDI), and electrical (high-speed)breed integrated point toolsrouting solution in on-demand basedomainsplus options configuration
Allegro PCB Design SolutionPCB Editor TechnologyConstraint-Driven PCB EditingEnvironmentAt the heart of Allegro PCB Designer isa PCB Editor—an intuitive, easy-to-use,constraint-driven environment for creating and editing simple to complex PCBs.Its extensive feature set addresses a widerange of design and manufacturabilitychallenges: A powerful set of floorplanning andplacement tools including placementreplication for accelerating placementof the design Powerful shape-based shove, huginteractive etch creation, editingestablishes a highly productiveinterconnect environment whileproviding real-time, heads-up displaysof length and timing margins Dynamic shape capability offersreal-time copper pour plowing andhealing functionality during placementand routing iterationsThe PCB Editor can also generate a fullsuite of phototooling, bare-board fabrication, and test outputs, including Gerber274x, NC drill, and bare-board test in avariety of formats.Constraint ManagementA constraint management system displays physical/spacing and high-speedrules along with their status (based onthe current state of the design) in realtime and is available at all stages of thedesign process. Each worksheet providesa spreadsheet interface that enablesusers to define, manage, and validate thedifferent rules in a hierarchical fashion.With this powerful application, designerscan graphically create, edit, and reviewconstraint sets as graphical topologiesthat act as electronic blueprints of anideal implementation strategy. Once theyexist in the database, constraints can drivethe placement and routing processes forconstrained signals.The constraint management system iscompletely integrated with the PCB Editor,and constraints can be validated in realtime as the design process proceeds. Theresult of the validation process is a graphi-www.cadence.comFigure 2: DFA rules-driven placement allows for compact placement of components withoutintroducing errorscal representation of whether constraintspass (highlighted in green) or fail (highlighted in red). This approach allowsdesigners to immediately see the progressof the design in the spreadsheets, as wellas the impact of any design changes.Floorplanning and PlacementThe constraint and rules-driven methodology of PCB design solutions includesa powerful and flexible set of placement capabilities, including interactiveand automatic. The engineer or designercan assign components or subcircuitsto specific “rooms” during design entryor floorplanning. Components can befiltered and selected by reference designator, device package/footprint style,associated net name, part number, or theschematic sheet/page number.With thousands of components comprising today’s boards, precise managementis critical. Real-time assembly analysisand feedback can facilitate this management—helping designers increaseproductivity and efficiency by placingcomponents according to corporate orEMS guidelines. Dynamic DFA-drivenplacement offers real-time packageto-package clearance checking duringinteractive component placement (seeFigure 2). Driven from a two-dimensionalspreadsheet array of classes and packageinstances, real-time feedback providesminimum clearance requirements. Basedon the package’s side-to-side, side-toend, designers can simultaneously placedevices for optimum routability, manufacturability, and signal timing.Placement ReplicationSuperior placement replication technologywithin Allegro PCB Designer allows usersto quickly place and route multiple similarcircuits in a design. It allows users to createa template using one instance of placedand routed circuit that can be applied toother instances within the design. Thesaved placement template can be usedwith other designs where similar circuitsare used. When replicating placement,users can flip or mirror the circuit from toplayer to bottom layer. All associated etchelements, including blind buried vias, aremapped to correct layers when circuit ismoved from top layer to bottom layer.Display and VisualizationThe built-in 3D viewer is available in allPCB Editor products. The 3D environmentsupports several filtering options, cameraviews, graphic display options such assolid, transparency, and wireframe, andmouse-driven controls for pan, zoom, andspinning the display. 3D viewing also supports the display of complex via structuresor isolated sections of the board. Multipledisplay windows can be opened using thecontext sensitive command structure, and3D images can be captured and saved inJPEG format. (See Figure 3.)The flipboard capability “flips” the designabout its Y axis inverting the design database in the canvas. This “flip” reorganizesthe display of the design such that whatwas displayed as top through to bottombecomes bottom through to top. Havinga true bottom side view from within theCAD system is essential for hardware2
Allegro PCB Design Solutionogy requirements—and it’s no wonderthat traditional CAD tools and technologies fall short of capturing a designer’sspecific routing intent and acting upon it.The Allegro PCB Designer Design PlanningOption provides the technology andmethodology to capture as well as adhereto a designer’s intent. Through the interconnect flow planning architecture andthe global route engine, users can for thefirst time put their experience and designintent into a tool that understands whatthey want—natively.Figure 3: Built-in 3D viewer allows reviewing of a section of the board or complex via structureswith pan, zoom, rotation, and spinning to reduce iterations with mechanical design teams or PCBfabricators without introducing errorsengineers when debugging a board in thelab, or for assembly/test engineers on themanufacturing floor. Flipboard is not justlimited to viewing; design edits can alsobe performed while in this mode.hours with traditional one trace at a time.Hug-contour option takes care of inserting traces with curves that are aligned tocontour of the flex portion of the design.(See Figure 4.)Interactive Etch EditingDesign Planning OptionThe routing feature of the PCB Editorprovides powerful, interactive capabilities that deliver controlled automation tomaintain user control, while maximizingrouting productivity. Real-time, shapebased, any-angle, push/shove routingenables users to choose from “shovepreferred,” “hug-preferred,” or “hugonly” modes.Highly constrained, high-density designsdominated by bussed interconnect cantake significant time to strategically planand route. Compound this with thedensity issues of today’s components,new signaling levels, and specific topol-Users create abstracted interconnect data(through the interconnect flow planningarchitecture) and can quickly converge ona solution and validate it with the globalroute engine. The interconnect abstraction reduces the number of elements thesystem has to deal with—from potentiallytens of thousands down to hundreds—resulting in a significant reduction in themanual interaction required.Using the abstracted data, the planningand routing process can be acceleratedby providing a visual/spatial map of theopen area in relation to the data and theuser’s design intent. The route engine canthen deal with the details of the routing,adhering to the specified intent, without the user having to both visualize andsolve the interconnect problems at once.This significant simplification over currentdesign tools means users converge on aDuring etch editing, the designer can viewa real-time, graphical heads-up display ofhow much timing slack remains for interconnect that has high-speed constraints.Interactive routing also enables grouprouting on multiple nets and interactivetuning of nets with high-speed length ordelay constraints.Multi-Line RoutingMulti-line routing allows users to quicklyroute multiple lines as a group on thePCB. Coupled with “hug-contour” option,this utility can help designers routemultiple lines on the flex portion of therigid-flex design in minutes instead ofwww.cadence.comFigure 4: Multi-line routing with contour hug option accelerates through no-click routing on flexsection of the PCB designs3
Allegro PCB Design Solutionsystem then provides feedback throughthe constraint manager if a signal doesn’tconform to the topology or the rules associated with the topology, ensuring thatissues are identified (and therefore can beaddressed) as quickly as possible.Figure 5: The Design Planning Option allows users reduce layer counts and shorten design cyclethrough design planningsuccessful interconnect solution far fasterand more easily than ever before, reducing design cycle time through increasedefficiency and productivity. (See Figure 5.)Getting routes out of dense BGAs isincreasingly difficult for PCB designers.With increasing pin counts and shrinking pin pitches, the time PCB designersspend on getting routes in and out ofBGAs has gone up significantly. The traditional approach of performing breakoutsfirst then routing the traces between twoBGAs is running out of steam becauseresolving the resulting crossovers takes upa lot of time and board real estate.It offers an extensive range of electricalrules to ensure that the PCB design implementation is complaint with the specification for advanced interfaces. Additionally,it allows users to extend the rules throughthe use of formulas with existing rulesor post-route data such as actual tracelengths.The High-Speed Option allows users toapply a topology to a set of signals. Atopology can include a set of routingpreferences as well as constraints suchas putting the termination resistor closerto either the driver or a receiver on asignal. The constraint-driven PCB designThe High-Speed Option also enableschecking of delays through vias, connector pins, and IC package-pin for die2dielength/delay matching. It includes, utilitiesto identify trace segments crossing voids(return path issues that cause re-spins),supports back drilling (remove throughhole antennas) as well as provides atiming environment that can accelerate timing closure of critical nets up to60-70%.Accelerated Timing ClosureAs the data rates increase and supply voltages decrease in today’s advanced interfaces like DDR3/DDR4, PCIe, SATA, etc.,PCB designers must spend more time toensure signals in an interface meet timingrequirements. With increasing density onPCBs, the effort to get to timing closure—ensuring all signals meet timing requirements—can increase significantly. PCBdesigners need new tools to meet thisincreasingly complex challenge.Timing VisionTiming Vision is an innovative and uniqueenvironment that allows users to graphically see real-time delay and phase infor-AiBTAuto-interactive Breakout Technology(AiBT) improves user efficiency byallowing users to plan to break out onboth ends. AiBT can be used with thenew, Split View, and Bundle Sequencecommands to dramatically shorten thetime required to develop a high-qualityand properly ordered breakout solution(see Figure 6).High-Speed OptionIncreasing use of standards-basedadvanced interfaces such as DDR3,DDR4, PCIe, USB 3.0 are bringing a set ofconstraints that must be adhered to whileimplementing a PCB.The Allegro PCB Designer High-SpeedOption makes adhering to constraintson advanced interfaces quick and easy.www.cadence.comFigure 6: Split View allows working on both ends of a zoomed-in interface4
Allegro PCB Design SolutionBackdrillingThe High-Speed Option allows users tospecify which vias on critical high-speedsignals should be back drilled to avoidreflections. An output report—BackdrillNC and Legend Files from Bottom, Top, orAny Layer if backdrilling the inner core(s)of the PCB—allows users to send backdrilling instructions to their PCB manufacturersManufacturing OptionThe Allegro PCB Designer ManufacturingOption provides a comprehensive, powerful, easy-to-use suite of tools that makesit efficient and cost effective for PCBdesigners to streamline the developmentof release-to-manufacturing packages fortheir products. It includes three modules:Design for Manufacturing (DFM) Checker,Documentation Editor, and Panel Editor.Figure 7: AiDT shortens time to tune high-speed signals by 50% or more.mation directly on the routing canvas.Traditionally, evaluating current statusof timing/length of a routed interfacerequires numerous trips to ConstraintManager and/or use of the ShowElement command. Using an embedded route engine to evaluate complextiming constraints and interdependencies amongst signals shows current statusof a set of routed signals—a DDRx bytelane or a complete DDRx interface—via custom trace/connect line coloring;stipple patterns and customized data tipinformation to define the delay problemin the simplest terms possible.With the embedded route engine, TimingVision provides real-time feedback tothe user during interactive editing andenhances the user’s ability to developa strategy for resolving timing on largebuses or interfaces such as DDRx, PCIe,etc. Coupled with Auto-interactive PhaseTuning (AiPT) and Auto-interactive DelayTuning (AiDT) capabilities, users canaccelerate the time to tune advancedinterfaces like DDRx in one-third the timeit takes to do it manually using traditionalmethods.www.cadence.comAiPTDifferential pairs in an interface like DDRxrequire designers to match static as wellas dynamic phase. Matching phase for alldifferential pairs in an interface is a necessary first step before tuning and matchingthe rest of the signals. AiPT automaticallymatches dynamic and static phase forthe selected differential pairs. It workswith a set of parameters that allows theuser several options for trace lengthening or shortening as well as pad entry/exitoptions. With AiPT, users can significantlyshorten the time to match static anddynamic phases for differential pairs.AiDTDelay tuning for signals for interfaces likeDDRx takes up too much time when usingtraditional, manual methods. AiDT automatically generates tuning patterns on auser-selected routed byte lane or interfacebased on user-defined timing constraintsand tuning parameters. AiDT computesthe required length for the connectionsto meet timing constraints and utilizescontrolled push/shove techniques whenadding tuning patterns (see Figure 7).DFM CheckerThe Manufacturing Option’s DFM Checkermodule is designed for engineers anddesigners who appreciate the benefitsof manufacturing analysis and want toconduct it in a robust environment, withease and sensibility at any phase of thePCB design process. DFM Checker offerscomprehensive analysis for all majorPCB design tools, Gerber files, intelligent manufacturing files, and NC data toensure the content supplied to the manufacturer will minimize costly delays.Documentation EditorThe Manufacturing Option’sDocumentation Editor is a PCB documentation-authoring tool that intelligentlyautomates your documentation creationprocess to produce complex PCB documentation in a fraction of the time versustraditional methods. DocumentationEditor enables you to quickly create themanufacturing drawings that drive PCBfabrication and assembly.Panel EditorThe Manufacturing Option’s Panel Editormodule intelligently automates thecomplex process of panel definition anddocumentation, simplifying the designprocess. This solution enables designersto quickly create electronic manufacturing documents that clearly articulate5
Allegro PCB Design Solutionthe panel specification and instructionsfor successful fabrication, assembly, andinspection of their designs.Design Data Transfer toManufacturingA full suite of phototooling, bare-boardfabrication, and test outputs, includingGerber 274x, NC drill, and bare-board testin a variety of formats, can be generated.More importantly, Cadence supportsthe industry initiative toward Gerber-lessmanufacturing through export and importof design data in IPC-2581 format. TheIPC-2581 data is passed in a single filethat creates accurate and reliable manufacturing data for high-quality manufacturing. Users have a choice to export asubset of the design data for protectingtheir IP. Import of IPC-2581 is intended foroverlaying artwork data on the design forviewing purposes only.Miniaturization OptionConstraint-Driven HDI Design FlowWith BGA pin pitches decreasing to below1mm, (0.8mm or lower with 0.65mmor 0.5mm pin pitches), users are forcedto implement a buildup PCB technologyusing HDI.While miniaturization is not necessarily the primary objective in many marketsegments, the move to buildup technology is necessary for fanning out a BGA—particularly if it has three or four rows ofpins on each side.The Allegro PCB Designer MiniaturizationOption offers a proven constraint-drivenHDI design flow with a comprehensiveset of design rules for all different stylesof HDI designs, from a hybrid buildup/core combination to a complete buildupprocess like ALIVH.In addition, it includes automation foradding HDI to shorten the time to createdesigns that are correct by construction.Embedded ComponentsReducing end product size can be accomplished in many different ways. One ofthe approaches PCB designers are takingis to embed packaged components onwww.cadence.cominner layers. The Miniaturization Optionoffers constraint-driven embedded component placement and routing. It supportsdirect- and indirect-attach techniques, andsupports embedding components withdual-sided contacts, vertical components,and embedding in dielectric on a two-layerPCB. Additionally it offers the ability tocreate and manage cavities on layers specified for embedding components.Analog/RF OptionThe Allegro PCB Designer Analog/RFOption offers a mixed-signal design environment, from schematic to layout withback annotation, proven to increase RFdesign productivity up to 50%. It allowsengineers to create, integrate, and updateanalog/RF/microwave circuits with digital/analog circuits in the Allegro PCBDesign environment. With its rich layoutcapability and powerful interfaces withRF simulation tools, it allows engineersto start RF design from Allegro DesignAuthoring, Allegro PCB Designer, orKeysight Technologies Advanced DesignSystem (ADS).Team Design OptionGlobally dispersed design teams are onthe rise, which compounds the challengeof shortening design cycle times. Manualworkarounds that address multi-userissues are time-consuming, slow, andprone to error.The Allegro PCB Designer Team DesignOption provides a multi-user, concurrentdesign methodology for faster time tomarket and reduced layout time. Multipledesigners working concurrently on alayout share access to a single database,regardless of team proximity. Designerscan partition designs into multiplesections or areas for layout and editingby several design team members.Designs can be partitioned vertically(sections) with soft boundaries or horizontally (layers). As a result, each designercan see all partitioned sections andupdate the design view for monitoringthe status and progress of other users’sections. Such partitioning can dramatically reduce overall design cycles andaccelerate the design process.Routing OptionThe Allegro PCB Designer Routing Optionis tightly integrated with the PCB Editor.Through the Routing Option interface, alldesign information and constraints areautomatically passed from the PCB Editor.Once the route is completed, all route information is automatically passed back to thePCB Editor.Increased design complexity, density,and high-speed routing constraints makemanual routing of PCBs difficult andtime-consuming. The challenges inherent in complex interconnect routing arebest addressed with powerful, automatedtechnology. The robust, productionproven autorouter includes a batch routing mode with extensive user-definedrouting strategy control as well as built-inautomatic strategy capabilities.DFM Rules-Driven AutoroutingThe design for manufacturing capability within the Routing Option significantly improves manufacturing yields.Manufacturing algorithms provide aspreading capability that automaticallyincreases conductor clearances on aspace-available basis. Automatic conductor spreading helps improve manufactuability by repositioning conductors tocreate extra space between conductorsand pins, conductors and SMD pads, andadjacent conductor segments. Users gainthe flexibility to define a range of spacingvalues or to use the default values.Mitered corners and test points can beadded throughout the routing process.The manufacturing algorithms automatically use the optimal setback range,starting from the largest to the smallestvalue. Test point insertion automaticallyadds testable vias or pads as test points.Testable vias can be probed on the front,back, or both sides of the PCB, supporting both single side and clamshell testers.Designers have the flexibility to select thetest point insertion methodology thatconforms to their manufacturing requirements. Test points can be “fixed” to avoidcostly test fixture modifications. Test pointconstraints include test probe surfaces, viasizes, via grids, and minimum center-tocenter distance.6
Allegro PCB Design SolutionHigh-Speed Constraints-DrivenAutoroutingHigh-speed routing constraints and algorithms handle differential pairs, net scheduling, timing, crosstalk, layer set routing,and the special geometry requirementsdemanded by today’s high-speed circuits.The autorouting algorithms intelligentlyhandle routing around or through vias,and automatically conform to definedlength or timing criteria. Automatic netshielding is used to reduce noise on noisesensitive nets. Separate design rules maybe applied to different regions of thedesign; for example, you can specify tightclearance rules in the connector area of adesign and less stringent rules elsewhere.Operating System SupportAllegro PCB Designer Base Plus Options FeaturesFeatureAllegro PCB DesignerAllegro Design Authoring Allegro Design Entry CIS Constraint Manager: Physical, spacing, and samenet rules Constraint Manager: Properties and DRCs Constraint Manager: Differential pair rules Constraint Manager: Region rules Floorplanning, placement, placement replication DFA, DFF, DFT Dynamic feedback on DFA compliance during placement IDF3.0, DXF in/out EDMD schema-based ECAD-MCAD co-design Native 3D viewer Hierarchical interconnect flow planning Length-based rules for high-speed signals Constraint-driven flow for length-based high-speed signals Allegro Platform Technology:Match groups, layer sets, extended nets Sun SolarisT-point rules (pin to T-point) 6-layer automatic shape-based autorouter High-speed rules-based autorouting Linux IBM AIXLayer-specific rules-based autorouting WindowsDesign planning - plan spatial feasibility analysis and feedbackDesign Planning OptionDesign planning - generate topological planDesign Planning OptionDesign planning - Convert topological plan to traces (CLINES)Design Planning OptionOrCAD Technology: WindowsAuto-interactive Delay TuningHigh-Speed OptionConstraint Manager: Electrical rule set (relection, timing, crosstalk)High-Speed OptionConstraint-driven flow using electrical rulesHigh-Speed OptionElectrical constraint rule set (ECSets) / topology applyHigh-Speed OptionFormula and relationship-based (advanced) constraintsHigh-Speed OptionBackdrillingHigh-Speed OptionDie2Die pin delay, dynamic phase control, Z-axis delayHigh-Speed OptionReturn path management for critical signalswww.cadence.com High-Speed OptionConstraint Manager: HDI rule setMiniaturization OptionMicro-via and associated spacing, stacking, and via-in-pad rulesMiniaturization OptionConstraint-driven HDI design flowMiniaturization OptionManufacturing rule support for embedding componentsMiniaturization OptionEmbedd components on inner layersMiniaturization OptionHDI micro-via stack editingMiniaturization OptionDynamic shape-based filleting, line fattening, and trace filletingMiniaturization OptionHug contour routing (Flex)Miniaturization OptionSupport for cavities on inner layersMiniaturization OptionConcurrent team design - layer-by-layer partitioningTeam Design OptionConcurrent team design - functional block partitioningTeam Design OptionConcurrent team design - team design dashboardTeam Design OptionConcurrent team design - soft netsTeam Design OptionEdit constraints in a partitionTeam Design OptionManage netclasses in a partitionTeam Design OptionParameterized RF etch elements editingAnalog/RF OptionAsymmetrical clearancesAnalog/RF OptionBi-directional interface with Keysight ADSAnalog/RF Option7
Allegro PCB Design SolutionCadence Services and SupportFeatureAllegro PCB Designer Cadence application engineers cananswer your technical questions bytelephone, email, or Internet—they canalso provide technical assistance andcustom trainingImport Keysight ADS schematics into DE-HDLAnalog/RF OptionLayout-driven RF design creationAnalog/RF OptionFlexible Shape EditorAnalog/RF Option256-layer autoroutingRouting OptionDFM rules-based autoroutingRouting Option Cadence certified instructors teachmore than 70 courses and bring theirreal-world experience into the classroomAutomatic trace spreadiingRouting OptionATP generationRouting OptionLayer-specific rules-based autoroutingRouting Option More than 25 Internet LearningSeries (iLS) online courses allow youthe flexibility of training at your owncomputer via the Internet Cadence Online Support gives you 24x7online access to a knowledge base ofthe latest solutions, technical documentation, software downloads, and moreFor More InformationFor product sales, support, or additionalinformation on Allegro solutions, visitwww.cadence.com/contact us to locatea Cadence Sales office or channel partnerin your area.Cadence Design Systems enables global electronic design innovation and plays an essential role in thecreation of today’s electronics. Customers use Cadence software, hardware, IP, and expertise to designand verify today’s mobile, cloud, and connectivity applications. www.cadence.com 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and Allegro are registered trademarks of CadenceDesign Systems, Inc. PCI-SIG, PCI Express, and PCIe are registered trademarks and/or service marks of PCI-SIG. All other trademarks are the propertyof their respective owners and are not affiliated with Cadence. 4601 04/15 SA/DM/PDF
Cadence Allegro PCB Designer is a scalable, proven PCB design environment that addresses technological and method-ological challenges while making the design cycles shorter and predictable. Available in base plus options configuration, the PCB design solution contains everything needed to create a PCB layout with a fully inte-grated design flow. The base— Allegro PCB Designer—includes a .
