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Cadence Allegro PCB Design SolutionManaging complexity for faster, more cost-effective implementationsSystems companies are impacted by new devices and design methodologies offered by thesemiconductor industry. New devices often bring more challenges, like increasing pin counts packagedin shrinking pin pitch ball grid arrays (BGAs). Additionally, new devices use evolving standards-basedinterfaces, such as DDR3, DDR4, PCI Express Gen3, USB 3.0 and others, that may require learningnew ways to implement them on the board. Coupled with these increasingly complex technologies isthe desire by companies to differentiate their offerings and get them to market faster, cheaper, withmore functionality and in reduced end product size. As a result, many companies now outsource toor partner with companies in low-cost geographies. To manage such increasing complexities, PCBdesigners need a solution that addresses their technological and methodological challenges.Cadence Allegro PCBDesign SolutionAllegro PCB Designer is ascalable, proven PCB designenvironment that addressestechnological and methodological challenges while makingthe design cycles shorter andpredictable. Available in baseplus options configuration, thePCB design solution containseverything needed to createa PCB layout with a fully integrated design flow. The base—Allegro PCB Designer—includesa common, consistent constraintmanagement solution, PCBEditor, an auto/interactiverouter, as well as interfaces formanufacturing and mechaniFigure 1: Allegro PCB design solution brings together all the tools needed to design simple-tocal CAD. PCB Editor provides acomplex PCBscomplete placement and routing environment—from basic Eliminates unnecessary iterations Features a common, consistentfloor-planning, placement,through constraint-driven PCBconstraint management systemand routing to placement replication,design flowfor creation, management, andadvanced interconnect planning—forvalidation of constraints from frontsimple to complex PCB designs. Supports a comprehensive rule setto backfor physical, spacing, design forBenefitsfabrication, assembly and test (DFx), Open environment for third partyhigh-density interconnect (HDI), andapplication improves productivity Offers a proven, scalable,electrical (high speed) domainswhile providing access to best ofcost-effective PCB editing andbreed integrated point toolsrouting solution in on-demand baseplus options configuration
Cadence Allegro PCB Design SolutionPCB Editor TechnologyConstraint-Driven PCB EditingEnvironmentAt the heart of Allegro PCB Designer isa PCB editor—an intuitive, easy-to-use,constraint-driven environment for creating and editing simple to complex PCBs.Its extensive feature set addresses a widerange of design and manufacturabilitychallenges: A powerful set of floorplanning andplacement tools including placementreplication for accelerating placementof the design Powerful shape-based shove, huginteractive etch creation, editingestablishes a highly productiveinterconnect environment whileproviding real-time, heads-up displaysof length and timing margins Dynamic shape capability offersreal-time copper pour plowing &healing functionality during placementand routing iterationsThe PCB editor can also generate a fullsuite of phototooling, bare-board fabrication, and test outputs, including Gerber274x, NC drill, and bare-board test in avariety of formats.Constraint ManagementA constraint management system displays physical/spacing and high-speedrules along with their status (based onthe current state of the design) in realtime and is available at all stages of thedesign process. Each worksheet providesa spreadsheet interface that enablesusers to define, manage, and validate thedifferent rules in a hierarchical fashion.With this powerful application, designerscan graphically create, edit, and reviewconstraint sets as graphical topologiesthat act as electronic blueprints of anideal implementation strategy. Once theyexist in the database, constraints can drivethe placement and routing processes forconstrained signals.The constraint management system iscompletely integrated with the PCB editor,and constraints can be validated in realtime as the design process proceeds. Theresult of the validation process is a graphi-www.cadence.comFigure 2: Design For assembly (DFA) rules driven placement allows for compact placement ofcomponents without introducing errorscal representation of whether constraintspass (highlighted in green) or fail (highlighted in red). This approach allowsdesigners to immediately see the progressof the design in the spreadsheets, as wellas the impact of any design changes.Floorplanning and PlacementThe constraint and rules-driven methodology of PCB design solutions includesa powerful and flexible set of placement capabilities, including interactiveand automatic. The engineer or designercan assign components or subcircuitsto specific “rooms” during design entryor floor- planning. Components can befiltered and selected by reference designator, device package/footprint style,associated net name, part number, or theschematic sheet/page number.With thousands of components comprising today’s boards, precise managementis critical. Real-time assembly analysisand feedback can facilitate this management—helping designers increaseproductivity and efficiency by placingcomponents according to corporate orEMS guidelines. Dynamic design-forassembly (DFA)-driven placement offersreal-time package-to-package clearancechecking during interactive componentplacement (see Figure 2). Driven from atwo-dimensional spreadsheet array ofclasses and package instances, real-timefeedback provides minimum clearancerequirements. Based on the package’sside-to-side, side-to-end, designers cansimultaneously place devices for optimum routability, manufacturability, andsignal timing.Placement ReplicationSuperior placement replication technologywithin Allegro PCB Designer allows usersto quickly place and route multiple similarcircuits in a design. It allows users to createa template using one instance of placedand routed circuit that can be applied toother instances within the design. Thesaved placement template can be usedwith other designs where similar circuitsare used. When replicating placement,users can flip or mirror the circuit from toplayer to bottom layer. All associated etchelements, including blind buried vias, aremapped to correct layers when circuit ismoved from top layer to bottom layer.Display and VisualizationThe built-in 3D viewer is available in allPCB Editor products. The 3D environmentsupports several filtering options, cameraviews, graphic display options such assolid, transparency and wireframe, andmouse-driven controls for pan, zoom, andspinning the display. 3D viewing also supports the display of complex via structuresor isolated sections of the board. Multipledisplay windows can be opened using thecontext sensitive command structure, and3D images can be captured and saved inJPEG format. (see Figure 3.)The flipboard capability “flips” the designabout its Y axis inverting the design database in the canvas. This “flip” reorganizesthe display of the design such that whatwas displayed as top through to bottombecomes bottom through to top. Havinga true bottom side view from within theCAD system is essential for hardware2
Cadence Allegro PCB Design SolutionViewer. The ODB data format createsaccurate and reliable manufacturing datafor high-quality Gerberless manufacturing.High-Speed DesignIncreasing use of standards-basedadvanced interfaces such as DDR3, DDR4,PCI Express, USB 3.0 are bringing a set ofconstraints that must be adhered to whileimplementing a PCB.Figure 3: Built-in 3D viewer allows reviewing of a section of the board or complex via structureswith pan, zoom, rotation and spinning to reduce iterations with mechanical design teams or PCBfabricators without introducing errorsengineers when debugging a board in thelab, or for assembly/test engineers on themanufacturing floor. Flipboard is not justlimited to viewing; design edits can alsobe performed while in this mode.Interactive Etch EditingThe routing feature of the PCB editorprovides powerful, interactive capabilities that deliver controlled automation tomaintain user control, while maximizingrouting productivity. Real-time, shapebased, any-angle, push/shove routingenables users to choose from “shovepreferred,” “hug-preferred,” or “hugonly” modes.ing traces with curves that are aligned tocontour of the flex portion of the design.(See Figure 4.)PCB ManufacturingA full suite of phototooling, bare-boardfabrication, and test outputs, includingGerber 274x, NC drill, and bare-board testin a variety of formats, can be generated.More importantly, Cadence supports theindustry initiative toward Gerberless manufacturing through its Valor ODB interface that also includes the Valor UniversalAllegro PCB Designer through itsHigh-Speed Option makes adhering toconstraints on advanced interfaces quickand easy. It offers an extensive range ofelectrical rules to ensure that the PCBdesign implementation is complaint withthe specification for advanced interfaces.Additionally, it allows users to extend therules through the use of formulas withexisting rules or post-route data such asactual trace lengths.MiniaturizationConstraint-Driven HDI Design FlowWith BGA pin pitches decreasing tobelow 1mm—0.8mm or lower with 0.65or 0.5mm pin pitches—users are forcedto implement a buildup PCB technologyusing high-density interconnect (HDI).While miniaturization is not necessarily the primary objective in many marketsegments, the move to buildup technol-During etch editing, the designer can viewa real-time, graphical heads-up display ofhow much timing slack remains for interconnect that has high-speed constraints.Interactive routing also enables grouprouting on multiple nets and interactivetuning of nets with high-speed length ordelay constraints.Multi-Line RoutingMulti-line routing allows users to quicklyroute multiple lines as a group on thePCB. Coupled with “hug-contour” option,this utility can help designers routemultiple lines on the flex portion of therigid-flex design in minutes instead ofhours with traditional one trace at a time.Hug-contour option takes care of insert-www.cadence.comFigure 4: Multi-line routing with contour hug option accelerates through no-click routing on flexsection of the PCB designs3
Cadence Allegro PCB Design SolutionAnalog/RF Designogy is necessary for fanning out a BGA—particularly if it has three or four rows ofpins on each side.The Allegro PCB Designer through itsMiniaturization Option offers a provenconstraint-driven HDI design flow witha comprehensive set of design rules forall different styles of HDI designs, froma hybrid buildup/core combination to acomplete buildup process like ALIVH.In addition, it includes automation foradding HDI to shorten the time to createdesigns that are correct-by-construction.Figure 5: Dynamic fileting during etch editingshaves significant time from manufacturingprep phaseEmbedded ComponentsReducing end product size can be accomplished in many different ways. One of theapproaches PCB designers are taking is toembed packaged components on innerlayers. Allegro PCB Designer through itsMiniaturization Option offers constraintdriven embedded component placementand routing. It supports traditional directattach as well as new indirect-attach techniques. Additionally it offers the ability tocreate and manage cavities on layers specified for embedding components.Design Planning and RoutingHighly constrained, high-density designsdominated by bussed interconnect cantake significant time to strategically planand route. Compound this with thedensity issues of today’s components,new signaling levels, and specific topologyrequirements—and it’s no wonder thattraditional CAD tools and technologiesfall short of capturing a designer’s specificrouting intent and acting upon it. TheGlobal Route Environment provides thetechnology and methodology to captureas well as adhere to a designer’s intent.Through the interconnect flow planningarchitecture and the global route engine,users can for the first time put their experience and design intent into a tool thatunderstands what they want—natively.Users create abstracted interconnect data(through the interconnect flow planningarchitecture) and can quickly converge ona solution and validate it with the globalroute engine. The interconnect abstraction reduces the number of elements thesystem has to deal with—from potentiallywww.cadence.comtens of thousands down to hundreds—resulting in a significant reduction in themanual interaction required.Using the abstracted data, the planningand routing process can be acceleratedby providing a visual/spatial map of theopen area in relation to the data and theuser’s design intent. The route engine canthen deal with the details of the routing,adhering to the specified intent, without the user having to both visualize andsolve the interconnect problems at once.This significant simplification over currentdesign tools means users converge on asuccessful interconnect solution far fasterand more easily than ever before, reducing design cycle time through increasedefficiency and productivity. (See Figure 6.)The Allegro PCB Designer through itsAnalog/RF Design Option offers a mixedsignal design environment, from schematic to layout with back annotation,proven to increase RF design productivityup to 50%. It allows engineers to create,integrate, and update analog/ RF/ microwave circuits with digital/analog circuitsin the Allegro PCB Design environment.With its rich layout capability and powerful interfaces with RF simulation tools, itallows engineers to start RF design fromAllegro Design Authoring, Allegro PCBDesigner, or Agilent ADS.Concurrent Team DesignGlobally dispersed design teams are onthe rise, which compounds the challengeof shortening design cycle times. Manualworkarounds that address multi-userissues are time-consuming, slow, andprone to error.Allegro PCB Design Partitioning technology provides a multi-user, concurrentdesign methodology for faster time tomarket and reduced layout time. Multipledesigners working concurrently on alayout share access to a single database,regardless of team proximity. Designerscan partition designs into multiplesections or areas for layout and editingby several design team members.Designs can be partitioned vertically(sections) with soft boundaries or horizontally (layers). As a result, each designercan see all partitioned sections andFigure 6: Allegro Interconnect Flow Planner technology allows users reduce layer counts andshorten design cycle through design planning4
Cadence Allegro PCB Design Solutionupdate the design view for monitoringthe status and progress of other users’sections. Such partitioning can dramatically reduce over-all design cycles andaccelerate the design process.PCB Autorouter TechnologyPCB routing technologies are tightly integrated with the PCB editor. Through thePCB Router interface, all design informationand constraints are automatically passedfrom the PCB editor. Once the route iscompleted, all route information is automatically passed back to the PCB editor.Increased design complexity, density,and high-speed routing constraints makemanual routing of PCBs difficult andtime-consuming. The challenges inherent in complex interconnect routing arebest addressed with powerful, automatedtechnology. The robust, productionproven autorouter includes a batch routing mode with extensive user-definedrouting strategy control as well as built-inautomatic strategy capabilities.DFM Rules-Driven AutoroutingThe design for manufacturing capability within Allegro PCB Router significantly improves manufacturing yields.Manufacturing algorithms provide aspreading capability that automaticallyincreases conductor clearances on aspace-available basis. Automatic conductor spreading helps improve manufactuability by repositioning conductors tocreate extra space between conductorsand pins, conductors and SMD pads, andadjacent conductor segments. Users gainthe flexibility to define a range of spacingvalues or to use the default values.Mitered corners and test points can beadded throughout the routing process.The manufacturing algorithms automatically use the optimal setback range,www.cadence.comstarting from the largest to the smallestvalue. Test point insertion automaticallyadds testable vias or pads as test points.Testable vias can be probed on the front,back, or both sides of the PCB, supporting both single side and clamshell testers.Designers have the flexibility to select thetest point insertion methodology thatconforms to their manufacturing requirements. Test points can be “fixed” to avoidcostly test fixture modifications. Test pointconstraints include test probe surfaces, viasizes, via grids, and minimum center-tocenter distance.High-Speed Constraints-DrivenAutoroutingHigh-speed routing constraints and algorithms handle differential pairs, net scheduling, timing, crosstalk, layer set routing,and the special geometry requirementsdemanded by today’s high-speed circuits.The autorouting algorithms intelligentlyhandle routing around or through vias,and automatically conform to definedlength or timing criteria. Automatic netshielding is used to reduce noise on noisesensitive nets. Separate design rules maybe applied to different regions of thedesign; for example, you can specify tightclearance rules in the connector area of adesign and less stringent rules elsewhere.Cadence Services and Support Cadence application engineers cananswer your technical questions bytelephone, email, or Internet—they canalso provide technical assistance andcustom training Cadence certified instructors teachmore than 70 courses and bring theirreal-world experience into the classroom More than 25 Internet LearningSeries (iLS) online courses allow youthe flexibility of training at your owncomputer via the Internet Cadence Online Support gives you 24x7online access to a knowledge base ofthe latest solutions, technical documentation, software downloads, and moreFor More InformationContact Cadence sales at 1.800.746.6223or visit www.cadence.com for additionalinformation. To locate a Cadence salesoffice or channel partner in your area, visitwww.cadence.com/contact us.Operating System SupportAllegro Platform Technology: Sun Solaris Linux IBM AIX WindowsOrCAD Technology: Windows5
Cadence Allegro PCB Design SolutionAllegro PCB Designer Base Plus Options FeaturesFeatureAllegro PCB DesignerAllegro Design Authoring Allegro Design Entry CIS Constraint-Manager: Physical, spacing and samenet rules Constraint Manager: Properties and DRCs Constraint Manager: Differential pair rules Constraint Manager: Region rules Floorplanning, placement, placement replication DFA, DFF, DFT Dynamic feedback on DFA compliance during placement IDF3.0, DXF in/out EDMD schema-based ECAD-MCAD co-design Native 3D viewer Hierarchical interconnect flow planning Length-based rules for high-speed signals Constraint-driven flow for length-based high-speed signals Match groups, layer sets, extended nets T-point rules (pin to T-point) 6-layer automatic shape-based autorouter High-speed rules-based autorouting Layer-specific rules-based autorouting Design planning - plan spatial feasibility analysis and feedbackDesign Planning OptionDesign planning - generate topological planDesign Planning OptionDesign planning - Convert Topological plan to traces (CLINES)Design Planning OptionConstraint Manager: Electrical rule set (relection, timing, crosstalk)PCB High-Speed OptionConstraint-driven flow using electrical rulesPCB High-Speed OptionElectrical constraint rule set (ECSets) / topology applyPCB High-Speed OptionFormula and relationship based (advanced) constraintsPCB High-Speed OptionBackdrillingPCB High-Speed OptionDie2Die pin delay, dynamic phase control, Z-axis delayPCB High-Speed OptionReturn path management for critical signalsPCB High-Speed OptionConstraint Manager: HDI rule setMiniaturization OptionMicro-via and associated spacing, stacking, and via-in-pad rulesMiniaturization OptionConstraint-driven HDI design flowMiniaturization OptionManufacturing rule support for embedding componentsMiniaturization OptionEmbedd components on inner layersMiniaturization OptionHDI micro-via stack editingMiniaturization OptionDynamic shape-based filleting, line fattening, and trace filletingMiniaturization OptionHug contour routing (Flex)Miniaturization OptionSupport for cavities on inner layersMiniaturization OptionConcurrent team design - layer by layer partitioningPCB Team Design OptionConcurrent team design - functional block partitioningPCB Team Design OptionConcurrent team design - team design dashboardPCB Team Design OptionConcurrent team design - soft netsPCB Team Design OptionParameterized RF etch elements editingPCB Analog / RF OptionAsymmetrical clearancesPCB Analog / RF OptionBi-directional interface with Agilent ADSPCB Analog / RF OptionImport Agilent ADS schematics into DE-HDLPCB Analog / RF OptionLayout-driven RF design creationPCB Analog / RF OptionFlexible Shape EditorPCB Analog / RF Optionwww.cadence.com6
Cadence Allegro PCB Design SolutionFeatureAllegro PCB Designer256-layer AutoroutingPCB Routing OptionDFM rules-based autoroutingPCB Routing OptionAutomatic trace spreadiingPCB Routing OptionATP generationPCB Routing OptionLayer-specific rules-based autoroutingPCB Routing OptionCadence is transforming the global electronics industry through a vision called EDA360.With an application-driven approach to design, our software, hardware, IP, and services helpcustomers realize silicon, SoCs, and complete systems efficiently and profitably. www.cadence.com 2011 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, and Allegro are registered trademarks of Cadence DesignSystems, Inc., All rights reserved.22173 05/11 MP/MV/DM/PDF
Cadence Allegro PCB Design Solution Allegro PCB Designer is a scalable, proven PCB design environment that addresses technological and method-ological challenges while making the design cycles shorter and predictable. Available in base plus options configuration, the PCB design solution contains everything needed to create a PCB layout with a .
