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DATASHEETAllegro PCB Design SolutionManaging complexity for faster, more cost-effective implementationsSystems companies are impacted by new devices and design methodologies offered by thesemiconductor industry. New devices often bring more challenges, like increasing pin countspackaged in shrinking pin pitch ball grid arrays (BGAs). Additionally, new devices use evolvingstandards-based interfaces, such as DDR3, DDR4, PCI Express (PCIe ) Gen3, USB 3.0, andothers, that may require learning new ways to implement them on the board. Coupled withthese increasingly complex technologies is the desire by companies to differentiate theirofferings and get them to market faster, cheaper, with more functionality and in reduced endproduct size. As a result, many companies now outsource to or partner with companies inlow-cost geographies. To manage such increasing complexities, PCB designers need asolution that addresses their technological and methodological challenges.Allegro PCB Design SolutionCadence Allegro PCB Designer is a scalable, proven PCBdesign environment that addresses technological andmethodological challenges while making the design cyclesshorter and predictable. Available in base plus optionsconfiguration, the PCB design solution contains everythingneeded to create a PCB layout with a fully integrateddesign flow. The base—Allegro PCB Designer—includes acommon, consistent constraint management solution,PCB Editor, an auto-interactive router, as well as interfaces for manufacturing and mechanical CAD. PCB Editorprovides a complete placement and routing environment—from basic floorplanning, placement, and routing toplacement replication and advanced interconnectplanning—for simple to complex PCB designs. BenefitsfOffers a proven, scalable, cost-effective PCB editing androuting solution in on-demand base plus options configurationfEliminates unnecessary iterations through constraintdriven PCB design flowfSupports a comprehensive rule set for physical, spacing,design for fabrication (DFF), design for assembly (DFA),and design for test (DFT), high-density interconnect(HDI), and electrical (high-speed) domainsfFeatures a common, consistent constraint-managementsystem for creation, management, and validation ofconstraints from front to backfOpen environment for third-party application improvesproductivity while providing access to best-of-breedintegrated point tools
Allegro PCB Design SolutionPCB Editor TechnologyConstraint-Driven PCB Editing EnvironmentAt the heart of Allegro PCB Designer is a PCB Editor—anintuitive, easy-to-use, constraint-driven environment forcreating and editing simple to complex PCBs. Its extensivefeature set addresses a wide range of design and manufacturability challenges:fA powerful set of floorplanning and placement toolsincluding placement replication for acceleratingplacement of the designfPowerful shape-based shove, hug interactive etchcreation, editing establishes a highly productiveinterconnect environment while providing real-time,heads-up displays of length and timing marginsfDynamic shape capability offers real-time copper pourplowing and healing functionality during placement androuting iterationsThe PCB Editor can also generate a full suite ofphototooling, bare-board fabrication, and test outputs,including Gerber 274x, NC drill, and bare-board test in avariety of formats.constraint sets as graphical topologies that act aselectronic blueprints of an ideal implementation strategy.Once they exist in the database, constraints can drive theplacement and routing processes for constrained signals.The constraint management system is completelyintegrated with the PCB Editor, and constraints can bevalidated in real time as the design process proceeds. Theresult of the validation process is a graphical representationof whether constraints pass (highlighted in green) or fail(highlighted in red). This approach allows designers toimmediately see the progress of the design in the spreadsheets, as well as the impact of any design changes.Floorplanning and PlacementThe constraint and rules-driven methodology of PCBdesign solutions includes a powerful and flexible set ofplacement capabilities, including interactive and automatic.The engineer or designer can assign components or subcircuits to specific “rooms” during design entry or floorplanning. Components can be filtered and selected byreference designator, device package/footprint style,associated net name, part number, or the schematic sheet/page number.With thousands of components comprising today’s boards,precise management is critical. Real-time assemblyanalysis and feedback can facilitate this management—helping designers increase productivity and efficiency byplacing components according to corporate or EMS guidelines. Dynamic DFA-driven placement offers real-timepackage-to-package clearance checking during interactivecomponent placement (see Figure 2). Driven from a two-dimensional spreadsheet array of classes and packageinstances, real-time feedback provides minimum clearancerequirements. Based on the package’s side-to-side,side-to-end, designers can simultaneously place devicesfor optimum routability, manufacturability, andsignal timing.Figure 1: Allegro PCB design solution brings together allthe tools needed to design simple-to-complex PCBsConstraint ManagementA constraint management system dis- plays physical/spacing and high-speed rules along with their status(based on the current state of the design) in real time and isavailable at all stages of the design process. Eachworksheet provides a spreadsheet interface that enablesusers to define, manage, and validate the different rules in ahierarchical fashion. With this powerful application,designers can graphically create, edit, and reviewwww.cadence.comFigure 2: DFA rules-driven placement allows for compactplacement of components without introducing errors2
Allegro PCB Design SolutionPlacement ReplicationInteractive Etch EditingSuperior placement replication technology within AllegroPCB Designer allows users to quickly place and routemultiple similar circuits in a design. It allows users to create atemplate using one instance of placed and routed circuit thatcan be applied to other instances within the design. Thesaved placement template can be used with other designswhere similar circuits are used. When replicating placement,users can flip or mirror the circuit from top layer to bottomlayer. All associated etch elements, including blind buriedvias, are mapped to correct layers when circuit is movedfrom top layer to bottom layer.The routing feature of the PCB Editor provides powerful,interactive capabilities that deliver controlled automation tomaintain user control, while maximizing routing productivity. Real-time, shape- based, any-angle, push/shoverouting enables users to choose from “shove- preferred,”“hug-preferred,” or “hug- only” modes.Display and VisualizationThe built-in 3D viewer is available in all PCB Editor products.The 3D environment supports several filtering options,camera views, graphic display options such as solid, transparency, and wireframe, and mouse-driven controls forpan, zoom, and spinning the display. 3D viewing also supports the display of complex via structures or isolatedsections of the board. Multiple display windows can beopened using the context sensitive command structure,and 3D images can be captured and saved in JPEG format.(See Figure 3.)Figure 3: Built-in 3D viewer allows reviewing of a section ofthe board or complex via structures with pan, zoom, rotation,and spinning to reduce iterations with mechanical designteams or PCB fabricators without introducing errorsThe flipboard capability “flips” the design about its Y axisinverting the design data- base in the canvas. This “flip”reorganizes the display of the design such that what wasdisplayed as top through to bottom becomes bottomthrough to top. Having a true bottom side view from withinthe CAD system is essential for hardware engineers whendebugging a board in the lab, or for assembly/testengineers on the manufacturing floor. Flipboard is not justlimited to viewing; design edits can also be performed whilein this mode.www.cadence.comDuring etch editing, the designer can view a real-time,graphical heads-up display of how much timing slackremains for inter- connect that has high-speed constraints.Interactive routing also enables group routing on multiplenets and interactive tuning of nets with high-speed lengthor delay constraints.Multi-Line RoutingMulti-line routing allows users to quickly route multiple linesas a group on the PCB. Coupled with “hug-contour” option,this utility can help designers route multiple lines on theflex portion of the rigid-flex design in minutes instead ofhours with traditional one trace at a time. Hug-contouroption takes care of inserting traces with curves that arealigned to contour of the flex portion of the design. (SeeFigure 4.)Figure 4: Multi-line routing with contour hug optionaccelerates through no-click routing on flex sectionof the PCB designsDesign Planning OptionHighly constrained, high-density designs dominated bybussed interconnect can take significant time to strategically plan and route. Compound this with the density issuesof today’s components, new signaling levels, and specifictopology requirements—and it’s no wonder that traditionalCAD tools and technologies fall short of capturing adesigner’s specific routing intent and acting upon it. TheAllegro PCB Designer Design Planning Option provides thetechnology and methodology to capture as well as adhere3
Allegro PCB Design Solutionto a designer’s intent. Through the interconnect flowplanning architecture and the global route engine, userscan for the first time put their experience and design intentinto a tool that understands what they want—natively.ends. AiBT can be used with the new, Split View, andBundle Sequence commands to dramatically shorten thetime required to develop a high-quality and properlyordered breakout solution (see Figure 6).Users create abstracted interconnect data (through theinterconnect flow planning architecture) and can quicklyconverge on a solution and validate it with the global routeengine. The interconnect abstraction reduces the numberof elements the system has to deal with—from potentiallytens of thousands down to hundreds—resulting in a significant reduction in the manual interaction required.Using the abstracted data, the planning and routingprocess can be accelerated by providing a visual/spatialmap of the open area in relation to the data and the user’sdesign intent. The route engine can then deal with thedetails of the routing, adhering to the specified intent,without the user having to both visualize and solve theinterconnect problems at once. This significant simplification over current design tools means users converge on asuccessful interconnect solution far faster and more easilythan ever before, reducing design cycle time throughincreased efficiency and productivity. (See Figure 5.)Figure 6: Split View allows working on both endsof a zoomed-in interfaceHigh-Speed OptionIncreasing use of standards-based advanced interfacessuch as DDR3, DDR4, PCIe, USB 3.0 are bringing a set ofconstraints that must be adhered to while implementing aPCB.Figure 5: The Design Planning Option allows users reduce layercounts and shorten design cycle through design planningGetting routes out of dense BGAs is increasingly difficultfor PCB designers. With increasing pin counts and shrinkingpin pitches, the time PCB designers spend on gettingroutes in and out of BGAs has gone up significantly. Thetraditional approach of performing breakouts first thenrouting the traces between two BGAs is running out ofsteam because resolving the resulting crossovers takes upa lot of time and board real estate.AiBTAuto-interactive Breakout Technology (AiBT) improves userefficiency by allowing users to plan to break out on bothwww.cadence.comThe Allegro PCB Designer High-Speed Option makesadhering to constraints on advanced interfaces quick andeasy. It offers an extensive range of electrical rules toensure that the PCB design implementation is complaintwith the specification for advanced interfaces. Additionally,it allows users to extend the rules through the use offormulas with existing rules or post-route data such asactual trace lengths.The High-Speed Option allows users to apply a topology to aset of signals. A topology can include a set of routing preferences as well as constraints such as putting the terminationresistor closer to either the driver or a receiver on a signal.The constraint-driven PCB design system then providesfeedback through the constraint manager if a signal doesn’tconform to the topology or the rules associated with thetopology, ensuring that issues are identified (and thereforecan be addressed) as quickly as possible.The High-Speed Option also enables checking of delaysthrough vias, connector pins, and IC package-pin fordie2die length/delay matching. It includes, utilities toidentify trace segments crossing voids (return path issues4
Allegro PCB Design Solutionthat cause re-spins), supports back drilling (remove throughhole antennas) as well as provides a timing environmentthat can accelerate timing closure of critical nets up to60-70%.Accelerated Timing ClosureAs the data rates increase and supply voltages decrease intoday’s advanced interfaces like DDR3/DDR4, PCIe, SATA,etc., PCB designers must spend more time to ensure signalsin an interface meet timing requirements. With increasingdensity on PCBs, the effort to get to timing closure—ensuring all signals meet timing requirements—can increasesignificantly. PCB designers need new tools to meet thisincreasingly complex challenge.AiDTDelay tuning for signals for interfaces like DDRx takes uptoo much time when using traditional, manual methods.AiDT automatically generates tuning patterns on a user-selected routed byte lane or interface based on user-definedtiming constraints and tuning parameters. AiDT computesthe required length for the connections to meet timingconstraints and utilizes controlled push/shove techniqueswhen adding tuning patterns (see Figure 7).Timing VisionTiming Vision is an innovative and unique environment thatallows users to graphically see real-time delay and phaseinformation directly on the routing canvas. Traditionally,evaluating current status of timing/length of a routedinterface requires numerous trips to Constraint Managerand/or use of the Show Element command. Using anembedded route engine to evaluate complex timingconstraints and interdependencies amongst signals showscurrent status of a set of routed signals—a DDRx byte laneor a complete DDRx interface—via custom trace/connectline coloring; stipple patterns and customized data tipinformation to define the delay problem in the simplestterms possible.With the embedded route engine, Timing Vision providesreal-time feedback to the user during interactive editingand enhances the user’s ability to develop a strategy forresolving timing on large buses or interfaces such as DDRx,PCIe, etc. Coupled with Auto-interactive Phase Tuning(AiPT) and Auto-interactive Delay Tuning (AiDT) capabilities, users can accelerate the time to tune advanced interfaces like DDRx in one-third the time it takes to do itmanually using traditional methods.AiPTDifferential pairs in an interface like DDRx require designersto match static as well as dynamic phase. Matching phasefor all differential pairs in an interface is a necessary firststep before tuning and matching the rest of the signals.AiPT automatically matches dynamic and static phase forthe selected differential pairs. It works with a set of parameters that allows the user several options for trace lengthening or shortening as well as pad entry/exit options. WithAiPT, users can significantly shorten the time to matchstatic and dynamic phases for differential pairs.www.cadence.comFigure 7: AiDT shortens time to tune high-speed signalsby 50% or more.BackdrillingThe High-Speed Option allows users to specify which viason critical high-speed signals should be back drilled toavoid reflections. An output report—Backdrill NC andLegend Files from Bottom, Top, or Any Layer if backdrillingthe inner core(s) of the PCB—allows users to sendbackdrilling instructions to their PCB manufacturersManufacturing OptionThe Allegro PCB Designer Manufacturing Option provides acomprehensive, powerful, easy-to-use suite of tools thatmakes it efficient and cost effective for PCB designers tostreamline the development of release-to-manufacturingpackages for their products. It includes three modules:Design for Manufacturing (DFM) Checker, DocumentationEditor, and Panel Editor.5
Allegro PCB Design SolutionDFM CheckerThe Manufacturing Option’s DFM Checker module isdesigned for engineers and designers who appreciate thebenefits of manufacturing analysis and want to conduct itin a robust environment, with ease and sensibility at anyphase of the PCB design process. DFM Checker offerscomprehensive analysis for all major PCB design tools,Gerber files, intelligent manufacturing files, and NC data toensure the content supplied to the manufacturer willminimize costly delays.Documentation EditorThe Manufacturing Option’s Documentation Editor is a PCBdocumentation-authoring tool that intelligently automatesyour documentation creation process to produce complexPCB documentation in a fraction of the time versus traditional methods. Documentation Editor enables you toquickly create the manufacturing drawings that drive PCBfabrication and assembly.Panel EditorThe Manufacturing Option’s Panel Editor module intelligently automates the complex process of panel definitionand documentation, simplifying the design process. Thissolution enables designers to quickly create electronicmanufacturing documents that clearly articulate the panelspecification and instructions for successful fabrication,assembly, and inspection of their designs.Design Data Transfer to ManufacturingA full suite of phototooling, bare-board fabrication, and testoutputs, including Gerber 274x, NC drill, and bare-board testin a variety of formats, can be generated. More importantly,Cadence supports the industry initiative toward Gerber-lessmanufacturing through export and import of design data inIPC-2581 format. The IPC-2581 data is passed in a singlefile that creates accurate and reliable manufacturing datafor high-quality manufacturing. Users have a choice toexport a subset of the design data for protecting their IP.Import of IPC-2581 is intended for overlaying artwork dataon the design for viewing purposes only.Miniaturization OptionConstraint-Driven HDI Design FlowWith BGA pin pitches decreasing to below 1mm, (0.8mm orlower with 0.65mm or 0.5mm pin pitches), users are forcedto implement a buildup PCB technology using HDI.While miniaturization is not necessarily the primaryobjective in many market segments, the move to buildupwww.cadence.comtechnology is necessary for fanning out a BGA— particularlyif it has three or four rows of pins on each side.The Allegro PCB Designer Miniaturization Option offers aproven constraint-driven HDI design flow with a comprehensive set of design rules for all different styles of HDIdesigns, from a hybrid buildup/core combination to acomplete buildup process like ALIVH.In addition, it includes automation for adding HDI to shortenthe time to create designs that are correct by construction.Embedded ComponentsReducing end product size can be accomplished in manydifferent ways. One of the approaches PCB designers aretaking is to embed packaged components on inner layers.The Miniaturization Option offers constraint-drivenembedded component placement and routing. It supportsdirect- and indirect-attach techniques, and supportsembedding components with dual-sided contacts, verticalcomponents, and embedding in dielectric on a two-layerPCB. Additionally it offers the ability to create and managecavities on layers specified for embedding components.Analog/RF OptionThe Allegro PCB Designer Analog/RF Option offers a mixedsignal design environment, from schematic to layout withback annotation, proven to increase RF design productivityup to 50%. It allows engineers to create, integrate, andupdate analog/RF/microwave circuits with digital/analogcircuits in the Allegro PCB Design environment. With its richlayout capability and powerful interfaces with RF simulationtools, it allows engineers to start RF design from AllegroDesign Authoring, Allegro PCB Designer, or KeysightTechnologies Advanced Design System (ADS).Team Design OptionGlobally dispersed design teams are on the rise, whichcompounds the challenge of shortening design cycle times.Manual workarounds that address multi-user issues aretime-consuming, slow, and prone to error.The Allegro PCB Designer Team Design Option provides amulti-user, concurrent design methodology for faster timeto market and reduced layout time. Multiple designersworking concurrently on a layout share access to a singledatabase, regardless of team proximity. Designers canpartition designs into multiple sections or areas for layoutand editing by several design team members. Designs canbe partitioned vertically (sections) with soft boundaries orhorizontally (layers). As a result, each designer can see allpartitioned sections and update the design view formonitoring the status and progress of other users’ sections.Such partitioning can dramatically reduce overall designcycles and accelerate the design process.6
Allegro PCB Design SolutionRouting OptionThe Allegro PCB Designer Routing Option is tightly integratedwith the PCB Editor. Through the Routing Option interface, alldesign information and constraints are automatically passedfrom the PCB Editor. Once the route is completed, all routeinformation is automatically passed back to the PCB Editor.Increased design complexity, density, and high-speedrouting constraints make manual routing of PCBs difficultand time-consuming. The challenges inherent in complexinterconnect routing are best addressed with powerful,automated technology. The robust, production-provenautorouter includes a batch routing mode with extensiveuser-defined routing strategy control as well as built-inautomatic strategy capabilities.DFM Rules-Driven AutoroutingThe design for manufacturing capability within the RoutingOption significantly improves manufacturing yields.Manufacturing algorithms provide a spreading capabilitythat automatically increases conductor clearances on aspace-available basis. Automatic conductor spreadinghelps improve manufactuability by repositioningconductors to create extra space between conductors andpins, conductors and SMD pads, and adjacent conductorsegments. Users gain the flexibility to define a range ofspacing values or to use the default values.Mitered corners and test points can be added throughoutthe routing process. The manufacturing algorithmsautomatically use the optimal setback range, starting fromthe largest to the smallest value. Test point insertionautomatically adds testable vias or pads as test points.Testable vias can be probed on the front, back, or bothsides of the PCB, supporting both single side and clamshelltesters. Designers have the flexibility to select the testpoint insertion methodology that conforms to theirmanufacturing requirements. Test points can be “fixed” toavoid costly test fixture modifications. Test pointconstraints include test probe surfaces, via sizes, via grids,and minimum center-to- center distance.High-Speed Constraints-Driven Autoroutingintelligently handle routing around or through vias, andautomatically conform to defined length or timing criteria.Automatic net shielding is used to reduce noise on noisesensitive nets. Separate design rules may be applied todifferent regions of the design; for example, you can specifytight clearance rules in the connector area of a design andless stringent rules elsewhere.Operating System SupportAllegro Platform Technology:fSun SolarisfLinuxfIBM AIXfWindowsOrCAD Technology:fWindowsCadence Services and SupportfCadence application engineers can answer your technicalquestions by telephone, email, or Internet—they can alsoprovide technical assistance and custom trainingfCadence certified instructors teach more than 70 coursesand bring their real-world experience into the classroomfMore than 25 Internet Learning Series (iLS) onlinecourses allow you the flexibility of training at your owncomputer via the InternetfCadence Online Support gives you 24x7 online access toa knowledge base of the latest solutions, technicaldocumentation, software downloads, and moreFor More InformationFor product sales, support, or additional information onAllegro solutions, visit www.cadence.com/contact us tolocate a Cadence Sales office or channel partner in yourarea.High-speed routing constraints and algorithms handledifferential pairs, net scheduling, timing, crosstalk, layer setrouting, and the special geometry requirements demandedby today’s high-speed circuits. The autorouting algorithmswww.cadence.com7
Allegro PCB Design SolutionAllegro PCB Designer Base Plus Options Featureswww.cadence.comFeatureAllegro PCB DesignerAllegro Design Authoring Allegro Design Entry CIS Constraint Manager: Physical, spacing, and samenet rules Constraint Manager: Properties and DRCs Constraint Manager: Differential pair rules Constraint Manager: Region rules Floorplanning, placement, placement replication DFA, DFF, DFT Dynamic feedback on DFA compliance during placement IDF3.0, DXF in/out EDMD schema-based ECAD-MCAD co-design Native 3D viewer Hierarchical interconnect flow planning Length-based rules for high-speed signals Constraint-driven flow for length-based high-speed signals Match groups, layer sets, extended nets T-point rules (pin to T-point) 6-layer automatic shape-based autorouter High-speed rules-based autorouting Layer-specific rules-based autorouting Design planning - plan spatial feasibility analysis and feedbackDesign Planning OptionDesign planning - generate topological planDesign Planning OptionDesign planning - Convert topological plan to traces (CLINES)Design Planning OptionAuto-interactive Delay TuningHigh-Speed OptionConstraint Manager: Electrical rule set (relection, timing, crosstalk)High-Speed OptionConstraint-driven flow using electrical rulesHigh-Speed OptionElectrical constraint rule set (ECSets) / topology applyHigh-Speed OptionFormula and relationship-based (advanced) constraintsHigh-Speed OptionBackdrillingHigh-Speed OptionDie2Die pin delay, dynamic phase control, Z-axis delayHigh-Speed OptionReturn path management for critical signalsHigh-Speed OptionConstraint Manager: HDI rule setMiniaturization OptionMicro-via and associated spacing, stacking, and via-in-pad rulesMiniaturization OptionConstraint-driven HDI design flowMiniaturization OptionManufacturing rule support for embedding componentsMiniaturization OptionEmbedd components on inner layersMiniaturization OptionHDI micro-via stack editingMiniaturization OptionDynamic shape-based filleting, line fattening, and trace filletingMiniaturization OptionHug contour routing (Flex)Miniaturization OptionSupport for cavities on inner layersMiniaturization OptionConcurrent team design - layer-by-layer partitioningTeam Design OptionConcurrent team design - functional block partitioningTeam Design OptionConcurrent team design - team design dashboardTeam Design Option8
Allegro PCB Design SolutionConcurrent team design - soft netsTeam Design OptionEdit constraints in a partitionTeam Design OptionManage netclasses in a partitionTeam Design OptionParameterized RF etch elements editingAnalog/RF OptionAsymmetrical clearancesAnalog/RF OptionBi-directional interface with Keysight ADSAnalog/RF OptionImport Keysight ADS schematics into DE-HDLAnalog/RF OptionLayout-driven RF design creationAnalog/RF OptionFlexible Shape EditorAnalog/RF Option256-layer autoroutingRouting OptionDFM rules-based autoroutingRouting OptionAutomatic trace spreadiingRouting OptionATP generationRouting OptionLayer-specific rules-based autoroutingRouting OptionCadence is a pivotal leader in electronic design and computational expertise, using its IntelligentSystem Design strategy to turn design concepts into reality. Cadence customers are the world’smost creative and innovative companies, delivering extraordinary electronic products from chipsto boards to systems for the most dynamic market applications. www.cadence.com 2021 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marksfound at www. cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All othertrademarks are the property of their respective owners. 16097 04/21 SA/VY/PDF
Allegro PCB Design Solution Cadence Allegro PCB Designer is a scalable, proven PCB design environment that addresses technological and methodological challenges while making the design cycles shorter and predictable. Available in base plus options configuration, the PCB design solution contains everything needed to create a PCB layout with a .
