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Allegro Sigrity SI / PI OverviewBrad GriffinAllegro Product MarketingFebruary, 20151 2012 Cadence Design Systems, Inc. All rights reserved.
AgendaAllegro Sigrity Signal Integrity Solutions – Allegro SI Base Option Allegro Sigrity SI Base Power-Aware SI Option Serial Link Analysis Option Package Assessment OptionAllegro Sigrity Power Integrity Solutions – Allegro PI Base Options Allegro Sigrity PI Base Signoff and Optimization Option Package Assessment Option2 2012 Cadence Design Systems, Inc. All rights reserved.
Allegro Sigrity Signal Integrity SolutionBase Option Allegro Sigrity SI Base product enables constraint driven design Options for detailed analysis, compliance and 3 2012 Cadence Design Systems, Inc. All rights reserved.
Allegro Sigrity SI – (Base)Allegro Sigrity SI – PA 5700 New product (PA5700) integrating Allegro and Sigrity technology for SI analysis ofPCB, IC Package or SiP designs Enables Constraint Driven Design Layout floorplanning /editing, schematic-level topology exploration and TD SI simulation,constraint development/capture, analysis model library management, design translators SI related ERCs4 2012 Cadence Design Systems, Inc. All rights reserved.
Allegro Sigrity SI and Allegro PCB Editor- Integration7 2012 Cadence Design Systems, Inc. All rights reserved.
Constraint-driven design streamlines finalverification - Enables first-pass success Allegro Sigrity SI integrates with the same constraintmanager used throughout the design process Drive electrical constraints into the design– Validate throughout the design processLogical Design8High Speed Design 2012 Cadence Design Systems, Inc. All rights reserved.Physical Design
Impedance, Coupling, and Trace Reference Check OutputHTML reports, sortabletables, various plots10 2012 Cadence Design Systems, Inc. All rights reserved.
Allegro Sigrity SI Summary:Integrated high-speed design and analysisSummary: Allegro Sigrity SINo manual translation isrequired to analyze selectedsignals from the physical boardor extract them into theSigXplorer module. Analysisresults are reported in thesame constraint manager usedby Allegro PCB Editor.Coupled differential pairs andnets extended through discretecomponents (x-nets) areautomatically identified,analyzed, and/or extracted.11 2012 Cadence Design Systems, Inc. All rights reserved.
Power Aware Memory Interface Design and Analysis Allegro Sigrity SI Base product enables constraint driven design Options for detailed analysis, compliance and assessmentAllegro Sigrity SI Base12 2012 Cadence Design Systems, Inc. All rights reserved.
Power Aware Memory Interface Design and AnalysisKey features of Allegro Sigrity Power-Aware SI Option Allegro Sigrity Power-Aware SI addresses the challenges associated with sourcesynchronous bus design Industry-leading interconnect extraction and power-aware IBIS modelingtechnology includes the non-ideal power and ground effects Concurrent simulation of signal, power, and ground accurately determine Setupand Hold margins Comprehensive, automated JEDEC-based measurements and post-processing Easy-to-use environment featuring popular memory interface compliance kits ishighly integrated with layout allowing engineers to efficiently close on memory interfacetimingNote: Package and Chipextraction technologysold separately fromAllegro Sigrity PowerAware SI Option13 2012 Cadence Design Systems, Inc. All rights reserved.
System level power-aware SI analysis solution PowerSI provides efficient PCB interconnect extraction Integrates with IC and Package– XtractIM Package models drop into topology canvas– XcitePI IO Interconnect models drop into topology canvas MCP (Model Connection Protocol) connects signal, power, and groundacross fabricsExtraction14 2012 Cadence Design Systems, Inc. All rights reserved.ConnectionSimulation
Reflections, Xtalk, SSO Simulated Together Emulates your hardware15 2012 Cadence Design Systems, Inc. All rights reserved.
Automatic Setup & Hold Derating Slew rates measuredon each cycle Derating factor ispulled from table Applied to setup/holdmargins each cycle16 2012 Cadence Design Systems, Inc. All rights reserved.
Automation Raw waveformsmeasured like avirtual oscilloscope Tabulated reports for:––––Waveform qualityEye qualitySetup & holdDelays & skews Criteria plots,waveforms, eyediagrams all linked toHTML reports17 2012 Cadence Design Systems, Inc. All rights reserved.
TimingDesigner Integration with Sigrity Industry’s most complete timing analysis and timing documentation tool nowreads interconnect delay directly from Cadence Sigrity Parallel Bus Analysissolution– Automatically generate timing diagrams from power-aware Sigrity simulation results– TimingDesigner available from EMA Design Automation Graphical timing spreadsheets show full interface timing relationships DDR Timing Spreadsheets enable confirmation of timing closure TimingDesigner and Allegro Sigrity Power Aware SI Option - the industry’s mostcomplete timing analysis and timing reporting solution18 2012 Cadence Design Systems, Inc. All rights reserved.
DDR4/LPDDR4 Support in Power Aware SIOption / SystemSI PBA DDR4/LPDDR4 is faster and lower voltagethan its predecessor Analysis methodology for DDR4 differsfrom its predecessorDDR4 Spec– The Allegro Sigrity Power Aware SI solutionaddress these new requirements New features include– The ability to derive and evaluate DDR4 DQeye masks,– Derive Vref level on-the-fly– Bit error rate (BER) testing– AMI models for equalizationSystemSI-PBA19 2012 Cadence Design Systems, Inc. All rights reserved.
Multi-Gigabit Serial Link Design and Analysis Allegro Sigrity SI Base product enables constraint driven design Options for detailed analysis, compliance and assessmentAllegro Sigrity SI Base20 2012 Cadence Design Systems, Inc. All rights reserved.
Multi-Gigabit Serial Link Design and Analysis Allegro Sigrity Serial Link SI is addressing thechallenges associated with serial link design Industry-leading interconnect extraction technologyprovides an accurate and uniquely integratedsolution for channel modeling, including non-idealpower effects Robust frequency and time domain simulationtechnology is combined with statistical techniquesfor advanced multi-gigabit channel analysis Industry-leading IBIS-AMI modeling expertiseenables advanced channel simulation withalgorithmic equalization modeling (ex. FFE, DFE .) Automated eye diagram and bathtub generation forBit Error Rate (BER) analysis22 2012 Cadence Design Systems, Inc. All rights reserved.
Allegro Sigrity Serial Link SI – Serial Link Analysis Provides a comprehensive environment for design and accurateassessment of high speed serial links to ensure robust IC package andPCB implementations23 2012 Cadence Design Systems, Inc. All rights reserved.
Sweep Manager Enables sweeping of key parameters:––––24Jitter/Noise settingsEqualization parametersChannel interconnect modelsSubcircuit parameters 2012 Cadence Design Systems, Inc. All rights reserved.
Interface Compliance Flow 25 2012 Cadence Design Systems, Inc. All rights reserved.
Interface compliance ResultsPrintout readyHyperlinked tocurves for easyaccessInsertion LossEye MaskReturn LossJitter tolerance26 2012 Cadence Design Systems, Inc. All rights reserved.
Allegro Sigrity Serial Link Solution is Power Aware27 2012 Cadence Design Systems, Inc. All rights reserved.
New compliance kits for popular Serial interfaces Compliance kits– USB 3.0 and MIPI-M30 2012 Cadence Design Systems, Inc. All rights reserved.
HDMI 2.0 Compliance Kit Adding HDMI 2.0(up to 6Gbps)compliance kit toexisting HDMI 1.4bversion Adding support for“TP2” compliancechecks31 2012 Cadence Design Systems, Inc. All rights reserved.
Allegro Sigrity Package Assessment and Model Extraction– IC Package Design and Analysis Allegro Sigrity SI Base product enables constraint driven design Options for detailed analysis, compliance and assessmentAllegro Sigrity SI Base32 2012 Cadence Design Systems, Inc. All rights reserved.
Package Assessment and Model Extraction Common environment between layout and analysis– Issues can be resolved easily– All design data is available for analysis tools– No limitations that may exist translating from manufacturing data (ODB )33 2012 Cadence Design Systems, Inc. All rights reserved.
Running XtractIM from Allegro Sigrity SI Base Package Analyzeoption enablesXtractIM integration34 2012 Cadence Design Systems, Inc. All rights reserved.
Automatic Translation to XtractIM (.mcm to .spd) Package database is translated into SPD in ASI beforerunning XtractIM35 2012 Cadence Design Systems, Inc. All rights reserved.
XtractIM Running from Allegro Sigrity SIEdits can be made in base tool and quickly investigated in XtractIM36 2012 Cadence Design Systems, Inc. All rights reserved.
Detailed Full Wave 3D Extraction FlowAutomated cutting of 3D regions with PowerSI 3D-EM38 2012 Cadence Design Systems, Inc. All rights reserved.
Solution AccuracyMeasurement BenchmarkTwo long traces with viastubs in a 28-layer boardS11S12Red : measurementBlue : PSI-3D EM39 2012 Cadence Design Systems, Inc. All rights reserved.
PowerSI 3D EMLow Frequency Solution Stability and AccuracyResistanceInductance40 2012 Cadence Design Systems, Inc. All rights reserved.
Package Partitioning Approach Accelerates thetime to create full Package Models with 3D-EM XtractIM (Hybrid Solver) iseffective on multi-layer packageswith power and ground planes Lower cost packages may not be“plane rich” but still requireaccurate modeling 3D Full-wave can provide a fullpackage model by partitioning thepackage and solving each partition Individual simulation results arecombined together to generate a wholepackage RLC table and SPICE model.Get each net’s strong neighborsby Hybrid -SolverDivide package to groups of SPDfiles for 3DEM3DEM-extraction for individual SPDfilesCombine individual result intowhole package RLC41 2012 Cadence Design Systems, Inc. All rights reserved.
Allegro Sigrity Signal Integrity SolutionBase Option Allegro Sigrity SI Base product enables constraint driven design Options for detailed analysis, compliance and 42 2012 Cadence Design Systems, Inc. All rights reserved.
AgendaAllegro Sigrity Signal Integrity Solutions – Allegro SI Base Option Allegro Sigrity SI Base Power-Aware SI Option Serial Link Analysis Option Package Assessment OptionAllegro Sigrity Power Integrity Solutions – Allegro PI Base Options Allegro Sigrity PI Base Signoff and Optimization Option Package Assessment Option43 2012 Cadence Design Systems, Inc. All rights reserved.
Allegro Sigrity Power Integrity SolutionBase Option Allegro Sigrity PI Base product enables constraint driven PI design Option for cost-performance optimization and detailed analysisAllegro Sigrity PI Base44 2012 Cadence Design Systems, Inc. All rights reserved.
Allegro Sigrity PI – (Base)Allegro Sigrity PI – PA 5800 New product (PA5800) integrating Allegro and Sigrity technology forPI analysis of PCB, IC Package or SiP designs Sigrity engines will be called for analysis IR Drop analysis (as part of PI Base license) OptimizePI (as part of Signoff & Optimization option) Enables Constraint Driven Design Integrated solution for layout and analysis Target users Mostly layout designers Some hardware engineers A few SI engineers45 2012 Cadence Design Systems, Inc. All rights reserved.
For PCB Designers, IC Package Designers, and Power Integrityengineers needing to perform a quick scan of a design forpotential power integrity issues Constraint driven flowassociated decouplingcapacitors withcomponents Constraint templatesadvise layout designer oncapacitor placement IR Drop analysis providesfeedback regarding planedesign46 2012 Cadence Design Systems, Inc. All rights reserved.New Power Integrity constraint-drivenflow guides the layout designer ondecoupling capacitor placementPI BaseConstraint Driven Power Integrity designfor PCBs and IC Packages
Key Components of PIBaseFloorplanner Allegro based editor for .brd, .mcm,or .sip Layout editing and routingDC Analysis Sigrity technologywith cross-probingto layoutPower Feasibility Editor New unique constraintdriven DeCap flowConstraint Manager47 2012 Cadence Design Systems, Inc. All rights reserved.
Industry’s First Complete F2B Constraint-DrivenPI Design Process48Design EngineerLayout DesignerPI Engineer Can start at BOMstage Uses new PowerFeasibility Editor forDeCap selection andPI constraint definition Can start atfloorplanning stage First order analysisdirectly on layout Analyze, edit,re-analyze DeCap placementguidance and DRC Can start at any stage Leverages setup anddata from rest of team Signoff capableanalysis 2012 Cadence Design Systems, Inc. All rights reserved.
Allegro Sigrity PI Module An add-on module to Allegro / SiP Layout Designers Available through “Change Editor” Easy to use and integrated analysis for making on-the-fly changes to layoutbased on PI AnalysisAn integrated foundation for Sigrity technologies - Launching of Sigrity products fromlayout environment, automatically passing layout data and setup to Sigrity individualproducts PI Experts may change the design, re-analyze with advance Sigrity PI tools, andsave a local copy of improved designMain Functions : PCB IR drop analysis and current density checks for metal planes, vias and traces Power Feasibility Editor to allow specifications of decoupling capacitor needs andconstraints on decoupling capacitor placements for each IC components Interactive decoupling capacitor placement environment to facilitate layout engineersto place capacitors within specified constraints49 2012 Cadence Design Systems, Inc. All rights reserved.
Allegro Sigrity Power Integrity SolutionOptimization and Signoff Option Signoff option includes industry leading AC Analysis, DC Analysis,and decoupling capacitor optimizationAllegro Sigrity PI Base50 2012 Cadence Design Systems, Inc. All rights reserved.
For Power Integrity engineers requiring AC and DC analysisReduce costs while maximizing PDN performance by selectingthe optimal decoupling capacitors placed in the best location PowerSI for AC analysisIntegrated design and PI Analysis PowerDC for thermallyaware IR Drop analysis OptimizePI for decouplingcapacitor cost/performancetradeoffs 3D-EM for 3D full-wavePDN extraction52 2012 Cadence Design Systems, Inc. All rights reserved.Sign Off andOptimization OptionNew comprehensive Power Integrity Solutionintegrated with PCB and Package Layout
Electrical / Thermal Co-Simulation FlowPowerDCDC Current AnalysisCurrent densityCurrent density isan input for heattransfer analysisHeat Transfer AnalysistemperatureIterationTemperature is aninput for DC currentanalysisBoth electrical resistance andleakage power dissipationincrease at higher temperaturesJoule and componentheating will changetemperature distributionThe first integrated and automated electrical /thermal co-simulation tool in industry53 2012 Cadence Design Systems, Inc. All rights reserved.
Power IntegrityThermally-aware static IR Drop can be performed with an intuitive user interface.Engineers can verify power delivery and signal quality with tools from a single vendor.54 2012 Cadence Design Systems, Inc. All rights reserved.
Optimize power stability through AC power analysis Sigrity Power Integrity technologyperforms AC analysis– Integrated (no manual translation)design and analysis environmenthelps optimize decoupling strategy Frequency domain simulation– Quantify the impedance of the powerdelivery system across the frequencyrange of interest Time domain simulation– Effectiveness of decouplingcapacitor selection and placementcan be verified by measuring andoptimizing ripples in the voltages55 2012 Cadence Design Systems, Inc. All rights reserved.Note: SPEED2000 time domain simulationtechnology sold separately from Allegro SigrityOptimization and Signoff Option
Optimize power delivery through DC power analysis Sigrity Power DC includes static IR dropanalysis– Verifies the power distribution system will providestable and sufficient current to drive signals– Considers trace neck-down, swiss-cheese planes,partial planes– Considers all vias that connect multiple groundplanes of the same net– Results can be viewed graphically or in a textreport– Users can also view relative and absolute voltage drop at anypoint on the net56 2012 Cadence Design Systems, Inc. All rights reserved.
Overview of Allegro Sigrity OptionsPower Aware SIOptionPower IntegrityOptionSerial Link SIOptionPackage Assessment andModel Extraction Option SIGR011 Broadband SPICE SIGR031 CAD Translators SIGR011 Broadband SPICE SIGR031 CAD Translators SIGR021 T2B SIGR051 OptimizePI SIGR021 T2B SIGR201 PowerDC SIGR031 CAD Translators SIGR201 PowerDC SIGR031 CAD Translators SIGR311 3D-EM SIGR301 PowerSI SIGR301 PowerSI SIGR301 PowerSI SIGR801 XtractIM SIGR311 3D-EM SIGR311 3D-EM SIGR311 3D-EM SIGR570 System Explorer SIGR401 SPEED2000 SIGR570 System Explorer SIGR506 SystemSI – SLA II SIGR556 SystemSI – PBA IINote: Each Option is a single user license. Only one of the products listed in each Option can be run at a time57 2012 Cadence Design Systems, Inc. All rights reserved.
Summary Allegro Sigrity SI – a unique full-featuredSI solution– Power-aware Signal Integrity of high speedmemory interfaces is nicely integrated with thedesign environment– Multi-gigabit serial link solution– Algorithmic transceiver model support– Integrated full-wave 3D field solver– High capacity simulation engine accurately predicts BER Allegro Sigrity PI – a unique full-featuredPI solution– Integrated design and power integrity analysis– Constraint driven flow– Same environment for PCB designers and PIexperts58 2012 Cadence Design Systems, Inc. All rights reserved.One-of-a-Kind
59 2012 Cadence Design Systems, Inc. All rights reserved.
reads interconnect delay directly from Cadence Sigrity Parallel Bus Analysis solution -Automatically generate timing diagrams from power-aware Sigrity simulation results -TimingDesigner available from EMA Design Automation Graphical timing spreadsheets show full interface timing relationships DDR Timing Spreadsheets enable confirmation of timing closure TimingDesigner and .
