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Quartus II Version 6.1 HandbookVolume 4: SOPC BuilderPreliminary Information101 Innovation DriveSan Jose, CA 95134(408) 544-7000http://www.altera.comQII5v4-6.1

Copyright 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks andservice marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrantsperformance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to makechanges to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by AlteraCorporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.iiAltera Corporation

ContentsChapter Revision Dates . xiAbout this Handbook. xiiiHow to Contact Altera . xiiiTypographic Conventions . xivSection I. SOPC Builder FeaturesChapter 1. Introduction to SOPC BuilderOverview .Architecture of SOPC Builder Systems .SOPC Builder Components .SOPC Builder Ready Components .User-Defined Components .System Interconnect Fabric .Functions of SOPC Builder .Defining & Generating the System Hardware .Creating a Memory Map for Software Development .Creating a Simulation Model & Testbench .Getting Started .Document Revision History 61–71–7Chapter 2. Tour of the SOPC Builder User InterfaceStarting SOPC Builder . 2–1Starting a New SOPC Builder System . 2–1Working with SOPC Builder Systems . 2–2System Contents Tab . 2–3Adding a Component to the System . 2–5Specifying Connections, Base Address, Clock & IRQ . 2–6Connection Panel . 2–6Table of Active Components . 2–7Creating User-Defined Components . 2–7System Dependency Tabs . 2–8Board Settings Tab . 2–9System Generation Tab . 2–10System Generation Tab Options . 2–11SDK Option . 2–12HDL Option . 2–12Altera CorporationiiiQuartus II Handbook, Volume 4

Quartus II Handbook, Volume 4Simulation Option .Starting System Generation .Other Tools .Preferences .Document Revision History .2–132–142–142–142–16Chapter 3. System Interconnect Fabric for Memory-Mapped InterfacesIntroduction . 3–1High-Level Description . 3–1Fundamentals of Implementation . 3–3Functions of System Interconnect Fabric . 3–3Address Decoding . 3–4Datapath Multiplexing . 3–5Wait-State Insertion . 3–6Pipelining for High Performance . 3–7Pipeline Management . 3–8Endian Conversion . 3–9Native Address Alignment & Dynamic Bus Sizing . 3–10Native Address Alignment . 3–11Dynamic Bus Sizing . 3–12Wider Master . 3–12Narrower Master . 3–12Arbitration for Multimaster Systems . 3–13Traditional Shared Bus Architectures . 3–14Slave-Side Arbitration . 3–15Arbitrator Details . 3–16Arbitration Rules . 3–17Fairness-Based Shares . 3–17Round-Robin Scheduling . 3–18Burst Transfers . 3–19Minimum Share Value . 3–19Setting Arbitration Parameters in the SOPC Builder GUI . 3–20Burst Management . 3–20Clock Domain Crossing . 3–21Description of Clock Domain-Crossing Logic . 3–21Location of Clock Domain Crossing Logic . 3–23Duration of Transfers Crossing Clock Domains . 3–23Implementing Multiple Clock Domains in the SOPC Builder GUI . 3–24Interrupt Controller . 3–25Software Priority . 3–25Hardware Priority . 3–26Assigning IRQs in the SOPC Builder GUI . 3–27Reset Distribution . 3–28Document Revision History . 3–29ivQuartus II Handbook, Volume 4Altera Corporation

ContentsChapter 4. SOPC Builder ComponentsIntroduction . 4–1Sources of Components . 4–1Location of the Component Hardware . 4–2Components That Include Logic Inside the System Module . 4–2Components That Interface to Logic Outside the System Module . 4–3Structure & Contents of a Component Directory . 4–3class.ptf File . 4–3cb generator.pl File . 4–4hdl Directory . 4–5Other Component Files . 4–5Component Directory Location . 4–6Document Revision History . 4–8Chapter 5. Component EditorIntroduction . 5–1Component Editor Output . 5–2Starting the Component Editor . 5–3HDL Files Tab . 5–3Signals Tab . 5–5Naming Signals for Automatic Type and Interface Recognition . 5–6Templates for Interfaces to External Logic . 5–7Interfaces Tab . 5–7SW Files Tab . 5–9Component Wizard Tab . 5–10Identifying Information . 5–10Parameters . 5–11Saving a Component . 5–12Re-Editing a Component . 5–13Document Revision History . 5–14Chapter 6. Archiving SOPC Builder ProjectsIntroduction .Scope .Required Files .SOPC Builder Design Files .Nios II Application Software Project Files .Nios II System Library Project .File Write Permissions .Document Revision History .6–16–16–26–26–36–46–46–4Chapter 7. Board Description EditorIntroduction .Board Descriptions .Uses for Board Descriptions .Board Description Editor .Creating a Board Description .Altera Corporation7–17–17–27–27–4vQuartus II Handbook, Volume 4

Quartus II Handbook, Volume 4Pins Flow . 7–4Steps for the Pins Flow . 7–5Creating a PCB Model from the Netlist . 7–5Flash Flow . 7–8Board Description Editor Output . 7–9Board Description File Structure . 7–9Using Board Descriptions . 7–9Starting the Board Description Editor . 7–10Intro Tab . 7–10Netlist Tab . 7–10Devices Tab . 7–11Device List . 7–12Filtered Nets, Pass Throughs & Device Groups . 7–13Creating Pass Throughs . 7–13Creating Device Groups . 7–14Filtering False Target Devices . 7–15Previewing Pins Visible to the Pin Mapper . 7–15Nets Tab . 7–17Pass Throughs Tab . 7–18Groups Tab . 7–20Flash Memory Tab . 7–21Files Tab . 7–22Board Description Name and Version . 7–23System Template . 7–23Saving & Exiting the Board Description Editor . 7–24Document Revision History . 7–24Chapter 8. Pin MapperIntroduction .Design Flow .Applying Pin Assignments to the Quartus II Project .Pin Name Requirements .Pin Mapper GUI .Source Signals Column .Target Device Column .Target Pin Column .Vector Signals .Differential Signals .Signals with Multiple Destinations .Assign in Quartus II .Pin Mappings Status .Document Revision History .viQuartus II Handbook, Volume 78–78–78–78–8Altera Corporation

ContentsSection II. Building Systems with SOPC BuilderChapter 9. Building Memory Subsystems Using SOPC BuilderIntroduction . 9–1Example Design . 9–2Example Design Structure . 9–2Example Design Starting Point . 9–4Hardware & Software Requirements . 9–5Design Flow . 9–5Component-Level Design in SOPC Builder . 9–6SOPC Builder System-Level Design . 9–7Simulation . 9–7Quartus II Project-Level Design . 9–7Board-Level Design . 9–7Simulation Considerations . 9–7Generic Memory Models . 9–8Vendor-Specific Memory Models . 9–8On-Chip RAM & ROM . 9–9Component-Level Design for On-Chip Memory . 9–9Memory Type . 9–9Size . 9–10Read Latency . 9–10SOPC Builder System-Level Design for On-Chip Memory . 9–10Simulation for On-Chip Memory . 9–10Quartus II Project-Level Design for On-Chip Memory . 9–11Board-Level Design for On-Chip Memory . 9–11Example Design with On-Chip Memory . 9–11EPCS Serial Configuration Device . 9–13Component-Level Design for an EPCS Device . 9–13SOPC Builder System-Level Design for an EPCS Device . 9–14Simulation for an EPCS Device . 9–14Quartus II Project-Level Design for an EPCS Device . 9–14Board-Level Design for an EPCS Device . 9–14Example Design with an EPCS Device . 9–15SDRAM . 9–16Component-Level Design for SDRAM . 9–16SOPC Builder System-Level Design for SDRAM . 9–16Simulation for SDRAM . 9–16Quartus II Project-Level Design for SDRAM . 9–17Connecting & Assigning the SDRAM-Related Pins . 9–17Accommodating Clock Skew . 9–17Board-Level Design for SDRAM . 9–18Example Design with SDRAM . 9–18Off-Chip SRAM & Flash Memory . 9–20Component-Level Design for SRAM & Flash Memory . 9–21Avalon Tristate Bridge . 9–22Flash Memory . 9–23Altera CorporationviiQuartus II Handbook, Volume 4

Quartus II Handbook, Volume 4SRAM .SOPC Builder System-Level Design for SRAM & Flash Memory .Simulation for SRAM & Flash Memory .Quartus II Project-Level Design for SRAM & Flash Memory .Board-Level Design for SRAM & Flash Memory .

Preliminary Information 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com Quartus II Version 6.1 Handbook Volume 4: SOPC Builder