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Electrical and Telecommunications Engineering Technology TCET3122NEW YORK CITY COLLEGE OF TECHNOLOGYThe City University of New YorkDEPARTMENT:Electrical and TelecommunicationsEngineering TechnologySUBJECT CODEAND TITLE:TCET 3122 Switching and Automata TheoryCOURSEDESCRIPTION:REQUIRED:The course covers synchronous state machines. VHDLtechniques are used to cover state transition analysis, synthesisand optimization techniques. VHDL concepts are used todevelop simulation wave-shapes of all the circuits involved. Thecourse involved with the study of combinational networks,counters, shift registers and sequential machines.B.Tech Telecommunication Engineering TechnologyPREREQUISITE:AAS in TCET or department approvalTEXTBOOK:Digital Design with CPLD Applications and VHDLBy Robert Dueck - Second Edition, 2004COURSE OBJECTIVES/ Upon successful completion of this course, studentsOUTCOMES:(ABET STUDENT1. Analyze, simplify, and design Combinational Logic CircuitsOUTCOMES):(ABET Criteria 3d, 3f).2. Describe the structure of several types of ProgrammableLogic Devices-PLDs (ABET Criteria 3a).3. Use Altera’s Quartus II Software to design, simulate, andimplement PLDs (ABET Criteria 3a, 3b, 3d).4. Understand the basics of VHDL and use it in theprogramming of digital systems (ABET Criteria 3a, 3b, 3d).5. Analyze and design Combinational Logic Functions such asDecoders, Encoders, Multiplexers, and Comparators (ABETCriteria 3d, 3f).6. Analyze and design Sequential Logic Circuits such asLatches, Flip-flops, Counters, and shift registers. (ABETCriteria 3d, 3f).7. Understand the concepts of State Machine Design anddevelop Mini-Processors (ABET Criteria 3a, 3b, 3d)8. Understand the electrical characteristics of logic gates,
Electrical and Telecommunications Engineering Technology TCET3122Timing Parameters, and Arithmetic Circuits (ABET Criteria3a).9. Work in a group and gain hands-on experience in the lab bydesigning, implementing, testing and analyzing various logiccircuits in digital systems. (ABET Criteria 3a, 3b, 3c, 3d, 3e)10. Present individual/group technical reports in oral andwritten forms.( ABET Criteria 3e, 3g, 3i, and 3k)TOPICS:Topics include Basic Principles of Digital Systems, Logic Functions andGates, Boolean Algebra and Combinational Logic, Introduction to PLDsand Quartus II, Introduction to VHDL, Combinational Logic Functions,Digital Arithmetic and Arithmetic Circuits, Introduction to SequentialLogic, Counters and Shift Registers, State Machine Design, Logic GateCircuitry.CLASS HOURS:2LAB HOURS:3CREDITS:3Prepared by:Professor H. MarandiFall 2017COURSECOORDINATOR:Professor H. MarandiE-mail: Hmarandi@citytech.cuny.edu(718) 260-5312EXPERIMENTS:DIP Integrated CircuitsExpanding Logic GatesPulsed Operation of Logic GatesBoolean Algebra: SOP FormsBoolean Algebra: DeMorgan Equivalent FormsIntroduction to Quartus IIIntroduction to VHDLBinary DecodersBinary and 7-Segment Decoders in VHDLPriority EncodersMultiplexersContribution of course to meeting the requirements of Criterion 5:
Electrical and Telecommunications Engineering Technology TCET3122TCET3122 meets criterion 5 by providing students with a broad overview of modern techniquesand concepts in the design of digital systems. In particular, programmable logic and VHDL areused as vehicles for teaching digital design for both combinational and sequential digital circuits.Students are taught the theoretical concepts, but also gain practical laboratory skills. Academicbenchmarks, course outcomes, and assessment requirements have been established to ascertainstudent comprehension of concepts and proper usage of hardware and software and laboratorytest equipment by using Altera’s Quartus II CPLD software to design, simulate, and implementvarious digital circuits. Upon successful fostering of critical thinking, communications, andproper environment for teamwork, students develop the necessary skills to solve problems in aclassroom and laboratory environment, which later could serve them in the global job market.GRADING POLICY:Homework and class participationLab Report and PresentationExams and Midterm Exam:Final ExamLetter GradeAAB BBC CDF10%25%40%25%Numerical Grade 76.960-69.959.9 and belowQuality4.03.73.33.02.72.32.01.00.0
Electrical and Telecommunications Engineering Technology TCET3122AssessmentThe following assessment techniques are correlated to the course objectives as follows: Inaddition, each assessment technique incorporates one or more of the following ABETstudent outcomes (ABET Criteria 3a, 3b, 3c, 3d, 3e, 3f, 3g, 3i, 3k ).Course ObjectivesAssessment1. Analyze, simplify, and designcombinational logic circuits.Using Digital Design Software, the studentwill be able to:1.1 Describe the configuration ofseveral basic logic gates in DIPIntegrated Circuits.1.2 Determine how basic logic gatescan be used to enable or inhibittime-varying digital signals byexamining the gate truth tables.1.3 Monitor the pulsed behavior oflogic gates with LEDs and with anoscilloscope.1.4 Use Boolean algebra to simplify alogic gate network and to prove thattwo gate networks are equivalent.1.5 Use DeMorgan equivalent forms oflogic gates to simplify the Booleanexpression of a logic gate network.2.1 Create a project in Quartus II.2.2 Use Quartus Block Editor to entera graphical design in Quartus II.3.1 Compile and simulate the design.3.2 Program an Altera CPLD with theDesign.3.3 Test the design on a CPLD testBoard to determine the truth table.2. Describe the structure of severaltypes of Programmable Logic Devices(PLDs).3. Use Altera’s Quartus II software todesign, simulate, and implement PLDs.4. Understand the basics of VHDL and useit in the programming of digital systems.4.1 Enter a simple combinational logiccircuit in VHDL using the QuartusText Editor.4.2 Assign target device and pinnumbers and compile a VHDLdesign file.4.3 Write simulation criteria for a
Electrical and Telecommunications Engineering Technology TCET31225. Analyze and design CombinationalLogic Functions such as Decoders,Encoders, Multiplexers, and Comparators.6. Analyze and design Sequential LogicCircuits such as Latches, Flip- Flops,Counters, and Shift Registers.VHDL design entity and create aSimulation to verify theCorrectness of the design.5.1 Enter the design for a binarydecoder in Quartus II as aBlock Diagram File.5.2 Create a Quartus II simulation ofa binary decoder.5.3 Enter the design for a binarydecoder in Quartus II as aVHDL design entity.5.4 Use VHDL to create 7-segmentdecoder.5.5 Enter a VHDL design for aBCD priority encoder.5.6 Write simulation criteria forthe BCD priority encoder andcreate a simulation inQuartusII.5.7 Enter the logic circuit of a 4to-1 multiplexer (MUX) as ablock diagram file, usingAltra’s Quartus II CPLDdesign software.5.8 Create a Quartus IIsimulation file for the 4-to-1multiplexer.6.1 Draw circuits, function tables,and timing diagrams of edgetriggered D, JK, and T flipflops.6.2 Use Quartus II to create simplecircuits and simulations with Dlatches and D, JK, and T flipflops.6.3 Use simple latch and flip-flopdesigns using VHDL.6.4 Implement various countercontrol functions, such asparallel load, clear, countenable, and count directionboth in Block Diagram Filesand in VHDL.6.5 Design shift registers, ringcounters, Johnson countersusing the Quartus II simulation
Electrical and Telecommunications Engineering Technology TCET3122tool.7. Understand the concepts of StateMachine Design and develop MiniProcessors.7.1 Describe the components of astate machine.7.2 Distinguish between Moore andMealy implementations of statemachines.7.3 Create simulations in Quartus IIto verify a state machine design.7.4 Design state machineapplications,such as switch debouncer,single- pulse generator, andtraffic light controller.8. Understand the electrical characteristicsof logic gates, Timing Parameters, andArithmetic Circuits.8.1 Derive the logic gate circuits forfull and half adders andsubtractors, given their truthtables.8.2 Draw circuits to perform BCDarithmetic and explain theiroperation.8.3 Use VHDL to program CPLDdevices to perform variousarithmetic functions, such asparallel adders and 1scomplementers.9. Work in a group and gain hands-on9.1 Work together as a member of a
Electrical and Telecommunications Engineering Technology TCET3122experience in lab by designing,implementing, testing and analyzingvarious logic circuits in digital systems.10. Present individual/group technicalreport in oral and written form.group.9.2 Achieve familiarity withequipment used in professionallaboratories9.3 Know how to apply knowledgeto real world problems.9.4 Understand how to design,implement various logic circuitin a practical setting.10.1 Demonstrate writtencommunication competence.10.1 Demonstrate oralcommunication competence.10.3 Meet project/ report deadline.
Electrical and Telecommunications Engineering Technology TCET3122TOPICWEEK1&2 3 4 5 Course outline, lateness,absence, and classroom policyReview of the basic principlesof digital systemsReview of logic functions andgatesDeMorgan equivalent formsReview of Boolean AlgebraDescribe the behavior oftristate buffers.Introduction to Combinationallogic designExplain the relationshipbetween Boolean expression,logic diagram, and truth tableof a logic gate networkWrite sum of products andproduct of sums formsSimplify logic diagrams usingthe Karnaugh map techniqueRedraw a logic diagram usingall-NAND or all-NORimplementationsIntroduction to ProgrammableLogic Devices (PLDs)Introduction to QuartusDesign SoftwareDescribe the structure ofProgrammable Logic Arrays(PALs)Draw fuses on the logicdiagram of a PAL toimplement logic functionsUse Quartus II PLD designsoftware to enter simplecombinational circuits usingschematic captureMore on PLDs and Quartus IIdesign softwareAssign device and pinnumbers to schematic designsProgram Altera PLDs via aREADINGASSIGNMENTChapter 1 & 2HOMEWORK1.20, 1.21, 1.22,1.23, 1.24, 1.25,1.26Lab.#1DIP IntegratedCircuitsChapter 32.22, 2.24, 2.25,2.33, 2.35, 2.37,2.39Lab. #2ExpandingLogic GatesChapter 4Sections 4.14.64.4, 4.8, 4.12, 4.14,4.16,Lab. #3Pulse Operationof Logic GatesChapter 4Sections 4.74.104.16, 4.24, 4.25,4.27, 4.28
Electrical and Telecommunications Engineering Technology TCET3122 6 78 parallel port download cableCreate circuit symbols fromschematic designs and usethem in hierarchical designsfor PLDsIntroduction to VHDLUnderstand the functions of aVHDL entity declaration andarchitecture bodyWrite VHDL statementsdefining an entity andarchitectureEncode Boolean expressionsin VHDL using concurrentsignal assignment statementsEncode truth tables in vhdl,using selected signalassignment statementsUse Quartus II designsoftware to enter, andsimulate a VHDL designUse Quartus II designsoftware to assign pins to aCPLD and to program theCPLDExam IIntroduction to decoders,encoders, multiplexers, andmagnitude comparatorsDesign binary decoders inQuartus II using blockdiagram files or VHDLUse Quartus II block diagramfiles and/orDescribe the circuit operationof a multiplexer anddemultiplexer, and programthese functions in VHDLDefine the operation of aCMOS analog switch and itsuse in multiplexers anddemultiplexersDefine the operation of amagnitude comparator andprogram its function in VHDLLab. #4BooleanAlgebra: SOPFormsChapter 5Lab. #5BooleanAlgebra:DeMorganEquivalentFormsChapter 6Chapter 6Installing andLicensing Quatus IIDesign Software onYour PC5.4, 5.5, 5.17, 5.19,5.20Introduction toQuartus II DesignSoftware6.1, 6.4, 6.15, 6.22,6.33, 6.45, 6.46
Electrical and Telecommunications Engineering Technology TCET3122 9 10 Explain the use of parity as anerror-checking system anddraw simple parity-generationand checking circuitsIntroduction to sequentialcircuits and differencebetween combinational andsequential circuitsDefine the set and resetfunctions of an RS latchDraw circuits, function tablesand timing diagrams ofNAND and NOR latchesExplain the effect of eachpossible input combination toa NAND and NOR latch,including set, reset, and nochange functions, as well asthe ambiguous or forbiddeninput conditionsDesign circuit applicationsthat employ NAND and NORlatchesDescribe the use of ENABLEinput of a gated RS or D latchas an Enable/Inhibit functionand as a synchronizingfunctionExplain the concept of edgetriggering and why it is animprovement over levelsensitive enablingDraw circuits, function tables,and timing diagrams of edgetriggered D, JK, T flip-flopsDescribe the toggle functionof a JK flip-flop and a T flipflopDescribe the operation of theasynchronous preset and clearfunctions of D, JK, and T flipflops and be able to drawtiming diagrams showingtheir functionsUse Quartus II to createsimple circuits andLab. #6Introduction toVHDLChapter 8Sections 8.1 8.38.1, 8.7, 8.15,8.19,8.20Lab. #7StandardWiringConfigurationfor AlteraChapter 8Sections 8.48.88.26, 8.32, 8.34,8.36, 8.46
Electrical and Telecommunications Engineering Technology TCET3122 11 12 simulations with D latchesand D, JK, and T flip-flopsCreate simple latch and flipflop design using VHDLExplain the structure of anOutput Logic MarcoCell(OLMC)State the differences betweenthe Generic Logic Array(GAL) and standard PALIntroduction to DigitalCounters and Shift RegistersExplain the concept of asynchronous counterDetermine the modulus of acounterDraw the count sequencetable, state diagram, andtiming diagram of a counterDetermine the recycle point ofa counter sequenceCalculate the frequencies ofeach counter output, givingthe input clock frequencyDraw a circuit for a fullsequence synchronous counterUse Quartus II and VHDL todesign and simulatesynchronous countersIntroduction to Shift RegistersDraw logic circuit of a serialshift register and determine itscounts over time giving anyinput dataDraw a timing diagramshowing the operation of aserial shift registerDraw a logic circuit andtiming diagram of a generalparallel load shift registerDraw the general logic circuitand timing diagrams of bidirectional shift register andexplain the concepts of rightshift and left-shiftLab. #8BinaryDecodersChapters 9Sections 9.19.69.2, 9.14, 9.16, 9.27,9.36Lab. #9Binary andSeven-SegmentDecodersChapters 9Sections 9.99.99.48, 9.54, 9.55
Electrical and Telecommunications Engineering Technology TCET3122 13 14 15 Describe the operation of auniversal shift registerDesign shift registers, ringcounters, and Johnsoncounters with Quartus II blockeditor or VHDLExam IIIntroduction to StateMachinesDescribe the components of astate machine and distinguishbetween Moore and Mealyimplementations of statemachinesDraw the state diagram of astate machine from verbaldescriptionUse the state table method ofa state machine design todetermine the Booleanequations of the state machineTranslate the Booleanequations of a state machineinto a Block Diagram File inAltera’s Quartus II softwareWrite VHDL code toimplement state machinesCreate simulations in QuartusII to verify the function of astate machine designDesign state machineapplications, such as a switchdebouncer, a single pulsegenerator, and a traffic lightcontrollerReview and FinalExaminationLab. #10PriorityEncodersChapter 10Chapter 10Lab. #11Multiplexers
Electrical and Telecommunications Engineering Technology TCET3122New York City College of Technology on Academic IntegrityStudents and all others who work with information, ideas, texts, images, music,inventions, and other intellectual property owe their audience and sources accuracy andhonesty in using, creating, and citing sources. As a community of intellectual andprofessional workers, The College recognizes its responsibility for providing instructionin informal literacy and academic integrity, offering models of good practice, andresponding vigilantly and appropriately to infractions of academic integrity. Accordingly,academic dishonesty is prohibited in the City University of New York and at New YorkCollege City of Technology and is punishable by penalties, including failing grades,suspension, and expulsion. The complete text of the College policy on AcademicIntegrity may be found in the catalog.
2.1 Create a project in Quartus II. 2.2 Use Quartus Block Editor to enter a graphical design in Quartus II. 3. Use Altera's Quartus II software to design, simulate, and implement PLDs. 3.1 Compile and simulate the design. 3.2 Program an Altera CPLD with the Design. 3.3 Test the design on a CPLD test Board to determine the truth table. 4.
