WIXLIB

AD7745/AD7746ABSOLUTE MAXIMUM RATINGSTA 25 C, unless otherwise noted.Table 3.ParameterPositive Supply Voltage VDD to GNDVoltage on any Input or Output Pin toGNDESD Rating (ESD Association Human BodyModel, S5.1)Operating Temperature RangeStorage Temperature RangeJunction TemperatureTSSOP Package θJA,(Thermal Impedance-to-Air)TSSOP Package θJC,(Thermal Impedance-to-Case)Lead Temperature, SolderingVapor Phase (60 sec)Infrared (15 sec)Rating 0.3 V to 6.5 V–0.3 V to VDD 0.3 V2000 V–40 C to 125 C–65 C to 150 C150 C128 C/WStresses above those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. This is a stressrating only and functional operation of the device at these orany other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolutemaximum rating conditions for extended periods may affectdevice reliability.14 C/W215 C220 CESD CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on thehuman body and test equipment and can discharge without detection. Although this product featuresproprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energyelectrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performancedegradation or loss of functionality.Rev. 0 Page 6 of 28

AD7745/AD7746PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONSRDYSCL 116 SDA215 NCRDY16 SDA215 NC14 VDDEXCA 313 GNDTOP VIEWREFIN( ) 5 (Not to Scale) 12 VIN(–)EXCB 413 GNDTOP VIEWREFIN( ) 5 (Not to Scale) 12 VIN(–)REFIN(–) 611 VIN( )REFIN(–) 6EXCA 3EXCB 4AD774514 VDDAD774611 VIN( )10 NCCIN1(–) 710 CIN2(–)CIN1( ) 89NCCIN1( ) 89NC NO CONNECT05468-004CIN1(–) 7NC NO CONNECTFigure 4. AD7745 Pin Configuration (16-Lead TSSOP)CIN2( )05468-005SCL 1Figure 5. AD7746 Pin Configuration (16-Lead TSSOP)Table 4. Pin Function DescriptionsPin No.1MnemonicSCL2RDY3, 4EXCA, EXCB5, 6REFIN( ),REFIN(–)7CIN1(–)8CIN1( )9, 10(AD7745)9(AD7746)10(AD7746)11, 12NC1314GNDVDD1516NCSDACIN2( )CIN2(–)VIN( ), VIN(–)DescriptionSerial Interface Clock Input. Connects to the master clock line. Requires pull-up resistor if not alreadyprovided in the system.Logic Output. A falling edge on this output indicates that a conversion on enabled channel(s) has beenfinished and the new data is available. Alternatively, the status register can be read via the 2-wire serialinterface and the relevant bit(s) decoded to query the finished conversion. If not used, this pin should be leftas an open circuit.CDC Excitation Outputs. The measured capacitance is connected between one of the EXC pins and one of theCIN pins. If not used, these pins should be left as an open circuit.Differential Voltage Reference Input for the Voltage Channel (ADC). Alternatively, the on-chip internalreference can be used for the voltage channel. These reference input pins are not used for conversion oncapacitive channel(s) (CDC). If not used, these pins can be left as an open circuit or connected to GND.CDC Negative Capacitive Input in Differential Mode. This pin is internally disconnected in single-ended CDCconfiguration. If not used, this pin can be left as an open circuit or connected to GND.CDC Capacitive Input (in Single-Ended Mode) or Positive Capacitive Input (in Differential Mode). Themeasured capacitance is connected between one of the EXC pins and one of the CIN pins. If not used, this pincan be left as an open circuit or connected to GND.Not Connected. This pin should be left as an open circuit.CDC Second Capacitive Input (in Single-Ended Mode) or Positive Capacitive Input (in Differential Mode). If notused, this pin can be left open circuit or connected to GND.CDC Negative Capacitive Input in Differential Mode. This pin is internally disconnected in a single-ended CDCconfiguration. If not used, this pin can be left as an open circuit or connected to GND.Differential Voltage Input for the Voltage Channel (ADC). These pins are also used to connect an externaltemperature sensing diode. If not used, these pins can be left as an open circuit or connected to GND.Ground Pin.Power Supply Voltage. This pin should be decoupled to GND, using a low impedance capacitor, for examplein combination with a 10 µF tantalum and a 0.1 µF multilayer ceramic.Not Connected. This pin should be left as an open circuit.Serial Interface Bidirectional Data. Connects to the master data line. Requires a pull-up resistor if not providedelsewhere in the system.Rev. 0 Page 7 of 28

AD7745/AD7746TYPICAL PERFORMANCE CHARACTERISTICS181002.7V3V3.3V5V1614CAPACITANCE ERROR 23405468-017INL ANCE CIN PIN TO GND (pF)INPUT CAPACITANCE (pF)Figure 6. Capacitance Input Integral Nonlinearity,VDD 5 V, the Same Configuration as in Figure 31Figure 9. Capacitance Input Error vs. Capacitance between CIN and GND.CIN( ) to EXC 4 pF, CIN( ) to EXC 0 pF, VDD 2.7 V, 3 V, 3.3 V, and 5 V,the Same Configuration as in Figure 33200018GAIN TC –26ppm/ C161000CAPACITANCE ERROR 205468-015–3000–502.7V1205468-018GAIN ERROR (ppm)140150–20TEMPERATURE ( C)50100150200250300350400500450CAPACITANCE CIN PIN TO GND (pF)Figure 7. Capacitance Input Offset Drift vs. Temperature,VDD 5 V, CIN and EXC Pins Open CircuitFigure 10. Capacitance Input Error vs. Capacitance between CIN and GND,CIN( ) to EXC 21 pF, CIN( ) to EXC 23 pF, VDD 2.7 V, 3 V, 3.3 V, and 5 V,the Same Configuration as in Figure 341005752.7V4CAPACITANCE ERROR .3V21005468-016–753V05468-019OFFSET ERROR (aF)50–11500TEMPERATURE ( C)50100150200250300350400450500CAPACITANCE EXC PIN TO GND (pF)Figure 8. Capacitance Input Gain Drift vs. Temperature,VDD 5 V, CIN( ) to EXC 4 pF, the Same Configuration as in Figure 30Figure 11. Capacitance Input Error vs. Capacitance between EXC and GND,CIN( ) to EXC 21 pF, CIN( ) to EXC 23 pF, VDD 2.7 V, 3 V, 3.3 V, and 5 V,the Same Configuration as in Figure 34Rev. 0 Page 8 of 28

AD7745/AD7746086–2CAPACITANCE ERROR ��10–12–250 –200 –150 –100–5005010015020005468-031CAPACITANCE ERROR (fF)4–10250102CIN LEAKAGE TO GND (nA)34567SERIAL RESISTANCE (kΩ)Figure 12. Capacitance Input Error vs. Leakage Current to GND,CIN( ) to EXC 4 pF, CIN( ) to EXC 0 pF,VDD 2.7 V and 3 VFigure 15. Capacitance Input Error vs. Serial Resistance,CIN( ) to EXC 21 pF, CIN( ) to EXC 23 pF, VDD 5 V,the Same Configuration as in Figure 34.0.2860CAPACITANCE ERROR 468-0303.3V–10–12–250 –200 –150 TANCE ERROR (fF)43.03.54.04.55.05.5VDD (V)CIN LEAKAGE TO GND (nA)Figure 16. Capacitance Input Power Supply Rejection (PSR),CIN( ) to EXC 4 pF, the Same Configuration as in Figure 30Figure 13. Capacitance Input Error vs. Leakage Current to GND,CIN( ) to EXC 4 pF, CIN( ) to EXC 0 pF,VDD 3.3 V and 5 V100.20CAPDAC CODE DNL 0.050–0.05–0.10–0.1505468-033CAPACITANCE ERROR (pF)0.151–0.201000000PARALLEL RESISTANCE (MΩ)163248648096112CAPDAC CODEFigure 14. Capacitance Input Error vs. Resistance in Parallelwith Measured CapacitanceFigure 17. CAPDAC Differential Nonlinearity (DNL)Rev. 0 Page 9 of 28128

AD7745/AD77462.001.5–201.0GAIN (dB)ERROR ( 0050TEMPERATURE ( C)100150200250300350400INPUT SIGNAL FREQUENCY (Hz)Figure 21. Capacitance Channel Frequency Response,Conversion Time 62 msFigure 18. Internal Temperature Sensor Error vs. Temperature1.000.5–200GAIN (dB)ERROR ( –120150050TEMPERATURE ( N (dB)–2005468-036GAIN (dB)0200200Figure 22. Capacitance Channel Frequency Response,Conversion Time 109.6 ms0100150INPUT SIGNAL FREQUENCY (Hz)Figure 19. External Temperature Sensor Error vs. T SIGNAL FREQUENCY (Hz)INPUT SIGNAL FREQUENCY (Hz)Figure 20. Capacitance Channel Frequency Response,Conversion Time 11 msFigure 23. Voltage Channel Frequency Response,Conversion Time 122.1 msRev. 0 Page 10 of 28400

AD7745/AD7746OUTPUT NOISE AND RESOLUTION SPECIFICATIONSThe AD7745/AD7746 resolution is limited by noise. The noiseperformance varies with the selected conversion time.Table 5 shows typical noise performance and resolution for thecapacitive channel. These numbers were generated from 1000data samples acquired in continuous conversion mode, at anexcitation of 32 kHz, VDD/2, and with all CIN and EXC pinsconnected only to the evaluation board (no external capacitors.)Table 6 and Table 7 show typical noise performance andresolution for the voltage channel. These numbers weregenerated from 1000 data samples acquired in continuousconversion mode with VIN pins shorted to ground.RMS noise represents the standard deviation and p-p noiserepresents the difference between minimum and maximumresults in the data. Effective resolution is calculated from rmsnoise, and p-p resolution is calculated from p-p noise.Table 5. Typical Capacitive Input Noise and Resolution vs. Conversion TimeConversionTime (ms)11.011.920.038.062.077.092.0109.6Output DataRate (Hz)90.983.850.026.316.113.010.99.1–3dB Frequency(Hz)87.279.043.621.813.810.58.98.0RMS Noise(aF/ Hz)4.33.11.81.61.51.51.51.5RMSNoise (aF)40.027.312.27.35.44.94.44.2P-PNoise (aF)212.4137.782.550.333.728.327.827.3Effective P ble 6. Typical Voltage Input Noise and Resolution vs. Conversion Time, Internal Voltage ReferenceConversionTime (ms)20.132.162.1122.1Output DataRate (Hz)49.831.216.18.2–3dB Frequency(Hz)26.415.98.04.0RMS Noise(µV)11.47.14.03.0P-P Noise(µV)62422820Effective Resolution(Bits)17.618.319.119.5P-P Resolution(Bits)15.215.716.316.8Table 7. Typical Voltage Input Noise and Resolution vs. Conversion Time, External 2.5 V Voltage ReferenceConversionTime (ms)20.132.162.1122.1Output DataRate (Hz)49.831.216.18.2–3dB Frequency(Hz)26.415.98.04.0RMS Noise(µV)14.96.33.32.1P-P Noise(µV)95422215Rev. 0 Page 11 of 28Effective Resolution(Bits)18.319.620.521.1P-P Resolution(Bits)15.616.817.718.3

AD7745/AD7746SERIAL INTERFACEThe AD7745/AD7746 supports an I2C-compatible 2-wire serialinterface. The two wires on the I2C bus are called SCL (clock)and SDA (data). These two wires carry all addressing, control,and data information one bit at a time over the bus to allconnected peripheral devices. The SDA wire carries the data,while the SCL wire synchronizes the sender and receiver duringthe data transfer. I2C devices are classified as either master orslave devices. A device that initiates a data transfer message iscalled a master, while a device that responds to this message iscalled a slave.To control the AD7745/AD7746 device on the bus, thefollowing protocol must be followed. First, the master initiates adata transfer by establishing a start condition, defined by ahigh-to-low transition on SDA while SCL remains high. Thisindicates that the start byte follows. This 8-bit start byte is madeup of a 7-bit address plus an R/W bit indicator.All peripherals connected to the bus respond to the startcondition and shift in the next 8 bits (7-bit address R/W bit).The bits arrive MSB first. The peripheral that recognizes thetransmitted address responds by pulling the data line lowduring the ninth clock pulse. This is known as the acknowledgebit. All other devices withdraw from the bus at this point andmaintain an idle condition. An exception to this is the generalcall address, which is described later in this document. The idlecondition is where the device monitors the SDA and SCL lineswaiting for the start condition and the correct address byte. TheR/W bit determines the direction of the data transfer. A Logic 0LSB in the start byte means that the master writes informationto the addressed peripheral. In this case the AD7745/AD7746becomes a slave receiver. A Logic 1 LSB in the start byte meansthat the master reads information from the addressed peripheral. In this case, the AD7745/AD7746 becomes a slavetransmitter. In all instances, the AD7745/AD7746 acts as astandard slave device on the I2C bus.The start byte address for the AD7745/AD7746 is 0x90 for awrite and 0x91 for a read.READ OPERATIONWhen a read is selected in the start byte, the register that iscurrently addressed by the address pointer is transmitted on tothe SDA line by the AD7745/AD7746. This is then clocked outby the master device and the AD7745/AD7746 awaits anacknowledge from the master.If an acknowledge is received from the master, the address autoincrementer automatically increments the address pointerregister and outputs the next addressed register content on tothe SDA line for transmission to the master. If no acknowledgeis received, the AD7745/AD7746 return to the idle state and theaddress pointer is not incremented.The address pointers’ auto-incrementer allow block data to bewritten or read from the starting address and subsequentincremental addresses.In continuous conversion mode, the address pointers’ autoincrementer should be used for reading a conversion result.That means, the three data bytes should be read using onemultibyte read transaction rather than three separate single bytetransactions. The single byte data read transaction may result inthe data bytes from two different results being mixed. The sameapplies for six data bytes if both the capacitive and thevoltage/temperature channel are enabled.The user can also access any unique register (address) on a oneto-one basis without having to update all the registers. Theaddress pointer register contents cannot be read.If an incorrect address pointer location is accessed or, if the userallows the auto-incrementer to exceed the required registeraddress, the following applies: In read mode, the AD7745/AD7746 continues to outputvarious internal register contents until the master deviceissues a no acknowledge, start, or stop condition. Theaddress pointers’ auto-incrementer’s contents are reset topoint to the status register at Address 0x00 when a stopcondition is received at the end of a read operation. Thisallows the status register to be read (polled) continuallywithout having to constantly write to the address pointer. In write mode, the data for the invalid address is not loadedinto the AD7745/AD7746 registers but an acknowledge isissued by the AD7745/AD7746.WRITE OPERATIONWhen a write is selected, the byte following the start byte isalways the register address pointer (subaddress) byte, whichpoints to one of the internal registers on the AD7745/ AD7746.The address pointer byte is automatically loaded into theaddress pointer register and acknowledged by the AD7745/AD7746. After the address pointer byte acknowledge, a stopcondition, a repeated start condition, or another data byte canfollow from the master.A stop condition is defined by a low-to-high transition on SDAwhile SCL remains high. If a stop condition is ever encounteredby the AD7745/AD7746, it returns to its idle condition and theaddress pointer is reset to Address 0x00.If a data byte is transmitted after the register address pointerbyte, the AD7745/AD7746 load this byte into the register that iscurrently addressed by the address pointer register, send anacknowledge, and the address pointer auto-incrementer automatically increments the address pointer register to the nextinternal register address. Thus, subsequent transmitted databytes are loaded into sequentially incremented addresses.Rev. 0 Page 12 of 28

AD7745/AD7746If a repeated start condition is encountered after the addresspointer byte, all peripherals connected to the bus respondexactly as outlined above for a start condition, that is, a repeatedstart condition is treated the same as a start condition. When amaster device issues

AD7745/AD7746 Rev. 0 Page 3 of 28 SPECIFICATIONS V DD 2.7 V to 3.6 V or 4.75 V to 5.25 V; GND 0 V; EXC 32 kHz; EXC V DD/2; -40 C to 125 C, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments CAPACITIVE INPUT Conversion Input Range 4.096 pF1 Factory calibrated Integral Nonlinearity (INL)2 0.01 % of FSR