Guidelines For Using PEMS - NASA

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SSB-1: GUIDELINES FOR USING PLASTIC ENCAPSULATED MICROCIRCUITS ANDSEMICONDUCTORS IN MILITARY, AEROSPACE AND OTHER RUGGED APPLICATIONSHenry LivingstonVice-Chair, G-12 Solid State Device Committee of the Government Electronics & Information Technology AssociationSanders, a Lockheed Martin Co., P.O. Box 868, NCA01-2247, 95 Canal Street, Nashua, NH 03061-0868(603) 885-2360; fax: (603) 885-2783; e-mail: ELIABILITY MONITORINGINTRODUCTIONThe military and aerospace electronics industries are experiencingan ever increasing demand for the use of plastic encapsulatedmicrocircuits and semiconductors. While plastic encapsulatedmicrocircuits and semiconductors offer a number of inherentadvantages over hermetically sealed ceramic packages, uncontrolleduse can introduce a number of technical risks in military andaerospace equipment applications that are not associated withhermetic packaged devices.The G-12 Solid State Device Committee of the GovernmentElectronics & Information Technology Association (GEIA)developed guidelines for assessing the suitability of plasticencapsulated microcircuits and semiconductors for use in military,aerospace and other rugged applications. EIA Engineering BulletinSSB-1, Guidelines for Using Plastic Encapsulated Microcircuits andSemiconductors in Military, Aerospace and Other RuggedApplications provides: Methods for selecting the most suitable device for the applicationfrom both an equipment performance and economic perspective Means to emulate commercial buying practices by drawing uponqualification and reliability evaluation methods applied by themicroelectronics design and manufacturing industrySSB-1 presently includes four annexes that describe the reliabilityassessment method, including supporting technical rationale. SSB-1.001 Qualification and Reliability Monitors recommendsminimum qualification and monitoring testing of plasticencapsulated microcircuits and discrete semiconductors.SSB-1.002 Environmental Tests and Associated FailureMechanisms provides more detailed information concerning theenvironmental stresses associated with qualification andreliability monitor tests and the specific failures induced by theseenvironmental stresses. SSB-1.003 Acceleration Factors provides reference informationconcerning acceleration factors commonly used by devicemanufacturers to model failure rates in conjunction withstatistical reliability monitoring SSB-1.004 Failure Rate Estimating provides referenceinformation concerning methods commonly used by thesemiconductor industry to estimate failure rates from acceleratedtest results.Failure-Mechanism-Driven Reliability Monitoring draws uponthe concepts and implementation of line controls, process stabilityand effective monitoring programs in lieu of qualifying a productbased solely on a fixed list of tests. A supplier must identify thosefailure mechanisms that may be actuated through a given product /process change(s), and design and implement reliability testsadequate to assess the impact of those failure mechanisms on systemlevel reliability. In order for this to be effective, the supplierestablishes a thorough understanding and linkage to their reliabilitymonitoring program. Statistical Reliability Monitoring (SRM) is astatistically based methodology for monitoring and improvingreliability involving identification and classification of failuremechanisms, development and use of monitors, and investigation offailure kinetics allowing prediction of failure rate at use conditions.Failure kinetics are the characteristics of failure for a given physicalfailure mechanism, such as the acceleration factor, derating curve,activation energy, median life, standard deviation, characteristic life,instantaneous failure rate, etc.The failure rate of semiconductor devices is inherently low. As aresult, the semiconductor industry uses a technique calledacceleration testing to assess device reliability. Elevated stresses areused to produce the same failure mechanisms as would be observedunder normal use conditions, but in a shorter time period.Acceleration factors are used by device manufacturers to estimatefailure rates based on the results of accelerated testing. The objectiveof this testing is to identify these failure mechanisms and eliminatethem as a cause of failure during the useful life of the product.ACCELERATION TESTING ANDFAILURE MECHANISMSThe following describes tests frequently used in statisticalreliability monitoring (SRM) activities for plastic encapsulatedmicrocircuits and semiconductors and identifies the potential failuremechanisms monitored by these tests. This discussion does notinclude all of the tests typically included in device qualification andreliability monitoring, but focuses on those tests specificallydesigned to apply to (or have unique implications for) plasticencapsulated microcircuits and semiconductors. EIA JESD-47Stress-Test-Driven Qualification of Integrated Circuits includes acomplete set of reliability stress tests used by the semiconductorindustry for qualifying new or changed products.This paper presents the reliability assessment methodologydescribed in SSB-1.1 of 10

Preconditioning of Surface Mount Devices(EIA JESD-22-A113)The advent of surface mount devices (SMDs) introduced a newclass of quality and reliability concerns regarding package cracks anddelamination. Moisture from atmospheric humidity will enterpermeable packaging materials by diffusion and preferentially collectat the dissimilar material interfaces. Assembly processes, used tosolder SMDs to printed circuit boards (PCBs), will expose the entirepackage body to temperatures higher than 200 C. During solderreflow, the combination of rapid moisture expansion and materialsmismatch can result in package cracking and/or delamination ofcritical interfaces within the package. The solder reflow processes ofconcern are convection, convection/IR, infrared (IR), vapor phase(VPR), and hot air rework tools. The use of assembly processes thatimmerse the component body in molten solder are not recommendedfor most SMD components.IPC/JEDEC J-STD-033, Standard for Handling, Packing,Shipping and Use of Moisture/Reflow Sensitive Surface MountDevices, describes the standardized levels of floor life exposure formoisture/reflow-sensitive SMDs. This standard also includeshandling, packing and shipping requirements necessary to avoidmoisture/reflow-related failures. These methods are provided toavoid damage from moisture absorption and exposure to solderreflow temperatures that can result in yield and reliabilitydegradation. By using these procedures, safe and damage-free reflowcan be achieved, with the dry packing process, providing a minimumshelf life capability in sealed dry-bags of 12 months from the sealdate.JESD22-A113, Preconditioning of Nonhermetic Surface MountDevices Prior to Reliability Testing, is an industry standardpreconditioning flow for nonhermetic SMDs that is representative ofa typical industry multiple solder reflow operation. Thesemiconductor manufacturer should subject these SMDs to theappropriate preconditioning sequence of this test method prior tospecific in-house qualification and reliability monitoring to evaluatelong term reliability which might be effected by solder reflow.Bias Life Test (EIA JESD-22-A108)Failure mechanisms targeted by this test include die cracking,shorts and opens on die, passivation cracks/fracture, voids in dieattach, plastic package fracture/cracks, wirebond pad cratering,excessive intermetallics in wirebonds, poor solder joints.Autoclave (EIA JESD-22-A102)Autoclave is an environmental test that measures deviceresistance to moisture penetration and the resultant effects ofgalvanic corrosion. It is a highly accelerated and destructive test.Conditions employed during the test include 121 C, 100% relativehumidity, and 15 psig. Minimum test duration is typically 96 hours.Failure mechanisms targeted by this test include metallizationcorrosion, moisture ingress and delamination.Disadvantages of autoclave testing lie in the fact thatcontaminants in the chamber can induce failures that are notrepresentative of device reliability.Temperature Humidity Bias (EIA JESD-22-A101)The Temperature Humidity Bias Life (THB) test is used to testfor moisture induced failures. Compared to Highly AcceleratedStress Test (HAST) or autoclave, it requires less severe levels oftemperature and relative humidity. The test requires the devices toundergo a constant temperature, elevated relative humidity, andelectrical bias (constant or intermittent, based on device type). Oncemoisture reaches the die surface, the electric potential helpstransform the device into an electrolytic cell. This in turn acceleratesthe corrosion failure mechanism. Electrical tests are performed afterthe THB stressing to detect parametric drifts associated withcorrosion of susceptible parts. Failure mechanisms targeted by thistest include electrolytic/galvanic corrosion, delamination, and crackpropagation. Common failure sites include interfaces between leadfingers and the encapsulant, wirebonds, bondpads, and diemetallization.THB has become less useful for microcircuits in recent years dueto the increased packaging quality of die; reliability tests can runthousands of hours in order to get useful results.Highly Accelerated Stress Test (EIA JESD-22-A110)This test is performed to determine the effects of bias conditionsand temperature on solid state devices over an extended period oftime. A device is defined as a failure if the parametric limits areexceeded or if functionality cannot be demonstrated under nominaland worst-case conditions.Temperature Cycling (EIA JESD-22-A104)Temperature cycling tests the durability of a package undergoingextreme temperature variations over a given period of time.Temperature is usually varied about a mean value with a constantramp rate followed by a dwell period. This test exposes the packageto mechanical stress and accelerates failure modes associated withdiffering coefficients of thermal expansion between die andencapsulant materials. The dwell period is important because itallows the part to reach thermal equilibrium and for stress relaxationto occur. To conduct a temperature cycling test, a temperaturecontrolled environmental chamber and a heating unit and cryogeniccooling unit with the ability to meet the ramp rate specifications arerequired. At the end of the test, the package is tested electrically andexamined visually to identify areas of failure.The Highly Accelerated Stress Test (HAST) is performed toevaluate the non-hermetic packaging of solid state devices in humidenvironments. This test uses a high temperature (usually 130 C),high relative humidity (about 85%), under high atmospheric pressureconditions (up to 3 atm) to accelerate the penetration of moisturethrough the external protective material or at the seals around thechip leads. Once moisture reaches the die surface (as described forTHB), the electric potential helps transform the device into anelectrolytic cell. This in turn accelerates the corrosion failuremechanism. This test is intended to precipitate failure mechanismsassociated with metallization corrosion, delamination at materialinterfaces, wirebond failures, and reduced insulation resistance. Oneshould exercise caution when evaluating results of HAST testsperformed at temperatures higher than 130 C. Such tests canprecipitate different failure mechanisms that would not be seenduring normal device operation.HAST was developed especially for plastic encapsulated solidstate devices after it became evident that autoclave and THB testswere no longer generating failures among certain robust PEMs.HAST detects failure mechanisms similar to those detected by THB,but at a greatly accelerated rate. Some device manufacturerssubstitute HAST testing for THB based on comparisons between lots2 of 10

with known moisture sensitivity and verifying that failures were dueto the same failure mode. Acceleration factors are then applied toderive equivalent THB failure results from HAST test results.estimate of that failure mechanism’s effect on the microcircuit failurerate. If one has more knowledge of the specific process and materialused, EIA/JEP122 includes more detail to some of the specificmaterials and processes listed here.ACCELERATION FACTORSFirst Order Activation EnergiesThis following discussion addresses acceleration factorscommonly used by device manufacturers to model failure rates inconjunction with in statistical reliability monitoring (SRM). Theseacceleration factors are frequently used by OEMs in conjunction withphysics of failure reliability analysis to assess the suitability ofplastic encapsulated microcircuits and semiconductors for specificend use applications.General Failure Mechanism ClassSurface / OxideCharge Loss (dynamic memory)Dielectric BreakdownField 0.04 micron thickField 0.04 micron thickMetallizationElectromigration (Aluminum, alloys, andmulti-layer aluminum)Corrosion – ChlorineCorrosion – PhosphorusWafer FabricationChemical contaminationSilicon / crystal defectsThermal Effects (Arrhenius) Ea 1 1 exp k Tu Tt AfAf acceleration factorEa activation energy, typical value for a given failure mechanismor derived from empirical datak Boltzman’s Constant (8.6171 x 10-5 eV)Tt test environment junction temperature (in K)The Arrhenius Life-Temperature Relationship [1] is widely usedto model product life as a function of temperature. This relationshipis used to express both a single failure mechanism’s sensitivity totemperature and a product’s thermal acceleration factor. When usedto estimate the reliability of a product, the form above is used toexpress that product’s reliability with respect to temperature and as afunction of time. Device manufacturers use the Arrhenius equation toderive acceleration factors for High Temperature Operating Life,High Temperature Steady State Life and Data Retention (for nonvolatile memory devices) from this equation.Time-to-failure estimates using the Arrhenius equation are verysensitive to the activation energy value. For example, the effect of a0.05eV variation in activation energy on time-to-failure at 70 C is:f 0.30.70.60.700.531.000.50Non-Volatile Memory Data RetentionTu use environment junction temperature (in K)tTypical(eV)1.00.6exp (Ea 0.05 )/ kT 5exp Ea / kTEIA/JEP122, Failure Mechanisms and Models for SiliconSemiconductor Devices, describes the basic thermal accelerationequation in detail and provides guidance in selecting thermalactivation energies used to estimate system failure rates for the Sumof-the-Failure-Rates Method. EIA/JEP122 includes a single value foreach as a worst-case likely value for use as an industry suggestion toprovide consistency and comparisons.The following table, from EIA/JEP122, is a first order listing ofthermal activation energies assigned to general classifications offailure mechanisms applicable to microcircuits. If one has onlysuperficial knowledge of the physical processing employed and hasno other way of obtaining the characteristics of the failuremechanism, but knows that the failure falls under one of thecategories on this table, then the selection of the typical value forthermal activation energy will provide the basis for a reasonableOne should exercise caution where the Arrhenius LifeTemperature Relationship is used to derive acceleration factors fordata retention time-to-failure. Based on the work of DeSalvo et al[2], the Arrhenius relationship does not give the proper relationshipfor data retention life versus temperature. The Arrhenius relationshipgenerally defines the rate of diffusion as a function of temperature.Since many failure mechanism in semiconductor devices areattributed to the effect of mobile ions, the Arrhenius relationshipprovides a good model for calculating the acceleration of theseaffects due to increased temperature, and visa versa, relatingobserved failure rates at high temperatures to expected life times atlower temperatures.DeSalvo et al argue that the Arrhenius relationship does notproperly model data retention in floating-gate non-volatile memorydevices, because the data loss in due to charge loss, which obeys theFowler-Nordheim transport. Cogent analysis of historical datademonstrates how the newly proposed “T-Model” fits existing data.The Arrhenius model, however, is shown to require differentactivation energies to fit the data at different test temperatures.Choosing the wrong activation energy for a given temperature candrastically exaggerated results.The data retention time-to-failure using the “T-Model” iscalculated by the equation:t tR0T exp T 0 DR tR data retention time to failuretO data retention time in reference conditionsT temperatureTODR data-retention characteristic temperature3 of 10

We can derive the acceleration factor to extrapolate data retentiontime-to-failure as follows:Af Tu T0 t Ru t 0 e e T t Rt t T0 t 0 e A voltage acceleration factor [3] is often used in combinationwith the Arrhenius relationship for failure mechanisms which areknown to be accelerated by voltage (i.e. time dependent dielectricbreakdown, gate oxide defects, charge gain, etc.):fv exp[β (Vt Vu )]Subsequent to this study, Hallberg and Peck [5] found that datataken from several publications optimally fit this equation with n 3.0 and Ea 0.90eV. Recent studies indicate that some devices havehigher activation energies associated with temperature-humidityeffects. Tam [6], for example, found better correlation with Ea 0.95eV from his own test results for one specific device. The use ofEa 0.90eV is most common and, therefore, generally recommendedexcept where a device manufacturer may have empirical data tosubstantiate a higher activation energy for specific devices.Hallberg and Peck concluded that HAST testing should replaceTHB in order to improve feedback as well as shipment times, andthat moisture life extrapolation from THB can be accomplished fromthe following equation.fβ Voltage Acceleration Constant (empirically derived)An overall acceleration factor is derived from the product of theArrhenius Life-Temperature Relationship and voltage accelerationfactor: Ea exp kT 0.85A exp 10,444 1 1 [T 273] 358 RH Vu Use Voltageftvn3Vt Test VoltageAtwhere tt is time-to-failure, n -2.66, Ea 0.79eV, A is a constant(the temperature humidity failure rate in reference conditions)Tt Tu T0 Voltage Acceleration for MicrocircuitsAt A (% RH )A AftTemperature - Humidity Effects (Hallberg - Peck)3tfuaThis equation may also be applied when extrapolating autoclave(unbiased) test results.One should exercise caution when evaluating results of HASTtests performed at very high temperatures. Such tests can precipitatedifferent failure mechanisms that would not be seen during normaldevice operation. Sinnadurai [7] advocated an upper limit of 130 Cfor the validity of HAST testing of PEMs. In an extreme example,Sinnadurai argues that at 140 C and 100% RH the polymer of aplastic package would progressively de-bond and the exteriorterminations of the package would suffer electrolytic damage. TheJEDEC standard test method, JESD22-A110, includes test conditionsof 110 C at 85% RH and 130 C at 85% RH. Further, JESD22-A110cautions that moisture reduces the effective glass transitiontemperature of the molding compound and that stress temperaturesabove the effective glass transition temperature may lead to failuremechanisms unrelated to standard 85ºC/85% RH stress.fvRHA exp E k RH where T is in C, RH is in % and Ea 0.90eV 1 1 Tu Tt Af acceleration factorRHu use environment relative humidityRHt test environment relative humidityEa activation energy, 0.90eV-5k Boltzman’s Constant (8.6171 x 10 eV)Tu use environment junction temperature (in K)Tt test environment junction temperature (in K)This equation is often used to estimate acceleration factors fortemperature-humidity and bias effects when applied to HAST testresults, and for temperature-humidity effects when applied toautoclave (unbiased). This model is also used for HAST testingperformed without bias, a condition preferred by some users toapproximate dormant storage under a variety of long term storageconditions. Peck [4] described a relationship between temperature,humidity and life for electrolytic corrosion of aluminummetallization. Peck concluded that this relationship allows theestablishment of very-short-time tests to replace 1000-hourTemperature Humidity Bias (THB) testing and suggested using thisrelationship to extrapolate autoclave test results. This relationship hasthe following form.Brizoux, et al [8], of Thompson-CSF derived a model fortemperature and humidity effects. Though the use of this model isnot widely reported, it is presented here for completeness. Thismodel is based on Peck’s law and the Thompson-CSF functionalfailure model, which assumes temperature and power supply voltageconditions activate functional failures. In contrast to Hallberg’s andPeck’s work, Thompson-CSF found that temperature-humidityacceleration can be represented by Peck’s law, with n -2.66 and Ea 0.7eV. Using the reference conditions of 55 C junctiontemperature, 50% relative humidity and voltage at nominal 10%,the Thompson-CSF model is expressed in the following form.2.66Af 0.7 11 RHj exp 50 k Tj 328 Af acceleration factorTj junction temperature (in K)4 of 10 exp(V 1.1Vn )

this approach to thin film cracking, failures due to passivation filmcracks induced by thermal stress. Blish [13] observed from severalstudies that Coffin-Manson exponents for integrated circuit failuremechanisms tend to lie in one of three relatively narrow ranges:k Boltzman’s ConstantRHj relative humidity at the die surfaceV power supply voltageVn nominal power supply voltagewhere Tj Ta θjaP (Ta is ambient temperature, θja is junction toambient thermal resistance, P is dissipated power)Bias effects are incorporated in this model. When there is no bias,or when test voltage equals the nominal voltage for the device, thisportion of the equation goes away. This model also addressed thenotion that during operating conditions, the relative humidity at thedie surface (RHj) is lower than ambient relative humidity due tojunction temperature heating effects. When the difference betweenthe junction and ambient temperature increases, the die dries and therate of acceleration decreases. Thompson-CSF models this correctiveterm using the following psychrometric law. 0.43 1 1 RHj RHa exp k Tj Ta where RHa is ambient relative humidity, Tj is junction temperature(in ûK) and Ta is ambient temperature (in ûK)Failure MechanismmDuctile Metal Fatigue 1-3Commonly Used IC Metal Alloys & Intermetallics 3-5Brittle Fracture 6-8Blish reviewed a large number of papers in a critical fashion toextract a useful set of reliability modeling parameters in a singletable. SN diagrams (Stress vs. Number of cycles to fatigue failure)from Materials Science literature were used to advantage forprediction of integrated circuit failure rates caused by cyclic thermalstresses. A number of thermal fatigue data sets were examined toinfer how the Coffin-Manson exponent varies depending upon whichfailure mechanism is active. Some of the materials shown in thistable are not relevant to integrated circuit reliability, but arepresented here for historical and technical perspective. Similar failuremechanisms are grouped together.Thermo-mechanical Effects (Coffin-Manson)Af T t T u Coffin-Manson ExponentsmAf acceleration factor Tt thermal cycle temperature change in the test environment Tu thermal cycle temperature change in the use environmentm constant, typical value for a given failure mechanism or derivedfrom empirical dataThe Coffin-Manson Relationship [9] is an effective method tomodel the effects of low-cycle fatigue induced by thermal stressingupon microcircuit and semiconductor package reliability. Thisrelationship is based on the inverse power law [10] originally used tomodel fatigue of metals subjected to thermal cycling and has beenused for mechanical and electronic components, solder and otherconnections, and metals fatigue life. The typical number of cycles tofailure (N) as a function of the temperature range ( T) of the thermalcycle is expressed asN A ( T )Bwhere A is the number of cycles to failure in reference conditionsand B is characteristic of the specific metal and the test method.The acceleration factor for the Coffin-Manson Relationship is theratio of the temperature swing under accelerated conditions to thetemperature swing under service conditions, raised to the powergiven by a Coffin-Manson exponent (m 1/B) specific to eachfailure mechanism.mAuthor(s)MechanismHalfordMorrow316 Stainless Steel316 SS, WaspAlloy, 4340 Steel1.51.75Norris,LandzbergKotlowiczLi, HallSolder (97Pb/3Sn) Crossing 30 C1.9Solder (37Pb/63Sn) Crossing 30 CSolder (37Pb/63Sn) T 30 CT 30 CSolder (37Pb/3Ag & eddada,BlishMischkeHatankaBlishEgashiraCu & Leadframe Allows (TAB)Al wire bondsAu4Al fracture in wire bonds2.73.54.0PQFP Delamination / Bonds Failure4.2ASTM 2024 Aluminum AlloyCopperAu Wire Downbond Heel CrackASTM 6061 Aluminum ish, VaneyAlumina fracture-Bubble memoryInterLayer Dielectric CrackingSilicon fractureSi fracture (“cratering”)MavoriDunn and McPherson [11] used this equation to analyzeaccelerated conditions for fractured-intermetallic bond and chip-outbond failures (“cratering”) and derived Coffin-Manson exponents forthese failure mechanisms. Blish and Vaney [12] subsequently applied5 of 10Thin Film Cracking5.55.5 0.75.57.18.4

Examples of Major Market Segment Environmental RangesMajor Market SegmentOp LifePower On(Hrs / Week)Indoor: PC/ Desktop, Server,Workstation, Consumer5 – 10 yrsConsumer Portable: NotebookPCs, PDAs, Cel Phones, etc.Other: Automotive, Telecomswitching, Unattended outside,etc.Op Temp(Ambient InEnclosure)StorageTempCycles / DayMoisture @Low Power60 – 168Env. Cycle: 1-2Power Cycle: 2-430 -36 C @85-92% RH0 to 40 C-40 to 50 C5 – 10 yrs60 – 168Env. Cycle: 2-4Power Cycle: 4-630 -36 C @85-92% RH-18 to 55 C-40 to 55 C7 – 25 yrs20 – 168Env. Cycle: 2-4Power Cycle: 2-1030 -36 C @85-92% RH-55 to 125 C-40 to 55 CUSE CONDITION BASED RELIABILITY EVALUATIONFAILURE RATE ESTIMATING METHODOLOGYThe SEMATECH Reliability Technology Advisory Board(RTAB) developed a reliability evaluation methodology based on theuse conditions a component is expected to encounter in its marketapplications [14]. One of the most critical steps in the process isdefining environmental, lifetime and manufacturing use conditionssince it provides the basis for all follow on activities that lead toestablishing baseline performance. Determining the target marketsegment for a product establishes the use environment and lifetimeappropriate for the technology.The most frequently used reliability measure for semiconductordevices is the failure rate (λ). For constant failure rate, the failure rateis the ratio of the number of failures to the product of the number ofdevices on test and the interval in hours (i.e. λ number of failures /number of devices / number of test hours). The standard method forreporting long term failure rates for semiconductor devices is toexpress failure rate in Failures-In-Time (FITs), or the fraction of thenumber of failures per billion (109) device-hours.It is important to note that semiconductor manufacturers derivebaseline performance estimates for use conditions associated withtheir predominant market segment(s). The table, prepared by theSEMATECH RTAB, encompasses the majority of specificconditions within each major market segment. When assessing thesuitability of a device for a specific application, it is essential toaccount for differences between the use environment and theenvironment the manufacturer used for reliability evaluation.To project from a sample to the population in general, one mustestablish confidence intervals. The application of confidenceintervals is a statement of how “confident” one is that the samplefailure rate approximates that for the population. To obtain failurerates at different confidence levels, it is necessary to make use ofspecific probability distributions. The chi-square distribution (χ2),which relates observed and expected frequencies of an event, isfrequently used to establish confidence intervals. The relationshipbetween failure rate and the chi-square distribution is as follows:λ χ (α , d . f .) 10To illustrate this point, here is a specific example comparingreliability assessment results for a benign use environment versusresults for a more stressful environment such as those encountered inmany military, aerospace, and other rugged applications.Upon reviewing a device manufacturer’s product reliabilityreport, we note that this manufacturer extrapolates HAST uremechanisms assuming use conditions of 70 C junctiontemperature and 17.6% relative humidity. For one producttechnology, the manufacturer publishes a failure rate estimate of5 Failures-In-Time (FITs), or Mean-Time-To-Failure (MTTF) 22,500 years.If, however, we recalculate the failure estimate for a useenvironment of 85 C junction temperature and 90% relativehumidity (with all other elements of the failure rate calculationremaining equal), the result becomes 2431 (FITs), MTTF 47years.292 Af tλ failure rate (Failures-In-Time)χ2 chi-square functionα (100 - confidence level) / 100d.f. (2n 2) degrees of freedomn number of failuresAf acceleration factort (sample siz

during normal device operation. HAST was developed especially for plastic encapsulated solid state devices after it became evident that autoclave and THB tests were no longer generating failures among certain robust PEMs. HAST detects failure mechanisms similar to those detected by THB, but at a greatly accelerated rate. Some device manufacturers