Transcription
i.MX 8M Plus Applications ProcessorReference ManualDocument Number: IMX8MPRMRev. 0, 04/2021
i.MX 8M Plus Applications Processor Reference Manual, Rev. 0, 04/20212NXP Semiconductors
ContentsSection numberTitlePageChapter 1Introduction1.1Product Overview . 131.2Target Applications.131.3Acronyms and Abbreviations. 141.4Architectural Overview.16Chapter 2Memory Map2.1Memory system overview.272.2Cortex-A53 Memory Map . 282.3Cortex-M7 Memory Map.302.4DMA memory maps. 332.5AIPS Memory Maps. 342.6DAP Memory Map. 402.7Audio Processor Memory Map.422.8HDMI TX Subsystem Memory Map. 42Chapter 3System Security3.1Overview.453.2Central Security Unit (CSU).453.3Cryptographic Acceleration and Assurance Module (CAAM). 453.4Secure Non-Volatile Storage (SNVS). 463.5On-Chip OTP Controller (OCOTP CTRL).463.6Resource Domain Controller (RDC). 463.7TrustZone.47Chapter 4Resource Domain Controller (RDC)4.1Overview.49i.MX 8M Plus Applications Processor Reference Manual, Rev. 0, 04/2021NXP Semiconductors3
Section numberTitlePage4.2Functional Description .514.3External Signals. 584.4Programming Interface. 584.5RDC Memory Map/Register Definition. 644.6RDC SEMA42 Memory Map/Register Definition. 86Chapter 5Arm Cortex A53 Platform (A53) PlaceholderChapter 6Arm Cortex M7 Platform (CM7)6.1Overview.976.2Functional Description.99Chapter 7Messaging Unit (MU) PlaceholderChapter 8Semaphore (SEMA4)8.1Overview.1038.2Functional Description.1058.3External Signal Description. 1108.4Initialization Information. 1108.5Application Information.1108.6Memory map and register definition.112Chapter 9On-Chip RAM Memory Controller (OCRAM)9.1Overview.1239.2Functional Description.1249.3Programmable Registers. 125Chapter 10Network Interconnect Bus System (NIC) PlaceholderChapter 11AHB to IP Bridge (AIPSTZ)11.1Overview.129i.MX 8M Plus Applications Processor Reference Manual, Rev. 0, 04/20214NXP Semiconductors
Section numberTitlePage11.2Clocks. 13011.3Functional Description.13011.4Access Protections. 13111.5Access Support.13111.6Initialization Information. 13211.7Off-Platform Peripherals Index.13411.8AIPSTZ Memory Map/Register Definition. 135Chapter 12Shared Peripheral Bus Arbiter (SPBA) PlaceholderChapter 13TrustZone Address Space Controller (TZASC) PlaceholderChapter 14System Debug14.1Debug.157Chapter 15System JTAG Controller (SJC) PlaceholderChapter 16System Counter (SYS CTR) PlaceholderChapter 17Clock Control Module (CCM) PlaceholderChapter 18General Power Controller (GPC)18.1Overview.16918.2Features. 16918.3Block Diagram. 17018.4Functional Description.17118.5Power Gating Controller (PGC) Overview.17518.6Power control for A53 Platform. 18018.7Power control for the M7 Platform.18418.8Domain control for PGCs. 18418.9Example Code.185i.MX 8M Plus Applications Processor Reference Manual, Rev. 0, 04/2021NXP Semiconductors5
Section numberTitlePage18.10 GPC Memory Map/Register Definition.19118.11 GPC PGC Memory Map/Register Definition. 295Chapter 19Crystal Oscillator (XTALOSC) PlaceholderChapter 20Thermal Monitoring Unit (TMU) PlaceholderChapter 21System Boot21.1Overview.32521.2Boot modes. 32621.3Device configuration.32921.4Device initialization. 33121.5Boot devices (internal boot).33921.6Boot image. 38521.7USB boot.38821.8Low-power boot.38821.9SD/MMC manufacture mode.39021.10 High-Assurance Boot (HAB).39021.11 Boot information for software. 392Chapter 22Fusemap22.1Boot Fusemap. 39522.2Lock Fusemap.39922.3Fusemap Descriptions Table.399Chapter 23On-Chip OTP Controller (OCOTP CTRL) PlaceholderChapter 24Secure Non-Volatile Storage (SNVS)24.1Overview.41524.2SNVS functional description. 417i.MX 8M Plus Applications Processor Reference Manual, Re
1.3 Acronyms and Abbreviations The table below contains acronyms and abbreviations used in this document. Acronyms and Abbreviated Terms Term Meaning ADC Analog-to-Digital Converter AHB Advanced High-performance Bus AIPS Arm IP Bus ALU Arithmetic Logic Unit AMBA Advanced Microcontroller Bus Architecture APB Advanced Peripheral Bus
