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THE USE OF INTERRUPTSIN A TIME- SHARING COMPUTER SYSTEMbyJames White EgertonLieutenant Commander, United States NavyB.S., Naval Academy, 1956Submitted in partial fulfillment of therequirements for the degree ofMASTER OF SCIENCE IN COMMUNICATIONS ENGINEERINGfrom theNAVAL POSTGRADUATE SCHOOLJune 1967

ABSTRACTDigital computer interrupts are becoming more important as thesemachines increase in the interaction with their environment.methods of interrupt implementation are described.DifferentThey are thenanalyzed in the areas of response time, overhead, and saturation.Examples of the use of interrupts in different computational environments are given.Five modifications' to a general purpose computersystem are proposed.enable the system toThese modifications, each of which used interrupts,be.more easily used inThe results of these, modificationsare.alimited time-sharing mode.compared to those of the softwarethat would be required to accomplish the same objectives.

LIBRARYNAVAL POSTGRADUATE SCHOOLMONTEREY, CALIF. 93940TABLE OF CONTENTSSECTIONI.II.PAGEINTRODUCTION15ANALYSIS OF INTERRUPT SYSTEM REQUIREMENTS16Design characteristicsMethods of implementationOperating characteristicsIII.IV.161623Response time23Overhead25Saturation26USE OF INTERRUPTS IN COMPUTER SYSTEMS27Input/output interrupts27On-line real-time interrupts28Time-sharing interrupts30PROPOSED DIGITAL CONTROL LABORATORY TIME-SHARING SYSTEMSDS9 30computer features3232Time-multiplexed communication channel32Programmed operator34Multi-level priority interrupt system34SDS 930 computer operation37Central processing unit operation37Interrupt control system operation39Digital control laboratory system objectivesPurpose of modificationsProposed logic design changes454648Multiple operating modes48Privileged instructions49

SECTIONPAGEMemory protection53Quantum timer57Non-interrupt ible sequences60Software equivalentsV.62Multiple operating modes62Privileged instructions62Memory protection63Quantum timer63Non-interrupt ible sequences6364CONCLUSION65BIBLIOGRAPHYAPPENDIXISDS9 30OPERATION CODES66APPENDIXIISDS9 30LOGIC TERMINOLOGY70Logic circuitry70Logic levels70Logic gate circuitry70Flip-flop operation76Logic documentation76Logic equation7 8Logic diagram78Timing diagram7 9Module reference data81Example81APPENDIX III SUMMARY OF PROPOSED LOGIC MODIFICATIONS84

LIST OF TABLESTablePage1.Digital Control Laboratory Optional Equipment332.Privileged Instructions503.Memory Protect Switch Positions544.Special Logic Equation Terms78

LIST OF ILLUSTRATIONSFigurePage1.Instruction Format382.Interrupt Control System Logic, Level 34403.AND Gate714.Expander AND Gate715.Expanded AND Gate716.OR Gate7 37.AND/OR Gate7 38.Inverter7 39.Buffer Amplifier7510.Buffered AND7511.Negative AND7512.Line Inverters7713.Flip-flops7714.Typical Logic Diagram8015.Timing Diagram, EAX Instruction8016.Timing Diagram, BRU Instruction8217.Ju Flip-flop Logic Circuit82

ITABLE OF SYMBOLS AND ABBREVIATIONSSymboMeaningATwenty-four bit accumulator registerAO-A23Stages of the accumulatorA/DAnalog to digitalAddl-3Three stages of the full adderAiAllow interrupt flip-flopBTwenty-four bit accumulator extension registerBRXSignal which is true during an Increment Indexand Branch instructionCTwenty-four bit exchange registerCO-C23Stages of the exchange registercpscharacters per secondCPUCentral processing unitCr3Signal which shifts the exchange register rightthree bits at each timing pulseCT16Medium frequency crystal oscillator module inSDS T Series LogicD/ADigital to analogDCLDigital Control LaboratoryEAXSignal which is true during an Effective Addressinto X instructionEaxFlip-flop set during an Effective Address into Xinstruction and programmed operator executionEnSignal which enables the interrupt system En)Switch which enables the interrupt systemEndSignal which is true during the last phase of aninstruct ionEomSignal which is true during an Energize Output,Multiplex instruction

F1-F3Three-stage counter which determines the phaseof an instruction cycleGoFlip-flop whichIIndex bit (bitlaFlip-flop used for indirect addressing and foradvancing the program counterlbSignal which indicates completion of an interruptsubroutineICSInterrupt control systemIeSignal which indicates that the computer hasstarted processing an interrupt subroutineIjSignal which indicates that the present interruptis a single-instruction interruptInrInterrupt interlock flip-flopIntInterrupt flip-flopI/OInput/outputipsInches per secondIp5-Ip900Interrupt process flip-flopsIrInterrupt signal for an enable-required interruptIsInterrupt signal for an enable-not-requiredinterruptIs5-Is900Interrupt storage flip-flopsIxIndex flip-flopI5-- 1900Interrupt request signalsJuBranching flip-flopKOne thousandkHzKilo -Hertzset during computer operationis9)of an instruction(Kmc)Memory clear switch(Kr)Hold switchMOperand address of an instruction (bits 10-23)10

mHzMega-HertzMoMode flip-flopMpl-Mp3Three stages of the memory protect switchmsecMillisecondNXNext instructionNOPSignal which is true duringinstructionN5-N14Interrupt address linesaNo OperationSix bit operation code registermemory protectObSignal which indicates thatviolation has occurredOcSignal which sets the operation code register to 020OPCODEOperation codeOxcSignal which enables the transfer of C to01-06Stages of the operation code registerPProgram address register; programmed operator bit(bit2) of an instructionPiFlip-flop which is set upon execution user modeprivileged instructionPidSignal which is enabled by a privileged instructionopcode in the exchange registerPiqSignal which is true when a privileged instructionis executed in user modePmeSignal which is true when the storage addressregister contains a protected memory referencePOPProgrammed operatorPr3Signal which shifts the program address registerright three bits at each clock pulse.P0-P14Stages of the program address registerQtcOutput signal of the quantum timer oscillatorQtl-4Four flip-flops of the quantum timer control circuit11a

Q1-Q6Six-stage counter which determines the designationof a timing pulseRRelocation bit (bit 0) of an instructionRCHSignal which is true during a Register ChangeinstructionRfReady flip-flopRtcSignal used for real-time clock inputRtl-3Three flip-flops of the real-time clock controlc ircuitrXYZReset flip-flop XYZSStorage address registerSDSScientific Data Systems, Inc.SkSkip flip-flopSkiSignal which initiates the CLOCK SYNC interruptSkuSignal which initiates the end of time quantuminterrupt(St)Signal enabled by the START switchSxcSignal which enables the transfer ofSxnSignal which enables the transfer of an interruptaddress to SSxpSignal which enables the transfer of P toSx48Signal used in conjunction with shift instructionssXYZSet flip-flop XYZS1-S14Stages of the storage address registerTiSignal which is true from T3 through TOTMCCTime multiplexed communication channelTpLast timing pulse of a machine cycleTrNext to last timing pulse of a machine cycleTsSignal which is true duringoperation12aCtto SStime-shared memory

TsmFlip-flop used during interlaced I/O operationTsrFlip-flop used during interlaced I/O operationT8,T7,.,T0First nine timing pulses of a machine cycleuseeMicrosecondUsiUser mode single-instruction flip-flopXIndex register; indexing bit (bitinstructionXwlMost significant write flip-flop00-07Eight phase designations of an instruction cycle33Decimal number331)of anOctal number JIndicates signal originates at a switchXYZIndicates XYZ is false or zero13

SECTIONIINTRODUCTIONEarly digital computers were designed and used to solve individualproblems involving extensive calculations and produce the answers.Whenthe tremendous computational power of computers was applied to otheruses, however, the mere sequential execution of programmed steps in apredetermined order was no longer sufficient.In such areas as on-lineautomatic control, real-time simulation, and time-sharing systems, thecomputer is required to be responsive to the demands of its environment.This requirement is usually fulfilled by the use of interrupts.Basically, an interruptisacircuit designed to halt the normalexecution of a computer program on signal, and to execute in its placeagroup of instructions to fulfill the needs of the device which initiatedthe signal.This paper will analyze the various methods of interrupt implementa-tion and usage, and proposeasmall-scale time-sharing system which isimplemented on a general purpose digital computer through design changesutilizing priority interrupts.15

SECTION IIANALYSIS OF INTERRUPT SYSTEM REQUIREMENTSInterrupts can be divided into three categories according to purpose.The first of these, the request interrupt, is one which requires thecomputer to take some immediate action to satisfy the cause of the interrupt.Secondly, the indicator interrupt notifies the computer of someexternal condition which does not require action, but the computer maysample this condition to determineisacourse of action.The third typethe fault interrupt, which is caused by some internal abnormal condi-tion such as a parity error.I.DESIGN CHARACTERISTICSThere are many methods for implementing interrupts incomputer.adigitalThe following paragraphs will describe the most prevalentmethods and classify them logically according to their characteristics.Methods of ImplementationThe basic requirement for an interrupt is to stop execution of thecurrent instruction sequence, make some record of the stopping point,and execute instead some other special set of instructions, called theinterrupt subroutine.The first method to implement this is the singleinterrupt system.Single interrupt.The single interrupt system basically consistsof one flip-flop in the computer's control circuitry which is wired tosome external device.This flip-flop is set whenever the conditionThe CPU will normally check the statecausing the interrupt is present.of this flip-flop after each instruction execution.Ifitisset, theCPU will store the contents of the program address counter and execute thenext instruction (the first instruction in the interrupt subroutine) from16

.some fixed location associated with this interrupt.Some provision wouldthen be made to clear the flip-flop and return to the point of interruption upon completion of the subroutine.The use ofasystem that doesnot mark the point of interruption is not feasible for the following rea-sons.Request and indicator interrupts normally require returning to theprogram in progress when the interrupt was received.Fault interruptsusually would not return, but the address of the instruction being executed when the fault occurred is important in determining the cause of thefaultThe single interrupt scheme described above has another limitationinaddition to being able to sense only one external condition.while the interrupt is being processed,received,isitasecond interrupt signal iswill be lost, since it will attempt to setalready set.IfIf,aflip-flop whichthe flip-flop is cleared at the start of the interruptsubroutine rather than at the end to correct this, then another interruptsignal would start the subroutine over again, destroying the originalThis would result in an infinite program loop.interruption point.Single interrupt with interlockeliminated by usinga.The deficiency noted above can besingle interrupt with interlock,adevice similarto the single interrupt except that it has a second, or interlock, flip-flop.An interrupt signal sets the first, or interrupt, flip-flop.Atthe end of the next instruction, the CPU initiates the interrupt only ifthe.interlock flip-flop is cleared.Immediately after starting theinterrupt subroutine, the CPU sets the interlock flip-flop and clearsthe interrupt flip-flop.Another interrupt signal may then be receivedand stored until completion of the present interrupt subroutine, when theinterlock flip-flopiscleared.17