WIXLIB

RISC- colins@eecs.berkeley.edu

Outline§ WhatcanRocketChipdo?§ HowdoIchangewhatRocketChipgenerates?- Whatarechiselparametersandhowdotheyhelpme?§ HowdoIusetheC emulator?§ HowdoIgetawaveform/debug?§ HowdoIadddifferentopDons?- WheredoIputmychanges?§ HowdoIaddnewinstrucDons?- HowdoI“drop- ‐in”myaccelerator?- WheredoIputdifferentextensions?§ HowdoIuseveriloggeneraDon?- ForanASICtoolflow- ForanFPGAtarget2

WhatcanRocketChipdo?§ WhatcanRocketChipdo?§ nonthissoPware§ etersmostofwhichcanbefreelychanged§ Wecanthenselectwhattogenerate§ C RTLemulator§ Verilog- FPGA- ASIC3

WhatareallthesesubmodulesinRocketChip?§ Chisel- TheHDLweuseatBerkeleytodevelopourRTL.§ Rocket- SourcecodefortheRocketcoreandcaches§ Uncore- stinterface§ Hardfloat- ParameterizedFMAsandconverters,seeREADME§ Dramsim2- SimulatesDRAMDmingforsimulaDons§ Fpga- ‐zync- Codethathelpsgetrocket- ‐chiponFPGAs§ Riscv- ‐tools- SoPwaretoolchainusedwiththisversionofRocketChip4

Whatabouttheotherfolders?Locatedin /bar/rocket-chip/§ src- Chiselsourcecodeforrocketchip§ csrc- GluecodetobeusedwiththeC emulator§ vsrc- Verilogtestharnessforrocket- ‐chip§ emulator- BuilddirectoryfortheC emulator,containsgeneratedcodeandexecutables§ fsim- BuilddirectoryforFPGAveriloggeneraDon§ vsim- BuilddirectoryforASICveriloggeneraDon§ project- Scala/sbtconfiguraDonfiles§ rocc-template (exampleroccusedforthistutorial)5

OverviewofRocketChipParameters§ Locatedinsrc/main/scala/PublicConfigs.scala§ EasilychangedparametersarecalledKnobscase VAddrBits 43caseNMSHRs Knob("L1D MSHRS")§ ImportantconfiguraDonopDonsfitinafewcategories- Tile–Howmany,whattypes,whataccel?- Memory–Phys/VirtAddressbits,Meminterfaceparams- Caches–Sets,ways,widthetc.forL1andL2;TLBs- Core–FPU?,fmalatency,etc.- Uncore–coherenceprotocol,Dlelinkparams6

Configs§ Dons§ nableviaDesignspaceexploraDon§ TwoexamplesgivenatbobomofPublicConfigs.scala- pecified- SmallConfig–removesFPUandhassmallercaches§ youwant7

SimulaEngaConfiguraEon§ C RTLemulatorbuiltfromemulatordirectory§ Thedefaultemulatorhasalreadybeenbuilt make run-asm-tests§ Wecanalsobuildthesmallconfigveryeasily make CONFIG ExampleSmallConfig§ Andtestittoo! make CONFIG ExampleSmallConfig runasm-tests§ artenoughtofindtheconfigclass8

MakingandSimulaEnganewConfiguraEon§ Letstrymakinga“medium”sizedconfig- lassclass MediumConfigMediumConfig extendsextends SmallConfig{SmallConfig{overrideoverride valval knobValues:Any AnyknobValues:Any Any {{case "L1D WAYS" 2case "L1I WAYS" 2}}class ExampleMediumConfig extends ChiselConfig(newMediumConfig new DefaultConfig)§ Allweneedtodoisspecifyitwhenmakingtheemulator make CONFIG ExampleMediumConfig§ Wecanthentestthenewconfig make CONFIG ExampleMediumConfig runasm-tests§ Thepowerofgenerators!9

MoreComplicatedConfiguraEons§ HowwouldIaddanewparametertorocketchip?- DefaultConfig- mentaDon§ HowdoIaddaccelerators?Whatabouttheirparameters?- ersdeclaredintheirownsourcefolder- aintherocket- ‐chipsource- Moreonthislater10

Rocket Custom CoprocessorISAExtensionsandRoCCExtensionsChapter 8§ Chapter9intheISAmanual§ 4majoropcodessetasidefornon- ‐standardextensions(TableRocket is a particular microarchitectural implementation of RISC-V, which supports addition ofRV32/64GInstruction Set Listings8.1)custom accelerators over a standardized coprocessor interface. This chapter describes the instruc-- Custom0- ‐3usedby Rocket Custom Coprocessors (RoCCs). Each accelerator willtion encodingtemplatedefine its-owninstructionsubsetname,but thesebegin with “X” to signify they n-standard ISA extensions.§ RoCCinterfaceusesthisopcodespaceOne goal of the RISC-V project is that it be used as a stable software development target. For tructionseldextensionformatis only ofonepossibleway(RV32Iof addingto thestandardbase in- extensionspurpose, Thiswe-definea combinationISAorfcustomRV64I)plus selectedand was designedto simplifymicroarchitecturaldependenciesbetweena core ��ISA,and entingthe base ISAThisand acoprocessorimplementingCustom exf instructionset terrs1/2,orwritestheset listings fortensions can be more tightly coupled to the core, for example, by building on the packed-SIMDRV32G and RV64G.extensions,which intoturnresponserdbuild on the floating-point extensions.Of course, Chisel is the best way to sculpt a RoCC.inst[4:2]000001010011100101110111inst[6:5]( 32b)The edforcustomextensions(custom-0,00LOADLOAD-FP custom-0 MISC-MEM OP-IMM -FP eserved custom-2/rv12848b11 BRANCHJALRreservedJALSYSTEM reserved custom-3/rv12880b3125 2420 1915 1413Table 8.1: RISC-V base opcodefunct7rs2rs1xd xs175511Table 8.1 shows a map of the major opcodes for RVG.roccinst[6:0]src2src112117 60map, inst[1:0] 11xs2rdopcode157Major opcodes with 3 or more lower bitsdestcustom-0/1/2/311

RoCCAccelerators§ ytocreateaRISC- ‐Vextension§ Toolchainalreadysupportscustom0- ‐3assembly- terface§ NeedtoimplementtheRoCCIOinterface§ Locatedinrocket/src/main/scala/rocc.scala12

RoCCInterface§ d(Resp)ROCCAccel.CacheIO§ busy§ IRQsupervisor bit§ § UncachedTileLinkIO§ PTWIOexception§ ndsmemoryrequeststoL1D nacceleratorPTWIOforpage- ‐tablewalkerportsonaccelerator13

RoCCAcceleratorExample§ dinteachingCS250atBerkeley§ Thisbranchofrocc- gorithm§ Itincludesseveralthings- Creferencecodeinrocc-template/src/main/c- ChiselimplementaDoninrocc-template/src/main/scala- CtestcasesforbothSWandRoCCinrocc-template/tests- FuncDonalmodelforSpikeinrocc-template/isasim- NewRocketchipconfiguraDoninrocc-template/config14

FuncEonalModelofAccelerator§ Firststeptoanyarchitectureprojectwriteasimulator§ /sha3/sha3.h§ Weextendtherocc tclassimplemenDngasubsetofthecustomopcodes§ DescribesafuncDonalmodelofthecomputaDon§ Adherestothesameinterfaceastheaccelerator§ rocessorsmmup- get mmu()- Seelines56,63§ Nowwearereadytotestthemodel15

FuncEonalModelofAccelerator§ Ratherthanmovingthefilesoutoftherocc- ) spike --extension sha3§ Needtorebuildspiketobeabletomodelouraccelerator cd riscv-tools && ./build-spikeonly.sh§ Nowspikeunderstandsourextension! spike --extension sha316

AcceleratorTests§ cc[-bm].c§ swversionsjustusesthereferenceCimplementaDon§ see:rocc-template/tests/sha3-rocc.c§ Theoperandsarexd/rd,xs1/rs1,xs2/rs2,andfunct§ Pucng0fortheregisteroperandsmarksthemunused§ estotheaccelerator17

FuncEonalModelofAcceleratorTesEng§ Nowwearereadytotestourmodel§ FirstjustthesoPwareonlyversion spike pk sha3-sw.rv§ Letstrytheacceleratorversionwithouttheaccel spike pk sha3-rocc.rv§ Anexpectedfailuresonowweenableourextension spike --extension sha3 sha3-rocc.rv§ Success!18

ChiselAccelerator§ tchip§ .e.haveasrc/main/scaladirectory)§ n/scala/sha3.scala§ s§ uwanttoundertake19

ChiselAcceleratorPlug- ‐in§ g/PrivateConfigs.scala§ ivestheconstructorfortheSha3accelerator§ torinitsdatapath§ Thecleaninterfaceallowsthistohappenseamlessly§ Nowwecanbuildtheacceleratedversion make CONFIG Sha3CPPConfig20

ChiselAcceleratorPerformance§ Timetotestthisnewemulator§ Wecanevenmeasureperformance(pk“s”flag) ./emulator-DefaultCPPConfig pk s ./rocc-template/tests/sha3-swbm.rv ./emulator-Sha3CPPConfig pk -s ./rocc-template/tests/sha3-sw-bm.rv ./emulator-Sha3CPPConfig pk -s ./rocc-template/tests/sha3-rocc-bm.rv§ up21

ChiselRTLDebugging§ WhatifIhadabug?§ twanttojustseeawaveform§ C emulatorsupportsthistoo make debug ./emulator-DefaultCPPConfig-debug vtest.vcd loadmem output/median.riscv.hex§ pen gtkwave test.vcd§ becauseofthepkandtestlength22

Non- ‐RoCCextensions§ RoCC)§ hterintegraDon§ UpdatesneedtobemadeinseverallocaDons- riscv- ‐opcodes(defineyournewencodings)- riscv- ‐gnu- ‐toolchain(addnewinstrucDonstoassembler)- riscv- ‐isa- ‐sim(update/addinstrucDondefiniDon)- rocket(datapathandfront- ‐endupdates)23

Non- ‐RoCCextensionriscv- ‐opcodes§ Repositoryforallencodings§ Generates- Headerfilesgnu- ‐toolchain- Headerfilesforisa- ‐sim- ISAmanualtables- Chiselcodetoincludeinrocket§ AddtheinstrucDontooneoftheopcodesfiles make install§ ecorrectfolders24

Non- ‐RoCCextensionriscv- ‐gnu- ‐toolchain§ ContainsbinuDls,gcc,newlibandgccports§ c.c§ Thisisallthat’sneededforsimpleinstrucDons§ Don25

Non- ‐RoCCextensionriscv- ‐isa- ‐sim§ AlreadylookedatthisearlierforRoCCextensions§ StandardriscvinstrucDonsaredefinedinriscv/insns§ AddingtheinstrucDontoriscv- sfolderwiththeinstrucDonsname§ TheheaderfiledescribeshowtheinstrucDonbehaves§ ManyexamplesofdifferentinstrucDonstostartwith26

Non- ‐RoCCextensionrocket§ ucDon§ SimplyaddinganewALUopwouldrequireveryfewchanges§ trucDon§ s- moreonthislater27

RocketChipVerilog§ logwithanASICbackendinmind cd ./vsim && make§ Thegenerated- ‐srcdirectorycontains- Verilogsource(Top. CONFIG.v)- Setofexportedparameters(Top. CONFIG.prm)- Memoryparameters(Top. CONFIG.conf)§ SRAMstogenerateorrequest§ vlsi mem genscriptisusedbyBerkeleytoautomatethisprocess§ APerthisprocessingtheverilogisreadyforCADtools28

RocketChipVerilogforFPGA§ logwithanFPGAbackendinmind cd ./fsim && make§ Thegenerated- ‐srcdirectorycontains- Verilogsource(Top. CONFIG.v)- Setofexportedparameters(Top. CONFIG.prm)- Memoryparameters(Top. CONFIG.conf)§ fpga mem genhandlesthememoryconfiguraDons§ fpga- thefpgatoolstorun§ Dons- hbps://github.com/riscv/fpga- ‐zynq29

RocketChipQuesEons,SuggesEons,andFeedback§ TechnicalSupportForRISC- ‐VSoPware/GeneralQuesDons- hbp://stackoverflow.com/quesDons/tagged/riscv§ DiscussionMailingListshbps://lists.riscv.org/- sw- ‐dev- hw- ‐dev§ Specificbugscanbereportedtogithub- shighlyencouraged§ QuesDonsinpersonforabitaPerthis30

QuesEons31

Rocket Custom Coprocessor Extensions Rocket is a particular microarchitectural implementation of RISC-V, which supports addition of custom accelerators over a standardized coprocessor interface. This chapter describes the instruc-tion encoding template used by Rocket