Transcription
Copyright 2016–2021 Xilinx
Zynq UltraScale MPSoCsCGDevicesDevicesDevicesApplication ProcessorEVEGDual-core Arm Cortex -A53MPCore up to 1.3GHzQuad-core Arm Cortex-A53MPCore up to 1.5GHzQuad-core Arm Cortex-A53MPCore up to 1.5GHzDual-core Arm Cortex-R5FMPCore up to 533MHzDual-core ARM Cortex-R5MPCore up to 600MHzDual-core ARM Cortex-R5MPCore up to 600MHzMali -400 MP2Mali -400 MP2Real-Time ProcessorGraphics ProcessorVideo CodecProgrammable LogicApplicationsH.264 / H.26581K–600K System Logic Cells81K–1143K System Logic Cells192K–504K System Logic Cells Sensor Processing & FusionMotor ControlLow-cost UltrasoundTraffic EngineeringFlight NavigationMissile & MunitionsMilitary ConstructionSecure SolutionsNetworkingCloud Computing SecurityData CenterMachine VisionMedical EndoscopySituational AwarenessSurveillance/ReconnaissanceSmart VisionImage ManipulationGraphic OverlayHuman Machine InterfaceAutomotive ADASVideo ProcessingInteractive DisplayXMP104 (v2.5.1)Page 2 Copyright 2016–2021 Xilinx
Processing System (PS)Zynq UltraScale MPSoCs: CG DevicesApplicationProcessor UnitReal-TimeProcessor UnitExternal MemoryConnectivityIntegrated BlockFunctionalityDevice Name(1)Processor CoreMemory w/ECCProcessor CoreMemory w/ECCDynamic Memory InterfaceStatic Memory InterfacesHigh-Speed ConnectivityGeneral ConnectivityPower ManagementSecurityAMS - System 401-PS to PL InterfaceProgrammable Logic ted IPTransceiversSpeed GradesSystem Logic Cells (K)CLB Flip-Flops (K)CLB LUTs (K)Max. Distributed RAM (Mb)Total Block RAM (Mb)UltraRAM (Mb)Clock Management Tiles (CMTs)DSP SlicesPCI Express Gen 3x16150G Interlaken100G Ethernet MAC/PCS w/RS-FECAMS - System MonitorGTH 16.3Gb/s TransceiversGTY 32.75Gb/s 6CGDual-core Arm Cortex -A53 MPCore up to 1.3GHzL1 Cache 32KB I / D per core, L2 Cache 1MB, on-chip Memory 256KBDual-core Arm Cortex-R5F MPCore up to 533MHzL1 Cache 32KB I / D per core, Tightly Coupled Memory 128KB per corex16: DDR4 w/o ECC; x32/x64: DDR4, LPDDR4, DDR3, DDR3L, LPDDR3 w/ ECCNAND, 2x Quad-SPIPCIe Gen2 x4, 2x USB3.0, SATA 3.1, DisplayPort, 4x Tri-mode Gigabit Ethernet2xUSB 2.0, 2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIOFull / Low / PL / Battery Power DomainsRSA, AES, and SHA10-bit, 1MSPS – Temperature and Voltage Monitor12 x 32/64/128b AXI 1624-1 -2 -2L-1 -1L 748.832.142,520124-Notes:1. For full part number details, see the Ordering Information section in DS891, Zynq UltraScale MPSoC Overview.2.-2LE (Tj 0 C to 110 C). For more details, see the Ordering Information section in DS891, Zynq UltraScale MPSoC Overview.XMP104 (v2.5.1)Page 3 Copyright 2016–2021 Xilinx
Processing System (PS)Zynq UltraScale MPSoCs: EG DevicesApplication ProcessorUnitReal-Time ProcessorUnitGraphic & VideoAccelerationExternal MemoryConnectivityIntegrated BlockFunctionalityDevice Name(1)Processor CoreMemory w/ECCProcessor CoreMemory w/ECCGraphics Processing UnitMemoryDynamic Memory InterfaceStatic Memory InterfacesHigh-Speed ConnectivityGeneral ConnectivityPower ManagementSecurityAMS - System 4471.25.332401-1 -2 ,96854414428PS to PL InterfaceProgrammable Logic ted IPTransceiversSpeed GradesSystem Logic Cells (K)CLB Flip-Flops (K)CLB LUTs (K)Max. Distributed RAM (Mb)Total Block RAM (Mb)UltraRAM (Mb)Clock Management Tiles (CMTs)DSP SlicesPCI Express Gen 3x16150G Interlaken100G Ethernet MAC/PCS w/RS-FECAMS - System MonitorGTH 16.3Gb/s TransceiversGTY 32.75Gb/s 7EGZU9EGZU11EGZU15EGZU17EGQuad-core Arm Cortex -A53 MPCore up to 1.5GHzL1 Cache 32KB I / D per core, L2 Cache 1MB, on-chip Memory 256KBDual-core Arm Cortex-R5F MPCore up to 600MHzL1 Cache 32KB I / D per core, Tightly Coupled Memory 128KB per coreMali -400 MP2 up to 667MHzL2 Cache 64KBx16: DDR4 w/o ECC; x32/x64: DDR4, LPDDR4, DDR3, DDR3L, LPDDR3 w/ ECCNAND, 2x Quad-SPIPCIe Gen2 x4, 2x USB3.0, SATA 3.1, DisplayPort, 4x Tri-mode Gigabit Ethernet2xUSB 2.0, 2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIOFull / Low / PL / Battery Power DomainsRSA, AES, and SHA10-bit, 1MSPS – Temperature and Voltage Monitor12 x 32/64/128b AXI 902224412221111111116162424243224441628-1 -2 -2L -3-1 -2 -2L -3-1 -1L -2Notes:1. For full part number details, see the Ordering Information section in DS891, Zynq UltraScale MPSoC Overview.2.-2LE (Tj 0 C to 110 C). For more details, see the Ordering Information section in DS891, Zynq UltraScale MPSoC Overview.Page 4XMP104 (v2.5.1) Copyright 2016–2021 Xilinx
Zynq UltraScale MPSoCs: EV DevicesProcessing System (PS)Application Processor UnitReal-Time Processor UnitGraphic & VideoAccelerationExternal MemoryConnectivityIntegrated BlockFunctionalityDevice Name(1)Processor CoreMemory w/ECCProcessor CoreMemory w/ECCGraphics Processing UnitMemoryDynamic Memory InterfaceStatic Memory InterfacesHigh-Speed ConnectivityGeneral ConnectivityPower ManagementSecurityAMS - System MonitorZU4EVPS to PL InterfaceProgrammable Logic ted IPTransceiversSpeed GradesSystem Logic Cells (K)CLB Flip-Flops (K)CLB LUTs (K)Max. Distributed RAM (Mb)Total Block RAM (Mb)UltraRAM (Mb)Clock Management Tiles (CMTs)DSP SlicesVideo Codec Unit (VCU)PCI Express Gen 3x16150G Interlaken100G Ethernet MAC/PCS w/RS-FECAMS - System MonitorGTH 16.3Gb/s TransceiversGTY 32.75Gb/s 5472812116-ZU5EVZU7EVQuad-core Arm Cortex -A53 MPCore up to 1.5GHzL1 Cache 32KB I / D per core, L2 Cache 1MB, on-chip Memory 256KBDual-core Arm Cortex-R5F MPCore up to 600MHzL1 Cache 32KB I / D per core, Tightly Coupled Memory 128KB per coreMali -400 MP2 up to 667MHzL2 Cache 64KBx16: DDR4 w/o ECC; x32/x64: DDR4, LPDDR4, DDR3, DDR3L, LPDDR3 w/ ECCNAND, 2x Quad-SPIPCIe Gen2 x4, 2x USB3.0, SATA 3.1, DisplayPort, 4x Tri-mode Gigabit Ethernet2xUSB 2.0, 2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIOFull / Low / PL / Battery Power DomainsRSA, AES, and SHA10-bit, 1MSPS – Temperature and Voltage Monitor12 x 32/64/128b AXI 81,7281122111624-1 -2 -2L -3-1 -1L -2Notes:1. For full part number details, see the Ordering Information section in DS891, Zynq UltraScale MPSoC Overview.2.-2LE (Tj 0 C to 110 C). For more details, see the Ordering Information section in DS891, Zynq UltraScale MPSoC Overview.Page 5XMP104 (v2.5.1) Copyright 2016–2021 Xilinx
Zynq UltraScale MPSoCsPS I/Os(1), 3.3V High-Density (HD) I/O, 1.8V High-Performance (HP) I/OsPS-GTR 6Gb/s, GTH 16.3Gb/s, GTY 32.75Gb/sPkgFootprint(2,3)Dimensions Ball Pitch(mm)(mm)ZU1ZU2ZU3170, 24, 584, 0, 0170, 24, 584, 0, 0170, 24, 584, 0, 0170, 24, 584, 0, 0ZU4ZU5214, 96, 1564, 4, 0214, 96, 1564, 4, 0214, 48, 1564, 16, 0214, 48, 1564, 16, 0ZU6ZU7ZU9ZU11ZU15A484(4)19x190.8170, 24, 584, 0, 0A4949.5x150.5170, 24, 584, 0, 0A5309.5x160.5A625(4)21x210.8170, 24, 1564, 0, 0170, 24, 1564, 0, 0170, 24, 1564, 0, 0C784(4,5)23x230.8214, 24, 156,4, 0, 0214, 96, 1564, 0, 0214, 96, 1564, 0, 0B90031x311.0C90031x311.0214, 48, 1564, 16, 0214, 48, 1564, 16, 0214, 48, 1564, 16, 0B115635x351.0214, 120, 2084, 24, 0214, 120, 2084, 24, 0214, 120, 2084, 24, 42.51.0D176042.5x42.5E192445x45Page 6ZU17ZU19214, 48, 1564, 16, 0214, 48, 3124, 20, 0214, 48, 3124, 20, 0214, 72, 4164, 16, 0214, 72, 5724, 16, 0214, 72, 5724, 16, 0214, 96, 4164, 32, 16214, 96, 4164, 32, 161.0214, 48, 2604, 44, 28214, 48, 2604, 44, 281.0214, 96, 5724, 44, 0214, 96, 5724, 44, 0214, 48, 4164, 24, 0214, 48, 4164, 32, 0214, 96, 4164, 32, 16 Copyright 2016–2021 XilinxXMP104 (v2.5.1)Notes:1. PS I/O is a combination ofPS MIO and PS DDRIO.2. Packages with the same lastletter and number sequence,e.g., A484, are footprintcompatible with all otherUltraScale devices with thesame sequence.3. For full part number details,see the Ordering Informationsection in DS891, ZynqUltraScale MPSoC Overview.4. These packages are onlyoffered in 0.8mm ballpitch.All other packages areoffered in 1.0mm ball pitch.5. GTH transceivers in theC784 package support datarates up to 12.5Gb/s.
Zynq UltraScale MPSoC Device Migration TableThe Zynq UltraScale family provides footprint compatibility to enable users to migrate designs from one device to another.Any two packages with the same footprint identifier code (last letter and number sequence) are footprint compatible.Zynq UltraScale CG DevicesPkgEG DevicesEV DevicesmmZU1CG ZU2CG ZU3CG ZU4CG ZU5CG ZU6CG ZU7CG ZU9CG ZU1EG ZU2EG ZU3EG ZU4EG ZU5EG ZU6EG ZU7EG ZU9EG ZU11EG ZU15EG ZU17EG ZU19EG ZU4EVA48419 A4949.5x15 A5309.5x16A62521 C78423 B90031 C90031 B115635 C115635B151740F151740C176042.5D1760E1924ZU5EVZU7EV 42.5 45 XMP104 (v2.5.1)Page 7 Copyright 2016–2021 Xilinx
Zynq UltraScale MPSoC Speed GradesIndustrialExtended(2)Device Name(1)ZU1ZU2ZU3ZU4ZU5ZU6ZU7ZU9Speed GradeCG EG CG EG CG EG CG EG EV CG EG EV CG EG CG EG EV CG EGZU11EGZU15EGZU17EGZU19EG-1 -2 -2L -3––––––– – – – – -1 -1L -2 Notes:1. For full part number details, see the Ordering Information section in DS891, Zynq UltraScale MPSoC Overview.2.-2LE (Tj 0 C to 110 C). For more details, see the Ordering Information section in DS891, Zynq UltraScale MPSoC Overview. :: available– :: not offeredXMP104 (v2.5.1)Page 8 Copyright 2016–2021 Xilinx
Zynq UltraScale MPSoC Ordering InformationDevice AttributesDevice NameXCZU#XilinxCommercialZynqUltraScale ValueIndexEGProcessor Engine TypeSystemG: General PurposeIdentifier V: VideoC: Dual APUDual RPUE: Quad APUDual RPUSingle GPU-1Speed Grade-1: Slowest-L1: Low Power-2: Mid-L2: Low Power-3: FastestFF: Flip-chipw/ 1.0mm Ball PitchFootprintFVA#EF: LidB: LidlessV: RoHS 6/6PackageDesignatorPackagePin CountTemperatureGrade(E, I)S: Flip-chipw/ 0.8mm Ball PitchU: InFOw/ 0.5mm Ball PitchE Extended (Tj 0 C to 100 C)I Industrial (Tj –40 C to 100 C)Note: -L2E (Tj 0 C to 110 C). Refer to DS891, Zynq UltraScale MPSoC Overview for additional information.XMP104 (v2.5.1)Important: Verify all data in this document with the device data sheets found at www.xilinx.comPage 9 Copyright 2016–2021 Xilinx
ReferencesDS890, UltraScale Architecture and Product OverviewUG572, UltraScale Architecture Clocking Resources User GuideDS891, Zynq UltraScale MPSoC OverviewUG573, UltraScale Architecture Memory Resources User GuideDS925, Zynq UltraScale MPSoC Data Sheet: DC and AC SwitchingCharacteristicsUG574, UltraScale Architecture Configurable Logic Block User GuideUG1075, Zynq UltraScale MPSoC Packaging and PinoutsUG576, UltraScale Architecture GTH Transceivers User GuideUG578, UltraScale Architecture GTY Transceivers User GuideUG1085, Zynq UltraScale MPSoC Technical Reference ManualUG579, UltraScale Architecture DSP Slice User GuideUG1087, Zynq UltraScale MPSoC Register ReferenceUG580, UltraScale Architecture System Monitor User GuideUG1137, Zynq UltraScale MPSoC: Software Developers GuideUG583, UltraScale Architecture PCB and Pin Planning User GuideUG1169, Zynq UltraScale MPSoC QEMU: User GuideUG1186, Zynq UltraScale MPSoC OpenAMP: Getting Started GuidePG150, LogiCORE IP UltraScale Architecture-Based FPGAs MemoryInterface SolutionsUG571, UltraScale Architecture SelectIO Resources User GuidePG182, UltraScale FPGAs Transceivers Wizard Product GuideImportant: Verify all data in this document with the device data sheets found at www.xilinx.comXMP104 (v2.5.1)Page 10 Copyright 2016–2021 Xilinx
Security AMS - System Monitor RSA, AES, and SHA 10-bit, 1MSPS -Temperature and Voltage Monitor PS to PL Interface 12 x 32/64/128b AXI Ports) Programmable Functionality System Logic Cells (K) 192 256 504 CLB Flip-Flops (K) 176 234 461 CLB LUTs (K) 88 117 230 Memory Max. Distributed RAM (Mb) 2.6 3.5 6.2
