Accelerating FPGA/ASIC Design And Verification - MATLAB

Transcription

Accelerating FPGA/ASIC Design andVerificationTabrez Khan – Senior Application EngineerVidya Viswanathan – Application Engineer 2015 The MathWorks, Inc.1

Agenda Challeges with Traditional Implementation workflowModel-Based Design for ImplementationGenerate VHDL and Verilog code from MATLAB, Simulink, andStateflow Optimize the generated RTL design for area and/or speedDevelop system-level test benches in MATLAB and Simulink for RTLverification with EDA toolsAutomate verification with FPGA-in-the-LoopSummary & next steps2

Traditional Implementation Workflow DESIGN MATLABSimulinkStateflowAlgorithmDevelopmentLong development cyclesPrevents short iteration cyclesDifficult to optimize thealgorithm at a system levelFixed Point ConversionFPGA VerificationHDL Code CreationHDL VerificationHDL RefinementHDL Verification3

Separate Views of DSP twareDesigner4

Separate Views of DSP ImplementationSystem DesignerFPGA DesignerAlgorithm DesignSystem Test BenchRTL DesignVerificationFixed-PointEnvironment ModelsIP InterfacesBehavioral SimulationTiming / Control LogicAnalog ModelsHardware ArchitectureFunctional SimulationArchitecture ExplorationDigital ModelsStatic Timing AnalysisAlgorithms / IPAlgorithms / IPTiming SimulationImplement DesignFPGA RequirementsHardware SpecificationTest StimulusBack AnnotationSynthesisMapPlace & RouteFPGA Hardware5

Model-Based Design for ImplementationMATLAB and Simulink Algorithm and System DesignAlgorithm DesignSystem Test BenchRTL DesignVerificationFixed-PointEnvironment ModelsIP InterfacesBehavioral SimulationTiming / Control LogicAnalog ModelsHardware ArchitectureFunctional SimulationArchitecture ExplorationDigital ModelsStatic Timing AnalysisAlgorithms / IPAlgorithms / IPTiming SimulationImplement DesignFPGA RequirementsHardware SpecificationTest StimulusBack AnnotationSynthesisMapPlace & RouteFPGA Hardware6

Model-Based Design for ImplementationMATLAB and Simulink Algorithm and System DesignModel Refinement for HardwareAutomatic HDLCode GenerationRTL DesignVerificationIP InterfacesBehavioral SimulationHardware ArchitectureFunctional SimulationStatic Timing AnalysisTiming SimulationImplement DesignBack AnnotationSynthesisMapPlace & RouteFPGA Hardware7

Model-Based Design for ImplementationMATLAB and Simulink Algorithm and System DesignModel Refinement for HardwareVerificationBehavioral SimulationAutomatic HDLCode GenerationFunctional SimulationHDL Co-SimulationStatic Timing AnalysisBehavioral SimulationTiming SimulationImplement DesignBack AnnotationSynthesisMapPlace & RouteFPGA Hardware8

Model-Based Design for ImplementationMATLAB and Simulink Algorithm and System DesignModel Refinement for HardwareAutomatic HDLCode GenerationVerificationFunctional SimulationHDL Co-SimulationStatic Timing AnalysisBehavioral SimulationTiming SimulationImplement DesignBack AnnotationBack AnnotationSynthesisMapImplement DesignSynthesisMapPlace & RouteVerificationPlace & RouteFPGA HardwareFunctional SimulationStatic Timing AnalysisTiming Simulation9

Model-Based Design for ImplementationMATLAB and Simulink Algorithm and System DesignModel Refinement for HardwareAutomatic HDLCode GenerationHDL Co-SimulationBehavioral SimulationBack AnnotationImplement DesignSynthesisMapPlace & RouteVerificationFPGA HardwareFunctional SimulationStatic Timing AnalysisTiming SimulationFPGA HardwareFPGA-in-the-Loop10

Model-Based Design for ImplementationIntegrated WorkflowMATLAB and Simulink Algorithm and System DesignModel Refinement for HardwareAutomatic HDLCode GenerationHDL Co-SimulationBehavioral SimulationBack AnnotationImplement DesignSynthesisMapPlace & RouteVerificationFunctional SimulationStatic Timing AnalysisTiming SimulationFPGA HardwareFPGA-in-the-Loop11

Why Model-Based Design: Achieving the Shift-LeftReduce overall development time Reduced FPGA prototype development scheduleShorter design iteration cycle by 80%Improved product development time12

Automatic HDL Code GenerationHDL CoderAutomatically generate bit-true,cycle-accurate HDL code fromSimulink, MATLAB and StateflowFull bi-directionaltraceability!!13

HDL Code Generation Example14

Generate Verilog or VHDL code15

Code Generation Report Traceability Report Resource UtilizationReport Critical PathEstimation Report16

What’s new?Native Floating-PointGenerate target-independentsynthesizable RTL from single-precisionfloating-point models Good for:– Designs with high dynamic range calculations– Getting started prototyping FPGAs withouthaving to perform fixed-point conversion Mix integer, fixed-point, and floating pointoperations to balance numerical accuracyversus hardware resource usage Over 130 Simulink blocks supported Demo video» edit hdlcoderFocCurrentFloatScript17

HDL Optimizations: What, How and Why?Does thismeet timing?Does it fit onmy FPGA?The three golden questions:1. Speed:Does it meet timing?2. Area:Does it fit on my FPGA?3. Validation: Does it do the right thing?Does it do theright thing?FPGA EngineerHDL optimizations assists the engineer in meeting these constraints18

Critical Timing Path Critical path highlighting Helps you identify speed bottlenecks19

Speed OptimizationMaximum rate 145 MHzIs this the bestrate that al path Automatic pipelining Helps you meet speed objectives20

Speed OptimizationOutput Pipelining21

Speed OptimizationOutput PipeliningWhere do I placethe pipelineregisters?22

Speed OptimizationDistributed Pipelining23

Speed OptimizationDistributed PipeliningMaximum rate 235 MHz24

Area Optimization‘N’ (say 20) multipliers, eachrunning at 1 clock cycle1 multiplier running at ‘N’ (20)clock cycles25

Area OptimizationResource Sharing26

Area OptimizationResource Sharing27

Area OptimizationResource Sharing28

What’s new?Adaptive PipeliningSpecify synthesis tool and target clockfrequency for automatic pipelineinsertion and balancingTargetFrequency 500 Automatically inserts pipeline registers tomeet target frequency– On by default– Adds pipeline registers on parallel paths tobalance number of stages Good for:– Getting started prototyping FPGAs withoutworrying about manually inserting Delay blocks29

Integrated HDL VerificationMATLAB and Simulink Algorithm and System DesignModel Refinement for HardwareAutomatic HDLCode GenerationHDL Co-SimulationBehavioral SimulationBack AnnotationImplement DesignSynthesisMapPlace & RouteVerificationFunctional SimulationStatic Timing AnalysisTiming SimulationFPGA HardwareFPGA-in-the-Loop30

Co-Simulation with HDL SimulatorTest BenchSimulink Stimuli AlgorithmResultsTest BenchHDL VerifierProof your HDL matchesthe MATLAB/SimulinkspecificationRe-using MATLAB/SimulinktestbenchHDL Simulator31

Model-Based Design for ImplementationMATLAB and Simulink Algorithm and System DesignModel Refinement for HardwareAutomatic HDLCode GenerationHDL Co-SimulationBehavioral SimulationBack AnnotationImplement DesignSynthesisMapPlace & RouteVerificationFunctional SimulationFPGA HardwareStatic Timing AnalysisTiming SimulationFPGA HardwareFPGA in the Loop32

FPGA-in-the-Loop (FIL)for any HDL codePart of HDL Verifier Easy to setup using FIL Wizard Fast simulation – HDL runs on FPGA– Gigabit Ethernet data transferSupported Xilinx boardsKC 705ML605ML505ML506ML507XUP AtlysXUP-V5SP605SP601ML401ML402ML403Supported Altera boardsArria IIDE2-115Cyclone IIICyclone IV33

Automation FPGA-in-the-Loop VerificationIntegration with FPGAdevelopment boardsAdd your own FPGAboard (needs Ethernet)Automatic creation ofFPGA-in-the-Loopverification models34

New FPGA Families and Boards Supported by FIL FPGA Family– Virtex Ultrascale FPGA board– Artix-7 Arty (JTAG)– Virtex-7 VC709 (JTAG, PCIe)– Virtex Ultrascale VCU110 (JTAG)35

SystemVerilog DPI Test Bench Previously only available via command-line interfaceNow it’s available in Config Param as well as HDL Workflow Advisor36

HDL Verifier: HDL Code CoverageActivate HDL simulator code coveragein generated test benches Works for cosimulation, SystemVerilog DPI,or vector-based testbenchesSupports Mentor Graphics Questa Sim andCadence Incisive» makehdltb('sfir fixed/symmetric fir',.» 'GenerateSVDPITestBench','ModelSim', .» 'HDLCodeCoverage', 'on', )37

HDL Verifier: FPGA Data CaptureProbe internal FPGA signals to analyzein MATLAB or Simulink Debug signals in a free-running FPGAdirectly in MATLAB or SimulinkGenerates a block to add into theVHDL/Verilog design going onto the FPGACollects and visualizes the data in MATLABor SimulinkDemo video» generateFPGADataCaptureIPAvailable as part of HDL Verifier Xilinx/Intel hardwaresupport packages38

Harris Accelerates Verification of SignalProcessing FPGAsChallengeStreamline a time-consuming manual process fortesting signal processing FPGA implementationSolutionHarris FPGA-based system.Use HDL Verifier to verify the HDL design from within MATLABResults Functional verification time cut by more than 85% 100% of planned test cases completed Design implemented defect-free“HDL Verifier enabled us to greatlyreduce functional verificationdevelopment time by providing a directcosimulation interface between ourMATLAB model and our logic simulator.As a result, we verified our designearlier, identified problems faster,completed more tests, and compressedour entire development cycle.”Jason PlewHarris CorporationLink to user story39

Lockheed Martin Develops Configurable,Space-Qualified Digital Channelizer UsingMathWorks ToolsChallengeDesign and implement a reconfigurable, space-qualifieddigital channelizerSolutionArtist’s rendition of one of the satellitesthat will carry Lockheed Martin’s digitalchannelizer.Use Simulink to model and simulate the system, andHDL Verifier with Mentor Graphics ModelSim to verify theVHDL implementation“With Simulink and HDL Verifier,Resultssimulation and verification are Verification time reduced by 90% Overall development time shortened by eightmonths Key algorithms reused, saving 50% of design efforton subsequent projectsperformed in one environment. Asa result, we can test the designfrom end to end, improving qualityand ensuring design accuracy andvalidity."Bradford WatsonLockheed Martin Space SystemsLink to user story40

Summary Respect project timeline– Discover issues early through simulation– Fast code turnarounds allow better design trade-offs Collaborate in multidisciplinary teams ?– Use one Model for Design and Implementation– Seamlessly integrate version management– Graphically compare models Create working code– Analyze fixed-point impact before going to implementation– Auto-generate bug free code– Verify early through co-simulation with FPGA’s Achieve required efficiency– Optimize through advisors and automatic optimizations41

Call To ActionLearn more with recorded webinars & videos Accelerate Design Space Exploration Using HDL Coder OptimizationsUsing HDL Coder and HDL Verifier for FPGA and ASIC DesignsHDL Implementation and Verification of a High-Performance FFTUsing Custom Boards for FPGA-in-the-Loop VerificationA Guided Workflow for Zynq Using MATLAB and SimulinkHDL Verifier: FPGA Data Capture42

Generating HDL Code from Simulinktwo-day course shows how to generate and verify HDL code from a Simulink model using HDLCoder and HDL Verifier Topics include: Preparing Simulink models for HDL code generation Generating HDL code and testbench for a compatible Simulink model Performing speed and area optimizations Integrating handwritten code and existing IP Verifying generated HDL code using testbench and cosimulation43

Programming Xilinx Zynq SoCs with MATLAB and Simulinktwo-day course focuses on developing and configuring models in Simulink and deploying onXilinx Zynq -7000 All Programmable SoCs. For Simulink users who intend to generate, validate, anddeploy embedded code and HDL code for software/hardware codesign using Embedded Coder andHDL Coder .A ZedBoard is provided to each attendee for use throughout the course. The board is programmedduring the class and is yours to keep after the training.Topics include: Zynq platform overview and environment setup, introduction to Embedded Coder and HDLCoderIP core generation and deployment, Using AXI4 interfaceProcessor-in-the-loop verification, data interface with real-time applicationIntegrating device drivers, custom reference design44

DSP for FPGAsThis three-day course will review DSP fundamentals from the perspective of implementation within the FPGA fabric.Particular emphasis will be given to highlighting the cost, with respect to both resources and performance, associatedwith the implementation of various DSP techniques and algorithms.Topics include: Introduction to FPGA hardware and technology for DSP applicationsDSP fixed-point arithmeticSignal flow graph techniquesHDL code generation for FPGAsFast Fourier Transform (FFT) ImplementationDesign and implementation of FIR, IIR and CIC filtersCORDIC algorithmDesign and implementation of adaptive algorithms such as LMS and QR algorithmTechniques for synchronisation and digital communications timing recovery45

Speaker DetailsEmail: .inContact MathWorks IndiaProducts/Training Enquiry BoothCall: 080-6632-6000Email: info@mathworks.inYour feedback is valued.Please complete the feedback form provided to you.46

Programming Xilinx Zynq SoCs with MATLAB and Simulink two-day course focuses on developing and configuring models in Simulink and deploying on Xilinx Zynq -7000 All Programmable SoCs. For Simulink users who intend to generate, validate, and deploy embedded code and HDL code for software/hardware