Transcription
SoC Platform ManagementPresented ByJerry WongSystem Software & SoC Solutions – Product and Technical Marketing Copyright 2018 Xilinx
Overview ofPlatformManagement Part 1 of 4:Platform ManagementOverview and Boot Overview for those that arenew to Xilinx Copyright 2018 Xilinx
Platform Management FirmwarePlatformManagementContains Base FirmwareRequired Programmable Logic Configuration ManagerOptional Power Management FrameworkRequired Warm Restart ManagerOptional Functional Safety Software Test Library (STL)Optional User estartBase FWPage 3 Select from optional functions Copyright 2018 XilinxSTLUser(Tradeoff)
Platform Management Functions Associated MarketsPlatform ManagementFeaturePlatformManagementApplied Primary MarketsSecondary MarketsBoot & ConfigurationAllSecurityA&D, Auto, ISMWiredPartial ReconfigurationData CenterA&D, Auto, WiredPower ManagementA&D (MILCOM, SATCOM), AutoISMResetWired, A&DAuto, ISMFunctional SafetyAuto, ISMA&D (Aerospace & Defense)PL Health MonitorA&D, Space, Data CenterWiredNote: Functions can be selected up to the available 128KB RAM Often “enabling” functionsto various applications Copyright 2018 Xilinx
Customizing PMU Firmware Modules can be enabled in codexpfw config.hENABLE PMENABLE EMENABLE RTC TESTENABLE SCHEDULERENABLE SAFETY- Enable Power Management Module- Enable Error Management Module- Enable RTC Event Handler Test Module- Enable Scheduler Module- Enable Safety Code UART outputfw printf() – useful for standard debug techniquesDefault is to print on UART0 – can be changed to UART1 in BSP settings EEMI ImplementationFound in pm core.cPage 5 See PMU Firmware Wiki formore Copyright 2018 XilinxHow to selectPlatformManagementModules
Zynq UltraScale MPSoC BootLinux / HypervisorU-Boot FSBL (First Stage Boot Loader)Configures Processing Subsystem (PS)Loads Partitions - Bitstream, ATF, U-boot, & RPU-ApplicationARM Trusted FirmwareRPU SWFSBL PMU(Platform Management Unit) FirmwareProvides Platform Management Services - PowerManagement, Restart, Safety, Error Management, PL ConfigPMU FirmwareCSU Boot ROM ATF (ARM Trusted Firmware)Mandatory component of the ARMv8 security architecture U-BootUniversal Boot Loader, used by Linux Community Linux / RPU-SWDesign specific Software layers on APU or RPU respectively 6 Boot functions in order Copyright 2018 XilinxPMU Boot ROMARM CortexR5ARM CortexA53ProgrammableLogicGPUPlatformManagement
An Example - Understanding Boot LevelsPMUCSURelease CSUPlatform Management (PMU Firmware)Load FSBLTamper Monitoring (SEU, PS JTAG covered in Security Workshop)RPUAPUBootDependencies RPU (Lockstep mode)FSBLATFPLUBootLinuxBitstreamTime Boot has various dependencies Copyright 2018 Xilinx
FPGA Configuration ManagerSecurity andConfiguration Use CaseSecure/Non-Secure Bitstream Download from Linux/UBoot/RPU (See Security session)Linux (FPGA Manager)ATF Two Components for FPGA Manager in PMUxilsecure – Provides an interface to access CSU resources(SHA3, AES, RSA engines)xilfpga – Provides an interface for configuring PL via PCAP(Processor Configuration Access Port) from the PSSource available and up streamed to GitHubRuns as Secure MasterService can be used by A53 or R5 codeIPI is used as interface for the APIPMUFW uses xilfpga and xilsecure librariesto perform bitstream decryption, authentication and download Security is done during Configuration Copyright 2018 XilinxAPUPMUAPI SummaryPage 8IPIxilfpgaxilsecurePMU FW
Isolation Configuration Text and Tree Diagram applies toPower ManagementWarm RestartSafety Define Subsystems based on Use-caseSubsystem Restart - Restarts the subsystemfrom a clean state without effecting the otheractive subsystemsSubsystem idling is a function of idling of allcomponents of a defined subsystem Subsystems can be defined in Vivado viaisolation configuration menuPage 9 Define a tree once in Vivado Info is shared with other tools Copyright 2018 XilinxAssociateProcessors andPeripherals
PMU: Xilinx & User Firmware PMU Firmware extends the PMU ROM functionalityClosely interacts with the PMU ROM as neededSW Framework provided for management functions‒ For specialized applications may be customized for application specific tasksUses Inter-Processor Interrupts (IPI) standard to communicate with other on-chip Processors The home for critical platform management functions:PowerPost boot (after initial CSU PL configuration) programmable logic configurationWarm RestartFunctional Safety Software Test Library User Code – Xilinx provides frameworkSystem error handlingHigh reliability code . Loaded in PMU RAM by CSU ROM / FSBLPage 10 Many functions usable as-is Copyright 2018 XilinxPlatformManagementRecap
PowerManagement Part 2 of 4:Power Management Power state of shared peripheralsmanaged centrally Copyright 2018 Xilinx
Full Power DomainLow PowerDomainHS MIODomainsUSB3SGMIIGTRProcessor SystemIslandsACPACEMIOHPC(2)HPM(2)HP (4)PL LPDLPD PLBattery Power DomainEMIOConfigProgrammable Logic DomainGeneral Purpose IOHigh Density HDIOHigh Performance HPIOUltraRAMHigh Speed SERDESGTHGTY Copyright2018 XilinxDSPBlockRAMCustomizableLogicConcepts:Domains Islands
Platform Management for Zynq UltraScale Devices Dedicated Platform Management interface Key component of the Xilinx Power Management FrameworkImplements the core of EEMI EMIATFPage 13 Platform Management is builtaround communication Copyright 2018 XilinxBaremetalPlatformManagementArchitecture
Platform Management Software StackWhat iscommunicated Power Management Framework (PMF)APU UserapplicationRPU User applicationRTOS & Bare-metalPMU Bare-Metal3º Party OSLinuxXilPM APIsATF/PSCIPM requestPower Management APIsXilPM APIsPM requestPower Management APIsPower Management APIsPM APIsPM statePM stateRPUAPU UserapplicationPMUAPU PMU knows “state” and providescentral services to all Copyright 2018 Xilinx
Power Off Suspend to DDR Power Advantage Tool lets you seethe power of your design (ZCU102,ZCU106, ZCU111) Suspend to DDR retains DDRcontents via self-refresh. Allowsdetecting resume by the returnvalue of XPm GetBootStatus. Power Off Suspend to DDRsupports very low standby powerdesigns The Power Off state suspendsto a nice low standby power Copyright 2018 XilinxA samplepower state
What Typical Power States are Available Wiki example demonstratesTypical Power States(“Dimmer”):Other PowerStates PS mw PS Power States:Full PerformanceAPU Hotplug CoresAPU Frequency ScalingAPU SuspendFPD OffRPU SuspendDeep SleepPower Off SuspendFPD IdleLPDActiveUse case / mAFPDActiveLPDActiveFPD1 CoreLPDActiveFPD1 Core300 MHzLPDActiveFPD IdleLPDActiveFPD OffLPDActiveFPD OffLPDIdleFPD , Full PowerDomain (FPD)ONON1-APU ON,FPD ON1-APU ON,FPD ONAPU OFF,FPD ONOFFOFFOFFOFFRPU, Low PowerDomain (LPD)R5 Active,LPD ONR5 Active,LPD ONR5 Active,LPD ONR5 Active,LPD ONR5 Active,LPD ONR5 Active,LPD ONR5 IdleLPD ONR5 Off, LPDONOFFPL Domain (PLD)ONONONONONONONONOFFBattery Domain(BD)ONONONONONONONONON Several PS Power Statesthat require no coding Copyright 2018 Xilinx
Warm Restart Part 3 of 4:Warm Restart Copyright 2018 Xilinx
Warm Restart Manager Use CaseIndependent PS/PL/APU/RPU sub-systemrestarts SummaryEnables independent sub-system restarts‒ PMU is always alive and has access to controlregistersIPI/WDT error triggers restartPMU idles down peripherals and DMAsAsserts reset to subsystemLoads images‒ Offloaded to resident FSBL in the case of full PSRestartReleases resetsPage 18 Restart is typically used toCopyrightrecoverfrom error states 2018 XilinxFour WarmRestart Modes
Warm Restart ExamplePMURestart APUWarm RestartDependencies Platform Management (PMU Firmware)CSUTamper Monitoring (SEU, PS JTAG covered in Security Workshop)RPURPU (Lockstep mode)APUPLLinuxWDTFSBLATFUBootLinuxBitstreamTime Warm Restart is similar toBoot, other processors unaffected Copyright 2018 Xilinx
Safety Part 4 of 4:Functional Safety Copyright 2018 Xilinx
Safety/Reliability TMR Processors in PMUTriple Modular Redundancy VotingLogic Physical Diversity (R5 / PMU / CSU)Synthesized to different frequencytargetsDifferent net listsDifferent areasDifferent layoutsDifferent routing “Early” Separation of Clocks andResets to Individual CoresPage 21Safety Features ECCECC for PMU & CSU RAMs Memory interleaving to avoidmulti-bit error by SEUs (Single EventUpsets)8:1 interleaving reduces probability ofmulti-bit error to nil Independent memories for Data andECCSeparate address latchesReduces probability of address latchcorruption resulting in bad data‒ Ex. Bad address for ECC data will resultin “random” ECC for correct data Redundancy for reliability Copyright 2018 Xilinx
Functional Safety Software Test Library (STL)STL Features Complements hardware safety featuresby increasing Diagnostic Coverage Software Test Library Coverage– R5 Caches, TCMs & OCM– PMU RAM APIs execute periodicallyfor coverage of random hardwarefailuresE.g., Register checking, Interconnectchecking, Memory scrubbing etc. APIs execute on user demandfor latent failure coverageEx: XMPU (Xilinx Memory ProtectionUnit), SysMon, error injection, etc.Executes from: R5 and PMUPage 22– Low Power Domain Interconnect/Switch– Peripherals: Ethernet, CAN & UART– System Monitor– LPD General Interrupt Controller– LPD DMA– LPD Watchdog Timer– Error injection into LPD memories & R5lockstep– XMPU (Xilinx Memory Protection Unit),XPPU (Xilinx Peripheral Protection Unit– LPD reset/clock controller, LPD TTC,PMU TMR (Triple Modular Redundancy) Periodic test where there Copyrightis no 2018hardwareredundancy Xilinx
The Trifecta of Embedded References HW: Technical Reference Manual (TRM ug1085) SW: Software Developer’s Guide (SDG ug1137) Xilinx-specific: Embedded Design Tutorial (EDT ug1209)HardwareSoftwareTRMSDGXilinx-SpecificEDT Of the many documents Best three to start with Copyright 2018 XilinxWhat toreference
Backup Slides Copyright 2018 Xilinx
How to Estimate Power: Xilinx Power Estimator Xilinx Power Estimator (XPE)Spreadsheet to model PSPower, etc.Helps with power tradeoffsduring the evaluation phase ofyour low power mode.Fill out XPE, then discuss yourdesign with a Xilinx FAESuggests Power ManagementMethodologyDownload /xpe.html Compare many low powermode power tradeoffs Copyright 2018 XilinxTool toestimate power
EEMI: How Do We Control a Power Island PMU turns off any island whenit is not in use Copyright 2018 XilinxAPI Example #1Power Island
EEMI: How Do We Suspend a Processor Copyright 2018Xilinx PMU communicates / performsrequeststo suspend API Example #2Processor
Additional Security Features Key Revocation – Public Key Authentication Encrypt/Decrypt Algorithm Enhancement Key Agility Permanent Decryptor Disable Tamper Logging DPA Resistance Obfuscated Key Loading Key Readback Protections User Access to Crypto Functions Other Items Copyright 2018 Xilinx
Functional Safety Software Test Library (STL) Complements hardware safety features by increasing Diagnostic Coverage APIs execute periodically for coverage of random hardware failures E.g., Register checking, Interconnect checking, Memory scrubbing etc. APIs execute on user demand for latent failure coverage Ex: XMPU (Xilinx Memory Protection
