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9/21/2011ImplementingMATLAB and Simulink Algorithmsgon FPGAsStefano OlivieriSenior Application EngineerMathWorksMarco VisintiniSales Account ManagerMathWorksDaniele BagniDSP Specialist EMEAXilinx 2011 The MathWorks, Inc.1Agenda9:45Welcome10:00Reduce FPGA DevelopmentpTime with Model-Based Designg11:00Break11:15Integrated HDL Verification12:00Xilinx Target-optimized FPGA Design Using MATLAB and Simulink13:15Lunch14:15FPGA Design Optimization Techniques15:45Q&A, Summary and Wrap-up21
9/21/2011Introducing The SpeakersXilinx: Daniele BagniDSP Specialist EMEAMathWorks: Stefano OlvieriSenior Application EngineerSignal Processing and Communication Marco VisintiniSales Account Manager3MathWorks and Xilinx Goals MathWorks: accelerate the pace of engineering andscience by providing best in class Software for:– DevelopmentDe elopment and verificationerification of algorithms and control logic– Embedded Systems implementation Xilinx: providing best in class Silicon including FPGAsand embedded system hardware platforms :– Offers FPGAs and Zynq – an Extensible Processing Platform– PartnerP twithith MathWorksM thW k tot provideid an integratedi tt d workflowkfl Purpose of the joint seminar:– to demonstrate a Model-Based Design workflow for FPGAs from first idea down to the Hardware.42
9/21/2011MathWorks at a Glance Headquarters:N ti k MNatick,Massachusettshtt US Other US Locations:California, Michigan,Texas, Washington DC Europe:France, Germany, Italy,Spain, the Netherlands,Sweden, Switzerland, UK Asia-Pacific:Australia, China, India,Japan, Korea Worldwide trainingand consulting Distributors in 25 countriesEarth’s topography on an equidistant cylindrical projection,created with MATLAB and Mapping Toolbox.5MathWorks Today 1984Revenues 600M in 2010Privately heldMore than 2000 employees worldwideWorldwide revenue balance:45% North America, 55% internationalMore than 1 million users in 175 countries1989199419992004200963
9/21/2011Key Industries Aerospace and DefenseAutomotiveBiotech and PharmaceuticalCommunicationsEducationElectronics and SemiconductorsEnergy ProductionFinancial ServicesIndustrial Automation andMachinery7Who is Who? Who is a System Engineer? Wh iis an FPGA designersWhod i? Who is using MATLAB? Who is using Simulink?104
9/21/2011Your Expectations Beyond the Agenda.11Corner Detection in Video Mosaicking(A Brief Example)135
9/21/2011Things to remember .DESIGNAlgorithmDevelopmentMATLABSimulinkStateflow Use Model-Based Design to providean integrated workflow Speed up algorithm developmentwith a unified design environment Automate manual steps inFPGA implementation to enableshorter iteration cyclesy Integrate FPGA development tools toreduce verification time14Agenda9:45Welcome10:00Reduce FPGA DevelopmentpTime with Model-Based Designg11:00Break11:15Integrated HDL Verification12:00Xilinx Target-optimized FPGA Design Using MATLAB and Simulink13:15Lunch14:15FPGA Design Optimization Techniques15:45Q&A, Summary and Wrap-up156
9/21/2011Why do we use FPGAs? Customized interfaces toperipheralsMemoryMemoryMemoryHigh-speed communicationinterfaces to otherprocessorsFinite state machines, digitallogic, timing and memorycontrolWe are goingto focus onthis use casetodayBridgeAnalog I/OFPGAARMDigital I/OHigh speed, highly parallelDSP Algorithms or ControlAlgorithmsDSPDSPAlgorithms16Separate Views of DSP ImplementationSystem DesignerFPGA DesignerAlgorithm DesignSystem Test BenchRTL DesignVerificationFixed-PointEnvironment ModelsIP InterfacesBehavioral SimulationHW ArchitectureTiming / Control LogicAnalog ModelsArchitecture ExplorationDigital ModelsAlgorithms / IPAlgorithms / IPTiming SimulationImplement DesignFPGA RequirementsHardware SpecificationTest StimulusFunctional SimulationStatic Timing AnalysisBack AnnotationSynthesisMapPlace & RouteFPGA Hardware177
9/21/2011Where do you spend most of your time?System Designer Algorithm DesignSystem Test BenchFixed-PointEnvironment ModelsTiming / Control LogicAnalog ModelsArchitecture ExplorationDigital ModelsAlgorithms / IPAlgorithms / IP FPGA Requirements Simulating designs?Creating designs and testbenches?Analyzing and combining resultsfrom multiple tools?Exploring implementation ideasand architectures?Floating point to fixed-point?Writing HW specifications?Hardware SpecificationTest Stimulus Iterating over designs with theFPGA designer?Blaming the FPGA designer?18Where do you spend most of your time? Simulating designs and validatingagainst HW specs?Creating designs and writing testbenches?Hardware architecture design?Writing interfaces to existing IP?Synthesis, Map, PAR cycles?FPGA DesignerRTL DesignVerificationIP InterfacesBehavioral SimulationHardware ArchitectureTiming SimulationImplement Design Iterating over designs with thesystem designer?Blaming the system designer?Functional SimulationStatic Timing AnalysisBack AnnotationSynthesisMapapPlace & RouteFPGA Hardware198
9/21/2011A Few Ways to Reduce Development Time1.2.3.4.Increase simulation speedSimplify design entry, system test harnesscreation, and explorationShorter iteration cycles required for RTL design& verificationIntegrate the separate workflows to facilitatecollaboration, re-use, and prototyping20Model-Based Design for ImplementationMATLAB and Simulink Algorithm and System DesignAlgorithm DesignSystem Test BenchRTL DesignVerificationFixed-PointEnvironment ModelsIP InterfacesBehavioral SimulationHardware ArchitectureTiming / Control LogicAnalog ModelsArchitecture ExplorationDigital ModelsAlgorithms / IPAlgorithms / IPTiming SimulationImplement DesignFPGA RequirementsHardware SpecificationTest StimulusFunctional SimulationStatic Timing AnalysisBack AnnotationSynthesisMapPlace & RouteFPGA Hardware219
9/21/2011Model-Based Design for ImplementationMATLAB and Simulink Algorithm and System DesignModel Refinement for HardwareRTL DesignVerificationIP InterfacesBehavioral SimulationHardware ArchitectureAutomatic HDLCode GenerationFunctional SimulationStatic Timing AnalysisTiming SimulationImplement DesignBack AnnotationSynthesisMapPlace & RouteFPGA Hardware22Model-Based Design for ImplementationMATLAB and Simulink Algorithm and System DesignModel Refinement for HardwareVerificationBehavioral SimulationAutomatic HDLCode GenerationFunctional SimulationHDL CoCo-SimulationStatic Timing AnalysisBehavioral SimulationTiming SimulationImplement DesignBack AnnotationSynthesisMapPlace & RouteFPGA Hardware2310
9/21/2011Model-Based Design for ImplementationMATLAB and Simulink Algorithm and System DesignModel Refinement for HardwareAutomatic HDLCode GenerationVerificationFunctional SimulationHDL CoCo-SimulationStatic Timing AnalysisBehavioral SimulationTiming SimulationImplement DesignBack AnnotationBack AnnotationSynthesisMapImplement DesignVerificationPlace & RouteFPGA HardwareFunctional SimulationSynthesisStatic Timing AnalysisMapTiming SimulationPlace & Route24Model-Based Design for ImplementationMATLAB and Simulink Algorithm and System DesignModel Refinement for HardwareAutomatic HDLCode GenerationHDL CoCo-SimulationBehavioral SimulationBack AnnotationImplement DesignSynthesisMapPlace & RouteVerificationFPGA HardwareFunctional SimulationStatic Timing AnalysisTiming SimulationFPGA HardwareFPGA-inFPGAin-thethe--Loop2511
9/21/2011Why Model-Based Design?MATLAB and Simulink Algorithm and System DesignModel Refinement for HardwareAutomatic HDLCode GenerationHDL CoCo-Simulation Use Model-Based Design toprovide an integratedworkflow Speed up algorithmdevelopment with a unifieddesign environment Automate manual steps inFPGA implementation toenable shorter iterationcycles Integrate FPGA developmenttools to reduce verificationtime27Behavioral SimulationBack AnnotationImplement DesignSynthesisMapPlace & RouteVerificationFunctional SimulationStatic Timing AnalysisTiming SimulationFPGA HardwareFPGA-inFPGAin-thethe--LoopAT4 wireless Increases Internal TestCoverage to Over 90% for LTE PhysicalLayer Test Equipment DesignsChChallengellDevelop test systems for LTE wireless equipmentAT4 wireless LTE layer 1 tester.SolutionUse MATLAB and Simulink to design and simulate theLTE physical layer, verify the FPGA implementation,and analyze test resultsResults Internal test coverage increased to over 90% Test harness reused throughout the projectlife cycle Development effort reduced by 25–30%“MATLAB is a universal language thatmakes it easy to exchange algorithmsand test results across our team. Ourphysical layer model in MATLAB andSimulink enabled us to betterunderstand the LTE specifications, andModel-Based Design enabled us toverify that our FPGA implementationconformed to those specifications.”Francisco Javier CamposAT4 wirelessLink to user story2912
9/21/2011Semtech Speeds Development ofDigital Receiver FPGAs and ASICsChallengegAccelerate the development of optimized digitalreceiver chains for wireless RF devicesThe Semtech SX1231 wireless transceiver.SolutionUse MathWorks tools for Model-Based Design togenerate production VHDL code for rapid FPGAand ASIC implementationResults Prototypes created 50% faster Verification time reduced from weeks to days Optimized, better-performing design delivered“Writing VHDL is tedious, and thehandwritten code still needs to beverified. With Simulink and SimulinkHDL Coder, once we have simulatedthe model we can generate VHDLdirectly and prototype an FPGA. Itsaves a lot of time, and the generatedcode contains some optimizations wehadn’t thought of.”Frantz PrianonSemtechLink to user story30Case Study: Corner Detection Algorithm 2011 The MathWorks, Inc.3113
9/21/2011Harris-Stephens’ Corner Detection Corner detection is used in many Image Processingapplications– Image mosaicking– Tracking– Object recognition32Harris-Stephens’ Corner DetectionHorizontal GradientCorner Metric McVertical GradientSobel EdgeFilterCalculate CornerMetricsThreshold &Find LocalMaxima3314
9/21/2011From Algorithm to Synthesizable RTLMATLAB and Simulink Algorithm and System DesignModel Refinement for HardwareAutomatic HDLCode GenerationHDL CoCo-SimulationBehavioral SimulationBack AnnotationImplement DesignSynthesisMapPlace & RouteVerificationFunctional SimulationStatic Timing AnalysisTiming SimulationFPGA HardwareFPGA-inFPGAin-thethe--Loop34Flexible Design EnvironmentDesign, Simulation and Implementation Choice of best modeling methods(Simulink, MATLAB and Stateflow)Integrate with MATLAB Algorithm Design3515
9/21/2011Fixed Point AnalysisCorner Detection Convert floating point to optimized fixed point models– Automatic tracking of signal range (also intermediate quantities)– Word / Fraction lengths recommendationAutomatically Bit-true models in the same environmentidentify and solvefixed point issues36Automatic HDL Code GenerationCorner DetectionAutomatically generate bit true,cycle accurate HDL code fromSimulink, MATLAB and StateflowFull bi-directionaltraceability!!Requirements3716
9/21/2011Simulink Library Support for HDLHDL Supported Blocks 170 blocks supported Core Simulink Blocks– Signal Processing Blocks– Basic and Array Arithmetic, Look-Up Tables,Signal Routing (Mux/Demux, Delays,Selectors), Logic & Bit Operations, Dual andsingle port RAMs, FIFOs, CORDICsNCOs,, FFTs,, DigitalgFilters (FIR,(, IIR,, Multirate, Adaptive), Rate Changes (Up &DownSample), Statistics (Min/Max)Communications Blocks–Psuedo-random Sequence Generators,Modulators / Demodulators, Interleavers /Deinterleavers, Viterbi Decoders38MATLAB & Stateflow for HDLHDL Supported Blocks MATLAB– Relevant subset of the MATLABlanguage for modeling and generatingHDL implementations– eml hdl design patterns:Useful MATLAB Function Block DesignPatterns for HDL Stateflow– Graphical tool for modeling Mealyand Moore Finite State Machines3917
9/21/2011Integrating Legacy HDL CodeHDL Supported BlocksIntegrate legacy HDL codein Simulink using blackboxesConfigure the interface tolegacy HDL codeEDA Simulator Link is aspecial black box40Summary: Modeling and Code Generation Model-Based Design provides an integrated workflow– Optimized design on a System Level Speed up algorithm development with a unified designenvironment– Collaborate with other engineers– Use Simulink blocks, Stateflow or MATLAB for modeling andimplementation Shorter iteration cycles– Assisted Fixed-Point Conversion– Automatic HDL Code Generation4118
9/21/2011Break42Things to remember .DESIGNAlgorithmDevelopmentMATLABSimulinkStateflow Use Model-Based Design to providean integrated workflow Speed up algorithm developmentwith a unified design environment Automate manual steps inFPGA implementation to enableshorter iteration cyclesy Integrate FPGA development tools toreduce verification time4319
9/21/2011Wh t wouldWhatld you likelik tot gettfrom automatic codegeneration?44Hardware Design Challenges:Optimizing for Speed, Area or flow Optimize HDL code Verify optimized HDL Place & Route Analyze result4520
9/21/2011IIR Low Pass FilterDirect-Form II Transposed SOS46From Algorithm to Optimized RTLMATLAB and Simulink Algorithm and System DesignModel Refinement for HardwareAutomatic HDLCode GenerationHDL CoCo-SimulationBehavioral SimulationBack AnnotationImplement DesignSynthesisMapPlace & RouteVerificationFunctional SimulationStatic Timing AnalysisTiming SimulationFPGA HardwareFPGA-inFPGAin-thethe--Loop4721
9/21/2011Hardware Design Challenges:Speed OptimizationFinding the critical path in your modelcan be challenging48Demo: HDL Workflow Advisor Choose target workflow: FPGA-in-the-LoopFPGA TurnkeyDesign exploration:Generic ASIC/FPGAChoose FPGA target4922
9/21/2011Demo: HDL Workflow AdvisorPerform relevantchecks for HDLcode generation50Demo: HDL Workflow AdvisorSet options and generateautomatically HDL code5123
9/21/2011Demo: HDL Workflow AdvisorCreate FPGA projectRun P&R-andAnnotate timing informationAutomated workflow from model to FPGA Analysis &Implementation52Identifying the critical pathSpeed OptimizationCritical Path highlighting: Visual representation of critical path in your model Easier to identify bottlenecks of your model5324
9/21/2011Balancing pipeline registersSpeed Optimizationparallelpaths critical pathMultiple parallel paths through your modelHigh risk to have unmatched latencies54Demo: Configuring Pipelining OptionsSpeed Optimization5525
9/21/2011Distributed PipeliningSpeed Optimization Distributed pipelining (model retiming)Automatic balancing of pipeline registers(focus on critical path only)You are in full control of your pipelining strategy Bottom-up and top-down56Distributed PipeliningSpeed OptimizationMinimum period: 23.796nsMaximum Frequency: 42.024MHz42 024MHzSection 1Section 3Section 2Device,package,speed:xc5vsx50t,ff1136,-15726
9/21/2011Distributed PipeliningSpeed OptimizationMinimum period: 9.379nsMaximum Frequency: 106.62MHz106 62MHzSection 3Section e Design Challenges:Area OptimizationXXXXMUXDEMUXSCHEDULINGXXX5927
9/21/2011IIR Low Pass FilterDirect-Form II Transposed SOSChallenges: Data dependent resources to be shared Feedback loops Vectorized inputs60Demo: Configuring Sharing OptionsArea Optimization6128
9/21/2011Resource Sharing and StreamingArea Optimization Easy to explore different sharing optionsDirect feedback through resource utilization reportProve correctness through validation models62Hardware Design Challenges:Power Optimization Power Dissipation Static Power Dynamic Power– Static Power Due to transistor leakage current Significant in smaller silicon geometries– Dynamic Power CV2f Function of load capacitance, operating frequency, and voltage swing6329
9/21/2011Better Algorithm DesignPower Optimization Steps To Reduce Power––––Smaller/Efficient DesignsReduce Clock FrequencyControl Subsystem Execution (enabled/triggered subsystems)Low Power Design Libraries/FPGA Devices64Multi-rate Models to Reduce Clock FrequencyPower Optimization Cycle accurate simulation and implementationMultiplep or singleg clock implementationpclk enableclkclk enableenb 1 2 1Timing Controllerenb 1 2 06530
9/21/2011Control Subsystem ExecutionPower OptimizationEnabled Subsystems Modules can be enabled and disabled66Control Subsystem ExecutionPower OptimizationTriggered Subsystems Modules can be triggered:ggrisingg / fallingg / either edgeg6731
9/21/2011Harris-Stephens’ Corner Detection How do these techniques work with our CornerDetection algorithm?68Summary: Corner Detection DemoMultipliersAdders/SubtractorsRegisters 0RAMsMultiplexers2Multiplexers6466794302Easy approach to explore different implementationsNo costly mistakes6932
9/21/2011Summary: Code Generation Optimizations Shorter iteration cycles– Automatic HDL code generation Flexible automatic HDL Code generation–––––Speed OptimizationArea OptimizationMake the right design choices to save powerAnalyze implementation results, resource utilization reportValidation models to prove that implementation is correct71Agenda9:45Welcome10:00Reduce FPGA DevelopmentpTime with Model-Based Designg11:00Break11:15Integrated HDL Verification12:00Xilinx Target-optimized FPGA Design Using MATLAB and Simulink13:15Lunch14:15FPGA Design Optimization Techniques15:45Q&A, Summary and Wrap-up7233
9/21/2011Things to remember .DESIGNAlgorithmDevelopmentMATLABSimulinkStateflow Use Model-Based Design to providean integrated workflow Speed up algorithm developmentwith a unified design environment Automate manual steps inFPGA implementation to enableshorter iteration cyclesy Integrate FPGA development tools toreduce verification time73HDL Verification How do yyou do HDL verification today?y7434
9/21/2011Verification Challenges:HDL Verification Design the Test Bench twice– 10 – to – 1 ratio of Test bench LOC – to – Design LOCMany stimuli-files from MATLABThese are ideal references which require pre- and postprocessingHow to analyze results?75Verification Challenges:HDL VerificationDemo: Re-Use System Level Test Bench7635
9/21/2011Digital Down Converter DDC acceptsp– A high sample-rate passband signal (may be 50 to 100 Msps) DDC produces– A low sample-rate baseband signal ready for demodulation 70 MSPSRFSection 270 KSPSDigitalDownConverterA/DConvDemod77Integrated HDL VerificationMATLAB and Simulink Algorithm and System DesignModel Refinement for HardwareAutomatic HDLCode GenerationHDL CoCo-SimulationBehavioral SimulationBack AnnotationImplement DesignSynthesisMapPlace & RouteVerificationFunctional SimulationStatic Timing AnalysisTiming SimulationFPGA HardwareFPGA-inFPGAin-thethe--Loop7836
9/21/2011Verify Handwritten HDL Vector-BasedDigital Down ConverterWhat is the impact ofthese differences?Difficult to analyzesimulation results79Co-Simulation with HDL simulatorsDigital Down ConverterRe-use system level testbenchDirect simulation link toHDL SimulatorsFlexible testbenchcreation in SimulinkAutomatically generatedHDL co-simulationmodelsDifference is small and inthe stopband of the filter8037
9/21/2011Additional Methods for VerificationHDL Verification Techniques Co-simulation with MATLAB– Test Bench– Component Generate vector based test benches forstandalone verification FPGA-in-the-Loop81Integrate MATLAB Algorithm DevelopmentCo-Simulation with MATLABMATLABTest Bench Verify HDL against high-levelhigh levelMATLAB designHDL SimulatorComponent R lReplacea “Broken”“B k ” or un-finishedfi i h dblock in a full HDL test bench with aworking high level componentTest alternate algorithms for systemtrade-off without developing HDL8238
9/21/2011Harris Accelerates Verification of SignalProcessing FPGAsChChallengellStreamline a time-consuming manual process fortesting signal processing FPGA implementationHarris FPGA-based system.SolutionUse EDA Simulator Link to verify the HDL designfrom within MATLAB“EDA Simulator Link enabled us toResultsdevelopment time by providing a direct Functional verification time cut by more than 85% 100% of planned test cases completed Design implemented defect-freegreatly reduce functional verificationcosimulation interface between ourMATLAB model and our logic simulator.As a result, we verified our designearlier, identified problems faster,completed more tests, and compressedour entire development cycle.”Jason PlewHarris CorporationLink to user story83Collaborate with Other Design TeamsTest Benches for Standalone VerificationCompile and simulationscripts are providedAutomatically generateself-checking testbenchesCan be used in any HDLSimulator8439
9/21/2011Challenges:Testing algorithms on real hardware Motivation:building confidenceBut interfaces with pperipheralsp& rest of the system neededDifficult to construct testbenches inreal hardwareDemo: Re-Use System Level test bench86FPGA-in-the-Loop verificationDigital Down ConverterIntegration with FPGAdevelopment boardsAutomatic creation ofFPGA-in-the-Loopverification models8740
9/21/2011FPGA-in-the-Loop verificationDigital Down ConverterRe-use system level testbench for FPGAverificationFlexible testbenchcreation in SimulinkBuilding confidence thatthe design works on realhardware88Summary: Verification Integration of FPGA development tools enhancesverification–Improved analysis, flexible testbench creation(multi domain, feedback loops)–Integration with HDL verification–Integration with FPGA verificationA tomation giAutomationgiveses shorter iteration ccyclescles– Automatically generated verification models for: HDL Co-Simulation FPGA-in-the-Loop– Wizards for legacy HDL code8941
9/21/2011From Algorithm to FPGA ImplementationMATLAB and Simulink Algorithm and System DesignModel Refinement for HardwareSimulink HDL CoderRTL CreationEDA Simulator LinkModelSimHDL CoCo--SimulationBehavioral SimulationBack AnnotationImplement DesignSynthesisMapPlace & RouteVerificationFunctional SimulationStatic Timing AnalysisTiming SimulationEDA Simulator 0:00Reduce FPGA DevelopmentpTime with Model-Based Designg11:00Break11:15Integrated HDL Verification12:00Xilinx Target-optimized FPGA Design Using MATLAB and Simulink13:15Lunch14:15FPGA Design Optimization Techniques15:45Q&A, Summary and Wrap-up9142
9/21/2011Agenda9:45Welcome10:00Reduce FPGA DevelopmentpTime with Model-Based Designg11:00Break11:15Integrated HDL Verification12:00Xilinx Target-optimized FPGA Design Using MATLAB and Simulink13:15Lunch14:15FPGA Design Optimization Techniques15:45Q&A, Summary and Wrap-up92Agenda9:45Welcome10:00Reduce FPGA DevelopmentpTime with Model-Based Designg11:00Break11:15Integrated HDL Verification12:00Xilinx Target-optimized FPGA Design Using MATLAB and Simulink13:15Lunch14:15FPGA Design Optimization Techniques15:45Q&A, Summary and Wrap-up9343
9/21/2011Things to remember .DESIGNAlgorithmDevelopmentMATLABSimulinkStateflow Use Model-Based Design to providean integrated workflow Speed up algorithm developmentwith a unified design environment Automate manual steps inFPGA implementation to enableshorter iteration cyclesy Integrate FPGA development tools toreduce verification time94ROI: Customer Adoption Of Model-Based DesignTime spent on FPGA/ASIC implementation Shorter implementation time by 48% (total project 33%)Reduced FPGA prototype development schedule by 47%Shorter design iteration cycle by 80%1st FPGA Prototype2nd FPGA Prototype1st FPGA Prototype9544
9/21/2011How to adopt MathWorks technologies? MathWorks tools pprovide a technologygy to speedpuppdevelopmentMathWorks services provide the support to roll out thistechnology in your organization96Example MathWorks Services MathWorks Training– Private training “Simulink HDL Coder”– Public training “SignalSignal Processing with MATLAB/SimulinkMATLAB/Simulink”Fundamental trainings for uniform knowledge, quick ramp up MathWorks Consulting– Jumpstart service to get you up and running quickly withSimulink HDL Coder– Advisory service for ongoing expert advice during technology adoption– Based on industry experience, assistance with tailoring workflow– On site expert customization / optimization of your workflow Technical Support– Comprehensive, product-specific Web support resources– 70% cases solved within 24 hours– Included in Software Maintenance Service9745
9/21/2011Were Your Expectations Met? Please complete and return seminar surveyforms Your comments and feedback are veryimportant to us99Next Steps 1.2.Visit www.mathworks.com/fpgapgfor more informationVisit www.xilinx.com/dspfor more information3.Watch our FPGA webinars:– www.mathworks.com/company/events/webinarsthk//t / bi4.Contact your local sales reps for a trial of our FPGA toolsQuestions?10046
“MATLAB is a universal language that makes it easy to exchange algorithms and test results across our team. Our physical layer model in MATLAB and Simulink enabled us to better AT4 wireless LTE layer 1 tester. 29 Test harness reused throughout the project life cycle Development effort
