MPC5777C , MPC5777C Microcontroller Data Sheet

Transcription

NXP SemiconductorsData Sheet: Technical DataDocument Number MPC5777CRev. 15, 03/2021MPC5777CMPC5777C MicrocontrollerData SheetFeatures This document provides electrical specifications, pinassignments, and package diagram information for theMPC5777C series of microcontroller units (MCUs). For functional characteristics and the programmingmodel, see the MPC5777C Reference Manual.NXP reserves the right to change the production detail specifications as may berequired to permit improvements in the design of its products.

Table of Contents1 Introduction. 33.11 Power management: PMC, POR/LVD, power sequencing.391.1Features summary.33.11.1Power management electrical characteristics.391.2Block diagram. 43.11.2Power management integration. 422 Pinouts.53.11.3Device voltage monitoring. 433.11.4Power sequencing requirements. 452.1416-ball MAPBGA pin assignments. 52.2516-ball MAPBGA pin assignments. 63.12 Flash memory specifications. 463 Electrical characteristics.73.12.1Flash memory program and erase specifications. 473.12.2Flash memory Array Integrity and Margin Read3.1Absolute maximum ratings. 73.2Electromagnetic interference (EMI) characteristics.93.3Electrostatic discharge (ESD) characteristics.93.12.3Flash memory module life specifications.483.4Operating conditions. 93.12.4Data retention vs program/erase cycles.493.5DC electrical specifications.123.12.5Flash memory AC timing specifications. 493.6I/O pad specifications. 133.12.6Flash memory read wait-state and address-3.73.83.6.1Input pad specifications.13pipeline control settings.503.6.2Output pad specifications. 153.13 AC timing. 513.6.3I/O pad current specifications.183.13.1Generic timing diagrams. 51Oscillator and PLL electrical specifications.193.13.2Reset and configuration pin timing. 513.7.1PLL electrical specifications. 203.13.3IEEE 1149.1 interface timing. 523.7.2Oscillator electrical specifications.213.13.4Nexus timing. 55Analog-to-Digital Converter (ADC) electrical specifications.233.13.5External Bus Interface (EBI) timing. 573.8.1Enhanced Queued Analog-to-Digital Converter3.13.6External interrupt timing (IRQ/NMI pin).61(eQADC). 233.13.7eTPU timing. 62Sigma-Delta ADC (SDADC). 253.13.8eMIOS timing.63Temperature Sensor.323.13.9DSPI timing with CMOS and LVDS pads.643.13.10FEC timing. 773.8.23.9specifications. 473.10 LVDS Fast Asynchronous Serial Transmission (LFAST) padelectrical characteristics.333.10.1LFAST interface timing diagrams.333.10.2LFAST and MSC/DSPI LVDS interface electrical3.10.34 Package information.814.1Thermal characteristics.814.1.1General notes for thermal characteristics. 82characteristics. 355 Ordering information.85LFAST PLL electrical characteristics. 386 Document revision history. 86MPC5777C Microcontroller Data Sheet, Rev. 15, 03/20212NXP Semiconductors

Introduction1 Introduction1.1 Features summaryOn-chip modules available within the family include the following features: Three dual issue, 32-bit CPU core complexes (e200z7), two of which run in lockstep Power Architecture embedded specification compliance Instruction set enhancement allowing variable length encoding (VLE), optionalencoding of mixed 16-bit and 32-bit instructions, for code size footprintreduction On the two computational cores: Signal processing extension (SPE1.1)instruction support for digital signal processing (DSP) Single-precision floating point operations On the two computational cores: 16 KB I-Cache and 16 KB D-Cache Hardware cache coherency between cores 16 hardware semaphores 3-channel CRC module 8 MB on-chip flash memory Supports read during program and erase operations, and multiple blocksallowing EEPROM emulation 512 KB on-chip general-purpose SRAM including 64 KB standby RAM Two multichannel direct memory access controllers (eDMA) 64 channels per eDMA Dual core Interrupt Controller (INTC) Dual phase-locked loops (PLLs) with stable clock domain for peripherals andfrequency modulation (FM) domain for computational shell Crossbar Switch architecture for concurrent access to peripherals, flash memory, orRAM from multiple bus masters with End-To-End ECC External Bus Interface (EBI) for calibration and application use System Integration Unit (SIU) Error Injection Module (EIM) and Error Reporting Module (ERM) Four protected port output (PPO) pins Boot Assist Module (BAM) supports serial bootload via CAN or SCI Three second-generation Enhanced Time Processor Units (eTPUs) 32 channels per eTPU Total of 36 KB code RAM Total of 9 KB parameter RAMMPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021NXP Semiconductors3

Introduction Enhanced Modular Input/Output System (eMIOS) supporting 32 unified channelswith each channel capable of single action, double action, pulse width modulation(PWM) and modulus counter operation Two Enhanced Queued Analog-to-Digital Converter (eQADC) modules with: Two separate analog converters per eQADC module Support for a total of 70 analog input pins, expandable to 182 inputs with offchip multiplexers Interface to twelve hardware Decimation Filters Enhanced "Tap" command to route any conversion to two separate DecimationFilters Four independent 16-bit Sigma-Delta ADCs (SDADCs) 10-channel Reaction Module Ethernet (FEC) Two PSI5 modules Two SENT Receiver (SRX) modules supporting 12 channels Zipwire: SIPI and LFAST modules Five Deserial Serial Peripheral Interface (DSPI) modules Five Enhanced Serial Communication Interface (eSCI) modules Four Controller Area Network (FlexCAN) modules Two M CAN modules that support FD Fault Collection and Control Unit (FCCU) Clock Monitor Units (CMUs) Tamper Detection Module (TDM) Cryptographic Services Engine (CSE) Complies with Secure Hardware Extension (SHE) Functional SpecificationVersion 1.1 security functions Includes software selectable enhancement to key usage flag for MACverification and increase in number of memory slots for security keys PASS module to support security features Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard, with somesupport for 2010 standard Device and board test support per Joint Test Action Group (JTAG) IEEE 1149.1 and1149.7 On-chip voltage regulator controller (VRC) that derives the core logic supply voltagefrom the high-voltage supply On-chip voltage regulator for flash memory Self Test capabilityMPC5777C Microcontroller Data Sheet, Rev. 15, 03/20214NXP Semiconductors

Pinouts1.2 Block diagramThe following figure shows a top-level block diagram of the MPC5777C. The purpose ofthe block diagram is to show the general interconnection of functional modules throughthe crossbar switch.COMPUTATIONAL SHELLFLEXCAN A-BMCAN 0-1e200z7 checkercore complexSWTe200z7(dual issue)e200z7(dual issue)STMINTCFPUDEBUGSWTSTMJTAGMMUNexus 3 DTSDSPI A-CeSCI A-CINTCFPUETPU Cw/RAMVLEVLE16K I-Cache16K I-Cache64ch eDMA16K D-Cache16K D-Cache64ch eDMAMMUMMUEtherneteMIOS 0eQADC A& Temp SensorsDECFILTER A-LSDADC 1/3SRX 0Crossbar Switch with ECCSafetyMonitorMPUPSI5 0REACM2SRAMControlEBIFlash ControlZipwire/SIPI/LFASTBridge ADual PLL/OSC/IRCSecurityTamperDetectionCRCCSESRAMFlash w/ EEPROMBridge BPCM/ERMSIU/SIU BCMU 0-8EBI registersFCCUSTCUPMU/PMCPIT-RTIFlexCAN C-DDSPI D-EeSCI D-FETPU A/B(w/RAM)eMIOS 1eQADC BSDADC 2/4SRX 1PSI5 1Figure 1. MPC5777C block diagram2 Pinouts2.1 416-ball MAPBGA pin assignmentsFigure 2 shows the 416-ball MAPBGA pin assignments.MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021NXP Semiconductors5

PinoutsFigure 2. MPC5777C 416-ball MAPBGA (full diagram)2.2 516-ball MAPBGA pin assignmentsFigure 3 shows the 516-ball MAPBGA pin assignments.MPC5777C Microcontroller Data Sheet, Rev. 15, 03/20216NXP Semiconductors

Electrical characteristicsFigure 3. MPC5777C 516-ball MAPBGA (full diagram)3 Electrical characteristicsThe following information includes details about power considerations, DC/AC electricalcharacteristics, and AC timing specifications.3.1 Absolute maximum ratingsAbsolute maximum specifications are stress ratings only. Functional operation at thesemaxima is not guaranteed.CAUTIONStress beyond listed maxima may affect device reliability orcause permanent damage to the device.See Operating conditions for functional operation specifications.MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021NXP Semiconductors7

Electrical characteristicsTable 1. Absolute maximum erLifetime power cycles1.2 V core supplyvoltage2, 3, 4I/O supply voltage (medium I/OI/O supply voltage (fast 0.31.5V—–0.36.0V—–0.36.0VVDDPMCPower Management Controller supplyvoltage5—–0.36.0VVDDFLADecoupling pin for flash regulator6—–0.34.5VVSTBYRAM standby supply voltage5—–0.36.0VVSSA SDSDADC ground voltageReference to VSS–0.30.3VVSSA EQeQADC ground voltageReference to VSS–0.30.3VVDDA EQA/BeQADC supply voltageReference to VSSA EQ–0.36.0VVDDA SDSDADC supply voltageReference to VSSA SD–0.36.0VVRL SDSDADC ground referenceReference to VSS–0.30.3VVRL EQeQADC ground referenceReference to VSS–0.30.3VVRH EQeQADC alternate referenceReference to VRL EQ–0.36.0VVRH SDSDADC alternate referenceReference to VRL SD–0.36.0VVREFBYPCeQADC reference decoupling capacitorpinsREFBYPCA25, REFBYPCA75,REFBYPCB25, REFBYPC75–0.36.0VVDDA MISCTRNG and IRC supply voltage—–0.36.0VVDDPWRSMPS driver supply pin—–0.36.0VVSSPWRSMPS driver supply pinReference to VSS–0.30.3VVSS – VSSA EQVSSA EQ differential voltage—–0.30.3VVSS – VSSA SDVSSA SD differential voltage—–0.30.3VVSS – VRL EQVRL EQ differential voltage—–0.30.3VVSS – VRL SDVRL SD differential VINI/O input voltagerange7Relative to VDDEx/VDDEHxRelative to VSSIINJDMaximum DC injection current for digital Per pin, applies to all digital pinspad–55mAIINJAMaximum DC injection current foranalog padPer pin, applies to all analog pins–55mAMaximum current per I/O powersegment—–120120mAStorage temperature range and nonoperating times—–55175 CMaximum storage time, assembled part No supply; storage temperature inprogrammed in ECUrange –40 C to 60 C—20yearsMaximum solder temperature10—260 CIMAXSEG8, 9TSTGSTORAGETSDR—Pb-free packageTable continues on the next page.MPC5777C Microcontroller Data Sheet, Rev. 15, 03/20218NXP Semiconductors

Electrical characteristicsTable 1. Absolute maximum ratings (continued)SymbolMoisture sensitivity it—1. Voltages are referred to VSS if not specified otherwise2. Allowed 1.45 V – 1.5 V for 60 seconds cumulative time at maximum TJ 150 C; remaining time as defined in note -1 andnote -13. Allowed 1.375 V – 1.45 V for 10 hours cumulative time at maximum TJ 150 C; remaining time as defined in note -14. 1.32 V – 1.375 V range allowed periodically for supply with sinusoidal shape and average supply value below 1.275 V atmaximum TJ 150 C5. Allowed 5.5 V – 6.0 V for 60 seconds cumulative time with no restrictions, for 10 hours cumulative time device in reset, TJ 150 C; remaining time at or below 5.5 V6. Allowed 3.6 V – 4.5 V for 60 seconds cumulative time with no restrictions, for 10 hours cumulative time device in reset, TJ 150 C; remaining time at or below 3.6 V7. The maximum input voltage on an I/O pin tracks with the associated I/P supply maximum. For the injection currentcondition on a pin, the voltage will be equal to the supply plus the voltage drop across the internal ESD diode from I/O pinto supply. The diode voltage varies greatly across process and temperature, but a value of 0.3V can be used for nominalcalculations.8. The sum of all controller pins (including both digital and analog) must not exceed 200 mA. A VDDEx/VDDEHx power segmentis defined as one or more GPIO pins located between two VDDEx/VDDEHx supply pins.9. The average current values given in I/O pad current specifications should be used to calculate total I/O segment current.10. Solder profile per IPC/JEDEC J-STD-020D11. Moisture sensitivity per JEDEC test method A1123.2 Electromagnetic interference (EMI) characteristicsTest reports with EMC measurements to IC-level IEC standards are available on request.To find application notes that provide guidance on designing your system to minimizeinterference from radiated emissions, go to nxp.com and perform a keyword search for"radiated emissions."3.3 Electrostatic discharge (ESD) characteristicsTable 2. ESD Ratings1, 2SymbolParameterVHBMESD for Human Body Model (HBM)VCDMESD for Charged Device Model (CDM)ConditionsValueUnitAll pins2000VCorner pins750VNon-corner pins5001. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specificationrequirements.MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021NXP Semiconductors9

Electrical characteristics3.4 Operating conditionsThe following table describes the operating conditions for the device, and for which allspecifications in the data sheet are valid, except where explicitly noted.If the device operating conditions are exceeded, the functionality of the device is notguaranteed.Table 3. Device operating Max——264/3062MHz—132/153, 3MHzMHzFrequencyfSYSDevice operatingfPLATFfrequency1Platform operating frequency———eTPU operating frequency———200/2404fEBIEBI operating frequency———66MHzfPERPeripheral block dulated peripheral —block operating frequency——132/1503MHzfETPUfFM PERPlatform clock period———1/fPLATFnstCYC ETPUtCYCeTPU clock period———1/fETPUnstCYC PERPeripheral clock period———1/fPERnsTemperatureTJJunction operating temperaturerangePackaged devices–40.0—150.0 CTA (TL to TH)Ambient operating temperaturerangePackaged devices–40.0—125.05 C1.2—1.32V1.2—1.383.5—5.5V4.5—5.5V3.3 V range3.0—3.6I/O supply voltage (medium I/Opads)5 V range4.5—5.53.3 V range3.0—3.6VDDEH1eTPU A, eSCI A, eSCI B, andconfiguration I/O supply voltage(medium I/O pads)5 V range4.5—5.5VVDDPMC12Power Management Controller(PMC) supply voltageFull functionality3.15—5.5VVDDPWRSMPS driver supply voltageReference to VSSPWR3.0—5.5VVDDFLAFlash core ernal core supplyvoltage6, 7LVD/HVD enabledLVD/HVDVDDA MISCVDDExVDDEHx11VSTBYTRNG and IRC supply voltagedisabled8, 9, 10, 11—I/O supply voltage (fast I/O pads) 5 V rangeRAM standby supply voltageVTable continues on the next page.MPC5777C Microcontroller Data Sheet, Rev. 15, 03/202110NXP Semiconductors

Electrical characteristicsTable 3. Device operating conditions (continued)SymbolVSTBY Standby RAM brownout flag trippoint voltage—VRL SDSDADC ground referencevoltage—VDDA SDSDADC supply voltage15—4.5—5.5VeQADC supply voltage—4.75—5.25VSDADC referenceVDDA EQA/BVRH SDVVVSSA SD—4.5VDDA SD5.5VVDDA SD – VRH SD SDADC reference differentialvoltage———25mVVSSA SD – VRL SDVRL SD differential voltage—–25—25mVeQADC reference—4.75—5.25VeQADC reference differentialvoltage———25mVVSSA EQ – VRL EQVRL EQ differential voltage—–25—25mVVSSA EQ – VSSVSSA EQ differential voltage—–25—25mVVSSA SD – VSSVSSA SD differential voltage—–25—25mVSlew rate on power supply pins———100V/msDigital pins and analog pins–3.0—3.0mA—–80—80mAVRH EQVDDA EQA/B –VRH EQVRAMPCurrentIICIMAXSEGDC injection current (per17, 18pin)16,Maximum current per powersegment19, 201. Maximum operating frequency is applicable to the computational cores and platform for the device. See the Clockingchapter in the MPC5777C Microcontroller Reference Manual for more information on the clock limitations for the various IPblocks on the device.2. If frequency modulation (FM) is enabled for the maximum operating frequency of 264 MHz or 306 MHz, the maximumfrequency still cannot exceed this value when frequency modulation is enabled (frequency modulation must spread downfrom the maximum).3. 132 MHz applies to the MPC5777C part number with 264 MHz operating frequency. 153 MHz applies to the version with306 MHz operating frequency.4. 200 MHz applies to the MPC5777C part number with 264 MHz max operating frequency. 240 MHz applies to the versionwith 306 MHz operating frequency.5. The maximum specification for operating junction temperature TJ must be respected. Thermal characteristics providesdetails.6. Core voltage as measured on device pin to guarantee published silicon performance7. During power ramp, voltage measured on silicon might be lower. Maximum performance is not guaranteed, but correctsilicon operation is guaranteed. See power management and reset management for description.8. Maximum core voltage is not permitted for entire product life. See absolute maximum rating.9. When internal LVD/HVDs are disabled, external monitoring is required to guarantee device operation. Failure to monitorexternally supply voltage may result in erroneous operation of the device.10. This LVD/HVD disabled supply voltage condition only applies after LVD/HVD are disabled by the application during thereset sequence, and the LVD/HVD are active until that point.11. This spec does not apply to VDDEH1.12. When internal flash memory regulator is used: Flash memory read operation is supported for a minimum VDDPMC value of 3.15 V. Flash memory read, program, and erase operations are supported for a minimum VDDPMC value of 3.5 V.MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021NXP Semiconductors11

Electrical characteristics13.14.15.16.17.18.19.20.When flash memory power is supplied externally (VDDPMC shorted to VDDFLA): The VDDPMC range must be within the limitsspecified for LVD FLASH and HVD FLASH monitoring. Table 1 provides the monitored LVD FLASH and HVD FLASHlimits.If the standby RAM regulator is not used, the VSTBY supply input pin must be tied to ground.VSTBY BO is the maximum voltage that sets the standby RAM brownout flag in the device logic. The minimum voltage forRAM data retention is guaranteed always to be less than the VSTBY BO maximum value.For supply voltages between 3.0 V and 4.0 V there will be no guaranteed precision of ADC (accuracy/linearity). ADC willrecover to a fully functional state when the voltage rises above 4.0 V.Full device lifetime without performance degradationI/O and analog input specifications are only valid if the injection current on adjacent pins is within these limits. See theabsolute maximum ratings table for maximum input current for reliability requirements.The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pin isabove the supply rail, current will be injected through the clamp diode to the supply rail. For external RC networkcalculation, assume a typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature.The sum of all controller pins (including both digital and analog) must not exceed 200 mA. A VDDEx/VDDEHx power segmentis defined as one or more GPIO pins located between two VDDEx/VDDEHx supply pins.The average current values given in I/O pad current specifications should be used to calculate total I/O segment current.3.5 DC electrical specificationsNOTEIDDA MISC is the sum of current consumption of IRC, ITRNG,and ISTBY in the 5 V domain. IRC current is provided in theIRC specifications.NOTEI/O, XOSC, EQADC, SDADC, and Temperature Sensor currentspecifications are in those components' dedicated sections.Table 4. DC electrical g current on the VDD core logicsupply1ValueMinTypMaxLVD/HVD enabled, VDD 1.2 Vto 1.32 V—0.651.35LVD/HVD disabled, VDD 1.2 Vto 1.38 V—0.651.4UnitAIDD PEOperating current on the VDD supply for flashmemory program/erase———85mAIDDPMCOperating current on the VDDPMC supply2Flash memory read——40mAFlash memory program/erase——70PMC only——35Flash memory read——10Flash memory program/erase——40PMC only——5Core regulator DC current output on VREGCTLpin———25mAStandby RAM supply current1.08 V, TJ 150 C——1140μAOperating current on the VDDPMC supply(internal core regulator bypassed)IREGCTLISTBYmATable continues on the next page.MPC5777C Microcontroller Data Sheet, Rev. 15, 03/202112NXP Semiconductors

Electrical characteristicsTable 4. DC electrical specifications (continued)SymbolIDD PWRIBG REFITRNGParameterOperating current on the VDDPWR supplyBandgap reference currentConditionsMinTypMax1.25 V to 5.5 V, TJ 150 C11701.25 V to 5.5 V, TJ 85 C360Unit1.25 V to 5.5 V, TJ 40 umption3True Random Number Generator currentValue—1. IDD measured on an application-specific pattern with all cores enabled at full frequency, TJ 40 C to 150 C. Flash memoryprogram/erase current on the VDD supply not included.2. This value is considering the use of the internal core regulator with the simulation of an external transistor with theminimum value of hFE of 60.3. This bandgap reference is for EQADC calibration and Temperature Sensors.3.6 I/O pad specificationsThe following table describes the different pad types on the chip.Table 5. I/O pad specification descriptionsPad typeDescriptionGeneral-purpose I/OpadsGeneral-purpose I/O and EBI data bus pads with four selectable output slew rate settings; alsocalled SR padsEBI padsProvide necessary speed for fast external memory interfaces on the EBI CLKOUT, address, andcontrol signals; also called FC padsLVDS padsLow Voltage Differential Signal interface padsInput-only padsLow-input-leakage pads that are associated with the ADC channelsNOTEEach I/O pin on the device supports specific driveconfigurations. See the signal description table in the devicereference manual for the available drive configurations for eachI/O pin.NOTEThroughout the I/O pad specifications, the symbol VDDExrepresents all VDDEx and VDDEHx segments.3.6.1 Input pad specificationsTable 6 provides input DC electrical characteristics as described in Figure 4.MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021NXP Semiconductors13

Electrical characteristicsV INV DDV IHV HYSV ILV INTERNAL(SIU register)Figure 4. I/O input DC electrical characteristics definitionTable 6. I/O input DC electrical characteristicsSymbolVIHCMOS HVIHCMOSVILCMOS HVILCMOSVHYSCMOSParameterConditionsInput high level CMOS (withhysteresis)3.0 V VDDEx 3.6 V andInput high level CMOS (withouthysteresis)3.0 V VDDEx 3.6 V andInput low level CMOS (withhysteresis)3.0 V VDDEx 3.6 V andInput low level CMOS (withouthysteresis)3.0 V VDDEx 3.6 V andInput hysteresis CMOS3.0 V VDDEx 3.6 V andValueUnitMinTypMax0.65 * VDDEx—VDDEx 0.3V0.55 * VDDEx—VDDEx 0.3V–0.3—0.35 * VDDExV–0.3—0.4 * VDDExV0.1 * VDDEx——V4.5 V VDDEx 5.5 V4.5 V VDDEx 5.5 V4.5 V VDDEx 5.5 V4.5 V VDDEx 5.5 V4.5 V VDDEx 5.5 VInput Characteristics1ILKGILKG FASTILKGACINDigital input leakageVSS VIN VDDEx/VDDEHx——2.5μADigital input leakage for EBIaddress/control signal padsVSS VIN VDDEx/VDDEHx——2.5μAAnalog pin input leakage (5 Vrange)VSSA SD VIN VDDA SD,VSSA EQ VIN VDDA EQA/B——220nADigital input capacitanceGPIO and EBI input pins——7pF1. For LFAST, microsecond bus, and LVDS input characteristics, see dedicated communication module sections.Table 7 provides current specifications for weak pullup and pulldown.MPC5777C Microcontroller Data Sheet, Rev. 15, 03/202114NXP Semiconductors

Electrical characteristicsTable 7. I/O pullup/pulldown DC electrical characteristicsSymbolIWPUParameterConditionsWeak pullup currentVIN 0.35 * nitμA4.5 V VDDEx 5.5 VVIN 0.35 * VDDEx3.0 V VDDEx 3.6 VIWPDWeak pulldown currentVIN 0.65 * VDDExμA4.5 V VDDEx 5.5 VVIN 0.65 * VDDEx3.0 V VDDEx 3.6 VThe specifications in Table 8 apply to the pins ANA0 SDA0 to ANA7, ANA16 SDB0 toANA23 SDC3, and ANB0 SDD0 to ANB7 SDD7.Table 8. I/O pullup/pulldown resistance electrical g input bias / diagnostic pullup/pulldown resistanceΔPUPDValueMinTypMax200 kΩ130200280100 kΩ651001405 kΩ1.457.5——5RPUPD pullup/pulldown resistance mismatch —UnitkΩ%3.6.2 Output pad specificationsFigure 5 shows output DC electrical characteristics.MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021NXP Semiconductors15

Electrical characteristicscore side inputVDD/2tPD(low to high)tPD(high to low)VDDExVohPADVolVSSExRiseTimeFallTimeFigure 5. I/O output DC electrical characteristics definitionThe following tables specify output DC electrical characteristics.Table 9. GPIO and EBI data pad output buffer electrical characteristics (SR pads)1SymbolIOHIOLParameterConditions2GPIO pad output highcurrentVOH 0.8 * VDDExGPIO pad output lowcurrentValue3MinTypMaxPCR[SRC] 11b or 01b25——4.5 V VDDEx 5.5 V PCR[SRC] 10b or 00b15——VOH 0.8 * VDDExPCR[SRC] 11b or 01b13——3.0 V VDDEx 3.6 V PCR[SRC] 10b or 00b8——VOL 0.2 * VDDExPCR[SRC] 11b or 01b48——4.5 V VDDEx 5.5 V PCR[SRC] 10b or 00b22——VOL 0.2 * VDDEx17——10.5——CL 25 pF——1.24.5 V VDDEx 5.5 V CL 50 pF——2.5CL 200 pF——8CL 25 pF——1.73.0 V VDDEx 3.6 V CL 50 pF——3.25CL 200 pF——12CL 50 pF——54.5 V VDDEx 5.5 V CL 200 pF——18PCR[SRC] 10b——73.0 V VDDEx 3.6 V CL 200 pF——25PCR[SRC] 01b——134.5 V VDDEx 5.5 V CL 200 pF——24PCR[SRC] 01b——25PCR[SRC] 11b or 01b3.0 V VDDEx 3.6 V PCR[SRC] 10b or 00btR FGPIO pad outputtransition time (rise/fall)PCR[SRC] 11bPCR[SRC] 11bPCR[SRC] 10bCL 50 pFCL 50 pFCL 50 pFUnitmAmAnsTable continues on the next page.MPC5777C Microcontroller Data Sheet, Rev. 15, 03/202116NXP Semiconductors

Electrical characteristicsTable 9. GPIO and EBI data pad output buffer electrical characteristics (SR erGPIO pad outputpropagation delay time tSKEW W Difference between riseand fall timeMinTypMax3.0 V VDDEx 3.6 V CL 200 pF——30PCR[SRC] 00b——244.5 V VDDEx 5.5 V CL 200 pF——50PCR[SRC] 00b——403.0 V VDDEx 3.6 V CL 200 pF——51PCR[SRC] 11b——64.5 V VDDEx 5.5 V CL 200 pF——13PCR[SRC] 11b——8.253.0 V VDDEx 3.6 V CL 200 pF——19.5PCR[SRC] 10b——94.5 V VDDEx 5.5 V CL 200 pF——22PCR[SRC] 10b——12.53.0 V VDDEx 3.6 V CL 200 pF——35PCR[SRC] 01b——274.5 V VDDEx 5.5 V CL 200 pF——40PCR[SRC] 01b——453.0 V VDDEx 3.6 V CL 200 pF——65PCR[SRC] 00b——404.5 V VDDEx 5.5 V CL 200 pF——65PCR[SRC] 00b——753.0 V VDDEx 3.6 V CL 200 pF——100———25CL 50 pFCL 50 pFCL 50 pFCL 50 pFCL 50 pFCL 50 pFCL 50 pFCL 50 pFCL 50 pFCL 50 pFUnitns%1. All GPIO pad output specifications are valid for 3.0 V VDDEx 5.5 V, except where explicitly stated.2. PCR[SRC] values refer to the setting of that register field in the SIU.3. All values to be confirmed during device validation.The following table shows the EBI CLKOUT, address, and control signal pad electricalcharacteristics. These pads can also be used for GPIO.Table 10. GPIO and EBI CLKOUT, address, and control signal pad output buffer electricalcharacteristics (FC BI Mode Output Specifications: valid for 3.0 V VDDEx 3.6 VCDRVExternal bus loadcapacitancePCR[DSC] 01b——10PCR[DSC] 10b——20pFTable continues on the next page.MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021NXP Semiconductors17

Electrical characteristicsTable 10. GPIO and EBI CLKOUT, address, and control signal pad output buffer electricalcharacteristics (FC pads) ypMaxPCR[DSC] 11b——30CDRV 10/20/30 pF——66MHzmAfMAX EBIExternal bus maximumoperating frequencyIOH EBIGPIO and external bus VOH 0.8 * VDDExPCR[DS

Data Sheet Features This document provides electrical specifications, pin assignments, and package diagram information for the MPC5777C series of microcontroller units (MCUs). For functional characteristics and the programming model, see the MPC5777C Refe