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IEEE Components, Packaging and ManufacturingTechnology Chapter, SCVFebruary 13, 2013Advanced Organic Substrate Technologies to Enable ExtremeElectronics MiniaturizationIEEE CPMT Santa ClaraFebruary 13, 2012Page 1Advanced Organic Substrate Technologies toEnable Extreme Electronics MiniaturizationSusan Bagen, Dave Alcoe, Frank D. Egitto,Rabindra N. Das & Glen ThomasEndicott Interconnect Technologies, Inc.1903 Clark Street, Endicott, New York, 13760Susan.Bagen@eitny.comFebruary 13, 2013Page 2www.cpmt.org/scv/1

IEEE Components, Packaging and ManufacturingTechnology Chapter, SCVFebruary 13, 2013Agenda IntroductionThin Core Substrates vs. PWBsChip-Package InteractionOrganic vs. CeramicSystem-in-Package Building BlocksSystem-in-Package Case StudiesZ-Interconnect3D SolutionsExtreme Miniaturization with MicroflexNew Substrate Technologies: LCP & StretchablePage 3Benefits of Electronics MiniaturizationMarkets: Aerospace, Defense, Industrial & MedicalMACRO ELECTRONIC ASSEMBLIESIncreased Function & Integration(Servers, Medical Systems)MICRO ELECTRONIC ASSEMBLIESIncreased Function / Reduced SWaP(Implantables, biosensors,guidance sensors, UAVs, advancedreceptors)Page 4www.cpmt.org/scv/2

IEEE Components, Packaging and ManufacturingTechnology Chapter, SCVFebruary 13, 2013Rigid SubstratesThin Core Substrates vs. PWBsPage 5Rigid Substrates Electronics miniaturization drives the use of finepitch BGAs, CSPs and tiny SMT components, as wellas bare die.Substrate attributes have significant impact on the ability toreliably assemble these types of components and bare die. Dielectric material & filler: glass cloth vs. particle Substrate thickness Blind & buried vias Line width & space capabilityPage 6www.cpmt.org/scv/3

IEEE Components, Packaging and ManufacturingTechnology Chapter, SCVFebruary 13, 2013Thin Core Substrates vs. PWBsCross-section ComparisonCoreEZ 2-4-23 fully wireablebuild up layersStandard Build-up PWB 3-2-32 fully wireablebuild up layers2 fully wireablebuild up layersEpoxy-based with silicaparticle fill(Photos are to scale)3 build up layers onlyuseful for redistributionEpoxy-based with glass cloth- Thin core vias are 4x smaller- Thin core requires fewer costly build up layers for the same wiring capacity- Thinner core reduces electrical parasiticsPage 7Substrate expansion, combined with PTH restraint, creates Z-axisexpansion stress on BU & soldermask and potential halo delamination.Std BUZ-expansionStress on viaCoreEZThin core has much less deformation for BU & soldermask layers toabsorb, therefore, less stress and virtually no halo delamination.Page 8www.cpmt.org/scv/4

IEEE Components, Packaging and ManufacturingTechnology Chapter, SCVFebruary 13, 2013Limiting Attributes of PWBs for Bare Die Assembly Thick Core: Z-axis Expansion– Limits bare die assembly primarily to wirebond or onlysmall, low I/O flipchip die Glass Cloth Filler– Risk of CAF (conductive anodic filament) defects– Mechanical or CO2 drill– Surface topography can impact ability to achieveconductor fine lines and spacesPage 9Thin Core Substrates vs. PWBsVia Density Comparison Very Dense Package Interconnect– Ultra Dense Core Via Pitch caneliminate additional build up layers– When CVP is nearly die bump pitch,enables Z-escape to all wiring planes Dual Side Component Mounting Fine Line Width and Spacing– 18 – 25 µmUV Laser Drilled CoreEZ Thin Core:100 um diameter pad (50 um via)Standard Build-Up Mechanically drilled core:400 micron diameter pad, 200 um diameter viaHDI Substrate has 9X Core Via Density over conventional build up PWBPage 10www.cpmt.org/scv/5

IEEE Components, Packaging and ManufacturingTechnology Chapter, SCVFebruary 13, 2013Packaging Attributes ComparisonSubstrate features and advanced IC Assembly techniques enable bare die implementationAttributeStandard PWBCoreEZ SubstrateShrinkt itopportunityThrough viaMechanicalLaserThrough via dia.200 microns50 microns4XThrough via capture pad diameter400 microns100 microns4X3XLine Width75 microns18-25 micronsSpace Width75 microns18-25 microns3XSemiconductorsPackagedWirebondBare die or smallpackagepg4X to 10XEI’s 3-4-3 CoreEZ Flip Chip BumpPage 11Typical CoreEZ 10 Layer Cross-SectionCu-filled stacked microviasFlip Chip BumpsSoldermaskPSR400015 µm thickGND / TOPBuild-up layer 1Build-up layer 2Build-up layer 3Driclad, 35/50 µmthickS1PWR / GNDOuter coreDielectric, Driclad35/50 µm thickS2PWR / GNDInner core135 µm thickEpoxy/P-AramidPWR / GNDCore Cu12 µm thickS3PWR / GNDBuild-up Cu 1Build-up Cu 2Build-up Cu 312 µm thickS4GND / BOT 3-4-3 Stack up (10 copper layers)Substrate thickness 0.7 mmPage 12www.cpmt.org/scv/6

IEEE Components, Packaging and ManufacturingTechnology Chapter, SCVFebruary 13, 2013Typical HyperBGA 9 Layer Cross Section40 micron thick KPPEouter dielectricEr 3.23235 micron thick PTFEDielectric, Er 2.7ChippBumpNon soldermaskdefined padUnderfill15 thick Cu,redistributionmicrovia12 thick Cu50 micron thick PTFEDielectric, Er 2.715 thick Cu,redistribution6 Cu/38 Invar/6 CuGround plane12 thick Cu,50m dia. through viaKPPE filledBGA PadShown: 7 layer core with 1 build-up. Alternatives: Core (3-7 layer), BU to 3x layers.Can also use a traditional soldermask for SMD defined pads, if desired.Page 13Chip-Package InteractionPage 14www.cpmt.org/scv/7

IEEE Components, Packaging and ManufacturingTechnology Chapter, SCVFebruary 13, 2013Flip-Chip vs. WirebondWirebond:Active face is away from the substrate and associated die adhesiveDie adhesive material stress cracking avoids wirebond connections - at firstBegs questions: How far will crack run? Why did it happen? Thermal performance?Fracture / debond may notdamage the wirebondFlip-Chip:Die is 'flipped' so that electrical connections to substrate have very short lengthThe connections and active die face are in proximity to the substrate and underfillUnderfill is used to avoid stress to the electrical connectionsFailure of the underfill can quickly lead to electrical opensFracture / debond likely todamage the bumpThermal expansion of the Die vs Substrate is one fundamental driver of reliabilityPage 15Illustration of effect of CTE mismatch in view of temp changeAssume two very stiff layers of material, viewed in sectionLinear Expansion Only, with CTE α CTE βEquilibrium TemperatureαβCooledHeatedααββWith temperature change, dissimilar materials expand differently: “Mismatch”This expansion mismatch creates strain and stressThe strain and stress exists in either the materials, the bonding , or bothPage 16www.cpmt.org/scv/8

IEEE Components, Packaging and ManufacturingTechnology Chapter, SCVFebruary 13, 2013Illustration of effect of CTE mismatch in view of temp changeAssume two coupled flexible layers of material, viewed in sectionLinear Expansion, with CTE α CTE β creates bending stressPage 17Ball Grid Array Module attached to a PWBCTE mismatch effect, in view of temp reduction from solder reflowFlip-chip solder array attached to a substrate is analogousPage 18www.cpmt.org/scv/9

IEEE Components, Packaging and ManufacturingTechnology Chapter, SCVFebruary 13, 2013General OverviewPage 19Numerical Analysis for Die warp and Die stress Closed-form solution for unsymmetrical bending of linear elastic composite plate– 3-layer solution for die, underfill, substrateDie: 18mm square, E 21.8Mpsi, CTE 3ppm/C (constant throughout)Underfill: Typical high Tg, 100 micron thick (constant throughout)propertiespof interestSubstrate: Various p Stress: Uniform temp change from underfill cure to room temp Parametric analysis executed for two key variable clusters–Nominal die thickness 750 micronsNominal substrate modulus 3MpsiNominal substrate : modulus 3Mpsi, thickness 1000 microns, CTE 20 ppm/CN i l substrate:b t t modulusd l 3 Mpsi,M i thicknessthi k500 microns,iCTE 20 ppm/C/CNominalNominal substrate : modulus 3 Mpsi, thickness 500 microns, CTE 10 ppm/CResponse Measures:–– SubstrateDie thickness (10 microns to 10mm), several substrates of interest UnderfillSubstrate thickness range 10 microns to 10mm, with CTE range 5-30 ppm/C –DieMaximum die warpage (center to corner)Maximum principal stress on upper surface of die (away from substrate)MANY analysis were performed to create the following charts!Page 20www.cpmt.org/scv/10

IEEE Components, Packaging and ManufacturingTechnology Chapter, SCVFebruary 13, 2013Substrate Thickness & CTE EffectsComparison for common die size CTE difference fromsilicon is key driver Substrate thicknessgcreates a significantmaximum response valuefor both die stress anddie warpage For substrates above themaximal response value,thinning the substrate isworse For substrates below themaximal response value,thinningg the substrate isbetter Nominal substratemodulus 3 Mpsi To compare actualdesigns, their stiffnesswill vary, along withthickness & CTE30Die STRESS5 ppm/C30252015Die WARPHyperBGA105 ppm/CWafer-level pkgPWB rangeTypical flip-chip pkg rangePage 21Die Thickness EffectComparison for three nominal substrates Strong effect of siliconthickness on warpage Silicon must becomeextremely thin tounderpass maximum,maximum sothat most substrateapplication will warpMORE with thinner die Substrate propertieshave significant effect ondie warpage Starting from typical diethickness, stressgenerally drops as die isthinned, but eventuallyh pointi t wherehitreachesbecomes compressed20 ppm/C, 1000micron20 ppm/C, 500micronDie STRESS10 ppm/C, 500micron20 ppm/C, 500micron20 ppm/C, 1000micronDie WARP Thinned stacked die haspotential to create layerlayer debonding stress,depending on substratechoice (similar to ULKILD issues)10 ppm/C, 500micronStacked (unthinned)Typical thinnedTypicalASICPage 22www.cpmt.org/scv/11

IEEE Components, Packaging and ManufacturingTechnology Chapter, SCVFebruary 13, 2013Organic vs. Ceramic SubstratesPage 23Generalized Ceramic vs Organic Substrate Designand Performance DifferencesCeramic Stiffer Material can fracture High temperature resistance Minimal warpage Material shrinks substantially in fabCan be hard to control dimensions Higher dielectric constant material Thicker Substrate HeavierHeavier substrateCan affect assembly temperatures Expansion coefficient 5-10 ppm/CPkg size drives significant BGA stressColumns can be used to reduce Substrate is hermeticPackage could be hermetic with lid sealOrganic Compliant materials: More stretching Material can fatigue Material has temperature dependency Warpage controlsDesign balance, fixtures, lids Good dimensional control Better electrical performance Thin, light substrateDi sizei affectsff t BGA stresst DieGood for SOP applications Lower BGA stress No need for solder columns Non-hermeticMoisture effects on adhesionPage 24www.cpmt.org/scv/12

IEEE Components, Packaging and ManufacturingTechnology Chapter, SCVFebruary 13, 2013Weight Comparisons40 mm body size substrateApproximate substrateweight (gm)Ceramic (30 layer, alumina, 10mil/layer)48Ceramic (15 layer, alumina, 10 mil/layer)24PTFE BGA 9 layer substrate2.3Thi core buildb ild up 10 llayer substrateb t tThin292.9Thin core build up 6 layer substrate2.0Page 25HyperBGA Compliant Laminate Overview Deformation analogy–Consider solder column array deformations between ceramic & card–HyperBGA laminate internalizes deformations: Low stress Connections–SolderS ld connectionstiare low-profilelfil jointsj i t andd nott prone tot shearhdamagedCeramic Solder ColumnHyperBGAFree CTE valuesLid: 17Chip: 3Laminate: 11high standoffPC card: 18 Rigid, Brittle, Shrink-Fired Dielectric Elongated Solder Connections Shear Deformable Laminate Expansion Compensated Laminate Thin, Compliant Laminate Materials HyperBGA is designed for an optimal distribution of low stresses on BGA, internalcircuitry, underfill, chip, adhesives Very thin laminate contributes to reliable high density connectionsPage 26www.cpmt.org/scv/13