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Introduction to Quartus II Software

Introduction to Quartus II SoftwareThe Altera Quartus II design software is a multiplatform design environment that easily adapts to your specificneeds in all phases of FPGA and CPLD design. Quartus II software delivers the highest productivity andperformance for Altera FPGAs, CPLDs, and HardCopy ASICs.Quartus II software delivers superior synthesis and placement and routing, resulting in compilation timeadvantages. Compilation time reduction features include: Multiprocessor support Rapid Recompile Incremental compilationIncremental Compilation and Rapid RecompileQuartus II Analysis and Synthesis, together with the Quartus II Fitter, incrementally compiles only the parts of yourdesign that change between compilations. By compiling only changed partitions, incremental compilation reducescompilation time by up to 70 percent.For small engineering change orders (ECOs), the Rapid Recompile feature maximizes your productivity by reducingyour compilation time by 65 percent on average, and improves design timing preservation.Compilation Time ComparisonQuartus II Relative Compilation Time by Release(Relative Time Based on Fixed Designs and Fixed CPU)Simulation100%You can perform thefunctional and timingsimulation of your designwith the ModelSim -AlteraEdition software, or anyEDA simulators supportedby Quartus II software. TheQuartus II NativeLinkfeature allows you to runyour third-party simulatorand other EDA tools fromwithin Quartus II software.Relative Compile Time (Log s II Software VersionThe Qsys system integration tool saves significant time and effort in theFPGA design process by automatically generating interconnect logic toconnect IP functions and subsystems. Qsys is the next-generation SOPCBuilder tool powered by a new FPGA-optimized Network-on-a-Chip(NoC) technology delivering high-performance, scalable systems, andimproved design reuse opportunities.2    Quartus II Design Software 2011 4.05.06.0www.altera.com7.08.09.010.011.0.For v11.0, use v10.1 data point.

Design EntryYour design can begin as HDL or a schematic. The MegaWizard Plug-In Manager helps you create or modify designfiles that contain custom megafunction variations, which you can then instantiate in a design file.Timing and Power AnalysisThe Quartus II TimeQuest timing analyzerallows you to analyze the timing characteristicsof your design. Altera is the only FPGA vendorwith comprehensive Synopsys Design Constraints (SDC) support in its second-generation,easy-to-use timing analyzer. The TimeQuestanalyzer offers a complete GUI and scriptingenvironment to create timing constraints andreports. It also includes a timing analysis wizardthat makes it easy to create initial constraints.PowerPlay Power Analyzer lacement andRoutingOptimize PowerTimeQuest Timing AnalyzerThe Quartus II PowerPlay power analysis and optimization toolsallow you to estimate power consumption throughout the designcycle. They use power optimization technology, which provides onaverage a 10-percent reduction in power consumption. The AlteraPowerPlay Early Power Estimator estimates power consumptionand produces a Microsoft Excel-based spreadsheet with estimateinformation. The PowerPlay power analyzer performs post-fittingpower analysis and reports power characteristics by device resourceand design entity.PowerPlayPower AnalyzerPower-Optimized DesignVerificationQuartus II software offers several tools to help you analyze the results of compilation and fitting. Verification with theSignalTap II logic analyzer and the System Console allows you to probe your design as it functions on the deviceand in the system.Links to Online ResourcesVideo: Basic Compilation FlowDocumentation: Design Planning with the Quartus II SoftwareQuartus II Design Software 2011 www.altera.com    3

Design EntryQsysThe Qsys system integration tool saves significant time and effort in the FPGA design process by automatically generating interconnect logic to connect custom HDL design blocks, commonly referred to as design modules; intellectualproperty (IP) cores; and components. Qsys is powered by a new FPGA-optimized NoC–based technology deliveringhigher performance. Qsys also raises the level of abstraction and increases productivity by enabling design reuse andscalable systems.Qsys Interconnect Fabric ExampleControl A32 BitMemory AControl B32 rWidth MatchWidth MatchWidth MatchWidth MatchWidth MatchProcessing 18 BitProcessing 28 BitProcessing 316 BitProcessing 464 BitProcessing 564 Bit.Processing XAddressArbiterDataMemory BClock 1Memory CClock 2Qsys Auto-Generated InterconnectQuartus II Block EditorThe Quartus II Block Editor allows you to enter and edit graphic design information in the form of schematics and blockdiagrams. The Block Editor reads and edits Block Design Files (.bdf) that contain blocks and symbols representing logic.MegaWizard Plug-In ManagerThe MegaWizard Plug-In Manager helps you create or modify design files that contain custom megafunction variations,which you can then instantiate in a design file. The MegaWizard Plug-In Manager allows you to set values for parameters and optional ports.4    Quartus II Design Software 2011 www.altera.com

Design PartitionsYou can assign design entities to design partitions—logical design blocks that are preserved or recompiled duringincremental compilation. Incremental compilation saves you time and effort by recompiling only those design partitionsyou are optimizing. Quartus II software preserves previous compilation results for partitions that already meet yourdesign requirements. The Design Partition Planner allows you to view a graphical representation of your designhierarchy and assists you in creating effective design partitions.Links to Online ResourcesVideo: Design EntryWebcast: Why You Should Evaluate Qsys System Integration ToolQuartus II Online Help: About Design EntryWeb: Design Entry and Planning Resource CenterDocumentation: Creating a System with QsysIncremental Design Planning and MethodologyQuartus II software is tailored to several different design methodologies, including incremental compilation designflows and block-based design flows. In a team-based incremental compilation flow, the design is divided into partitions.Each team member can functionally verify a partition independently, and then simply provide the source code for thepartition to a project lead for integration. Using placeholders, the project lead can compile the larger design even if thesource code is not yet complete for a partition.Compiling all design partitions in a single Quartus II project ensures that the design is compiled with a consistent set ofassignments.Incremental design encompasses the following: Synthesis Design partitioning Full compilation Simulation, verification, and analysis, followed by changes to the design Recompilation of only changed elements of the design hierarchyLinks to Online ResourcesVideo: Incremental CompilationVideo: Rapid RecompileWeb: Incremental Compilation Resource CenterOnline Help: About Incremental CompilationDocumentation: Best Practices for Incremental Compilation Partitions andFloorplan AssignmentsDocumentation: Quartus II Handbook: Incremental Compilation forHierarchical and Team-Based DesignQuartus II Design Software 2011 www.altera.com    5

Quartus Integrated Synthesis and the FitterQuartus II software includes a comprehensive integrated synthesis solution and advanced integration with leadingthird-party synthesis software vendors. Quartus II integrated synthesis fully supports the Verilog HDL and VHDLlanguages, and includes algorithms to minimize gate count, remove redundant logic, and use device architectureefficiently. Quartus II integrated synthesis includes advanced synthesis options and compiler directives to guide thesynthesis process to achieve optimal results.The Quartus II Fitter places and routes your design for the target device. Using the database created by Quartus IIintegrated synthesis, the Fitter matches the logic and timing requirements of the project with the available resources ofthe target device. It assigns each logic function to the best logic cell location for routing and timing, and selects appropriate interconnection paths and pin assignments.Netlist Viewers and the Chip PlannerThe Quartus II RTL Viewer, State Machine Viewer, and Technology Map Viewer provide powerful ways to view yourinitial and fully mapped synthesis results during the debugging, optimization, and constraint entry processes. The ChipPlanner supports ECOs by allowing quick and efficient changes to your logic late in the design cycle. It provides a visualdisplay of your post placement-and-routing design mapped to device architecture, and allows you to create, move, anddelete specific routing and resource usage.Links to Online ResourcesCompare Full and Incremental CompilationWeb: Synthesis and NetlistViewers Resource CenterIncremental CompilationTop-Down ApproachFull CompilationCreate Design Partitions (A, B, C)Online Help: About the NetlistViewersOnline Help: About the ChipPlannerStep 1Quartus II Project(No Partitions)Quartus II ProjectStep 1Modify Design (In Red)Re-Compile Whole ProjectStep 26    Quartus II Design Software 2011 www.altera.comQuartus II Project(No Partitions)AABBCCModify Design in Partition ARe-Compile Only Partition AQuartus II ProjectStep 2AABBCC

Making AssignmentsAssignments allow you to specify various options and settings for the logic in your design. When you make resourceassignments in your design, Quartus II software attempts to match those resource assignments with the resources on thedevice, meet any other constraints you have set, and then optimize the remaining logic in the design. The AssignmentEditor and Pin Planner are interfaces for creating and editing pin, node, and entity-level assignments in Quartus IIsoftware. The Pin Planner allows you to make assignments to individual pins and also groups of pins. It includes apackage view of the device with different colors and symbols that represent the different types of pins and additionalsymbols that represent I/O banks. The symbols used in the Pin Planner are very similar to the symbols used in devicefamily data sheets.Links to Online ResourcesOnline Help: About AssignmentsOnline Help: About the PinPlannerDocumentation: ConstrainingDesignsDocumentation: I/O ManagementAssignment Entry FlowQuartus IISettings Dialog BoxQuartus IIDesign FilesQuartus IIAssignment EditorQuartus IIProject File (.qpf)Quartus IIPin PlannerQuartus IIDesign PartitionsWindowQuartus IIChip PlannerTimeQuestTiming AnalyzerTo Quartus IIAnalysis &SynthesisQuartus IISettings File (.qsf)Verilog QuartusMapping Files (.vqm)From Block-Based DesignSynopsys DesignConstraints File (.sdc)SimulationYou can perform functional andtiming simulation of your design withthe ModelSim-Altera Edition softwareor any EDA simulators supported byQuartus II software. Quartus IIsoftware provides the followingfeatures for performing simulation: NativeLink integration withsimulation toolsAltera provides functional simulation libraries for designs that containAltera-specific components, and atom-based timing simulation libraries fordesigns compiled in Quartus II software.Quartus II software also allows you to use the EDA tools you are familiar withfor other stages of the design flow, including synthesis, timing analysis, andformal verification.Links to Online Resources Generation of output netlist filesVideo: ModelSim Simulation Functional and timing simulationlibrariesWeb: EDA Partners Generation of testbench templatesand memory initialization Generation of input for power analysisOnline Help: About Using the ModelSim Software with the Quartus IISoftwareDocumentation: Simulating Altera DesignsQuartus II Design Software 2011 www.altera.com    7