Transcription
COMPACT MODELING OF DEEP SUBMICRON CMOS TRANSISTORWITH SHALLOW TRENCH ISOLATION MECHANICAL STRESS EFFECTPHILIP TAN BEOW YEWUNIVERSITI SAINS MALAYSIA2008
COMPACT MODELING OF DEEP SUBMICRON CMOS TRANSISTOR WITHSHALLOW TRENCH ISOLATION MECHANICAL STRESS EFFECTbyPHILIP TAN BEOW YEWThesis submitted in fulfilment of therequirements for the degreeof Doctor of PhilosophyAugust 2008
ACKNOWLEDGEMENTSI would like to express my gratitude to my Ph.D. project supervisor, Dr. Othman Sidekfor his guidance and encouragement throughout the duration of this project. Hissupport in determining the project that benefit to both my work and study is highlyappreciated.Special thanks go to my Silterra supervisor, Al Kordesch for his unconditionalguidance and constructive suggestions, which enable me to overcome the obstacles inmy Ph.D. project. I am also grateful to Silterra management team for theencouragement for further study and technical publications. Not forgetting to all mysupportive colleagues in Technology Development and Device Modeling team, thanksfor everything.Finally, I would like to express my sincere thanks and utmost appreciation to mybeloved family, especially to my wife, Christine. For their undying love, support andpatient that enable me to complete my Ph.D. degree successfully.ii
TABLE OF CONTENTSPageACKNOWLEDGEMENTSiiTABLE OF CONTENTSiiiLIST OF TABLESviiLIST OF FIGURESviiiLIST OF SYMBOLxivLIST OF ABBREVIATIONxxABSTRAKxxiiABSTRACTxxivCHAPTER 1 : INTRODUCTION1.0Chapter Overview11.1Introduction to Compact Modeling11.2History of Compact Modeling21.3Compact Modeling of CMOS Transistor Deep Submicron4Effects1.3.1Body effect and Bulk Charge Effect61.3.2Short Channel Effect (SCE)81.3.3Reverse Short Channel Effect (RSCE)91.3.4Narrow Width Effect (NWE)111.3.5Inverse Narrow Width Effect (INWE)121.3.6Small Size Effect on Threshold Voltage131.3.7Drain Induced Barrier Lowering (DIBL)131.3.8Channel Length Modulation (CLM)161.3.9Velocity Saturation191.3.10 Subthreshold Conduction201.3.11 Field Dependent Mobility221.3.12 Substrate Current induced Body Effect24(SCBE)1.3.13 Gate Induced Drain Leakage (GIDL)271.3.14 Polysilicon Gate Depletion281.3.15 Velocity Overshoot291.3.16 Source and Drain Resistance Effect29iii
1.3.17 Effective Width and Effective Length301.4Why Focus on STI Mechanical Stress Effect Modeling?301.5Background and Objective311.6Contributions of the Proposed Compact Models321.7Chapter Summary33CHAPTER 2 : LITERATURE REVIEW2.0Chapter Overview342.1Background and Literature Review of STI Mechanical Stress34Effect2.2Literature Review of Modeling of STI Mechanical Stress Effect422.3Chapter Summary50CHAPTER 3 : MODELING OF STI MECHANICAL X-STRESSEFFECT3.0Chapter Overview513.1STI Mechanical x-Stress Effect523.1.1STI Mechanical x-Stress Effect on 0.18 μm CMOS52Technology3.1.2STI Mechanical x-Stress Effect on 0.13 μm CMOS59Technology3.2Modeling of STI Mechanical x-Stress Effect633.3Modeling of Width Dependence of STI Mechanical x-Stress67Effect3.4STI x-Stress Effect on CMOS Mismatch Characteristics693.5Modeling of STI x-Stress Effect on CMOS Mismatch73Characteristics3.6Chapter Summary76iv
CHAPTER 4 : MODELING OF STI MECHANICAL Y-STRESSEFFECT4.0Chapter Overview774.1STI Mechanical y-Stress Effect784.1.1814.24.3Verification of Hook Shaped Drain Current BehaviorModeling of STI Mechanical y-Stress Effect844.2.1Empirical-Based STI Mechanical y-Stress Model844.2.2Physical-Based STI Mechanical y-Stress Model864.2.3STI y-stress Model versus Standard SPICE Model904.2.4Extraction Methodology of STI y-Stress Model934.2.5Application of STI y-Stress Model96Chapter Summary102CHAPTER 5 : PHYSICAL EXPLANATIONS OF STI MECHANICALSTRESS EFFECT5.0Chapter Overview1035.1STI Induced Compressive Stress1045.2STI Stress Effect on Electron Mobility and Hole Mobility1055.3Interaction of x-Stress Effect and y-Stress Effect1105.4Chapter Summary113CHAPTER 6 : CONCLUSION AND FURTHER DEVELOPMENT6.0Conclusion1146.1Further Development115REFERENCES117PUBLICATIONS123v
APPENDICESACompact STI x-Stress HSPICE Model126for 0.13 μm Technology 1.2 V CMOS TransistorBEmpirical-Based STI x-Stress Width Dependence HSPICE129Model for 0.13 μm Technology 1.2 V CMOS TransistorCEmpirical-Based STI x-Stress Mismatch HSPICE Model132for 0.18 μm Technology 1.8 V CMOS TransistorDPhysical-Based STI y-Stress HSPICE Model135for 0.13 μm Technology 1.2 V High-Vt CMOS TransistorEPhysical-Based STI y-Stress HSPICE Model138for 0.13 μm Technology 2.5 V CMOS Transistor141BIODATA OF AUTHORvi
LIST OF TABLESPageTable 2.1External applied mechanical tensile stress effect on Id asreported in (Kumagai et al., 2002).38Table 2.2Internal process-induced mechanical tensile stress on Idsatas reported in (Ge et al., 2003).39Table 2.3Piezoresistance coefficient of the compressive STI xstress and y-stress on NMOS and PMOS as reported in(Gallon et al., 2004).41Table 3.1Summary of short channel Vtlin change due to STI x-stressfor 0.18 μm CMOS technology. Published in (Tan et al.,2004a and Tan et al., 2004b).53Table 3.2Summary of short channel Idsat change due to STI x-stressfor 0.18 μm CMOS technology. Published in (Tan et al.,2004a and Tan et al., 2004b).55Table 3.3Summary of short and long channels Idsat change inpercentage due to STI x-stress for 0.18 μm CMOStechnology. Published in (Tan et al., 2004a).58Table 3.4Summary of short channel Vtlin change due to STI x-stressfor 0.13 μm CMOS technology.61Table 3.5Summary of short channel Idsat change due to STI x-stressfor 0.13 μm CMOS technology.63Table 3.6Summary of STI x-stress effect on CMOS transistor Vtmismatch and Id mismatch. Published in (Tan et al.,2004c).72Table 4.1Transistor sizes of 1.2 V High-Vt transistors and 2.5 Vtransistors for STI y-stress model verification.96Table 5.1Process-induced mechanical compressive stress on Idsatas interpreted from paper (Ge et al., 2003).105Table 5.2Actual silicon results of W dependence on x-stress effectand L dependence on y-stress effect for NMOS andPMOS transistors.110vii
LIST OF FIGURESPageFigure 1.1Non-uniform depletion width when Vd 0 V (Cheng andHu, 1999).7Figure 1.2Charge regions: (a) in long channel; (b) in short channel(Liu, 2001).8Figure 1.3Lateral doping profile with pocket implantation (Chengand Hu, 1999).10Figure 1.4Vt versus L characteristics of a transistor with RSCE(Cheng and Hu, 1999).10Figure 1.5CMOS transistor with LOCOS isolation technology (Liu,2001).11Figure 1.6CMOS transistor with STI isolation technology.12Figure 1.7Surface potential versus L for (a) long channel transistor(b) short channel transistor, and (c) short channeltransistor at high Vd (Taur and Ning, 1998).14Figure 1.8Conduction band profile showing DIBL effect in shortchannel transistor (Yeo, 2005).15Figure 1.9CMOS transistor operates in; (a) linear region, (b) onsetof saturation, (c) beyond saturation where CLM occurs(Taur and Ning, 1998).17Figure 1.10Id-Vd curves with Vg,2 Vg,1, showing the relationshipbetween Va and the slope of Id in saturation (Liu, 2001).18Figure 1.11Id-Vd characteristics with velocity saturation, solid linesand as if there were no velocity saturation, dashed lines(Taur and Ning, 1998).20Figure 1.12Subthreshold characteristics of short and long channeltransistors at low and high Vd (Taur and Ning, 1998).21Figure 1.13Mobility versus Vertical Effective Field to illustrate howthe mobility behavior is dominated by differentscattering mechanisms (Cheng and Hu, 1999).23Figure 1.14Id-Vd characteristics due to SCBE (Cheng and Hu,1999).24Figure 1.15SCBE effect that increases Isub and Id due to impactionization (Cheng and Hu, 1999).25viii
Figure 1.16Id-Vd and Rout characteristics to illustrate how theirbehaviors are dominated by CLM, DIBL and SCBE(Cheng and Hu, 1999).26Figure 1.17NMOS drain region when the channel is (a) inverted, (b)accumulated and (c) when n region surface isdepleted or inverted (Taur and Ning, 1998).27Figure 1.18Poly gate depletion region (Cheng and Hu, 1999).28Figure 2.1Layout styles of the W/L 20 μm/0.2 μm transistor(Scott et al., 1999).35Figure 2.2NMOS Idsat versus layout types. Idsat decrease in smalltype L 0.2 μm is equivalent to 30 nm increase in L formedium type L 0.2 μm (Scott et al., 1999).35Figure 2.3(100) silicon wafer coordinates.36Figure 2.4Id change due to external x-stress (Kumagai et al.,2002).37Figure 2.5Id change due to external y-stress (Kumagai et al.,2002).37Figure 2.6Id change due to external z-stress (Kumagai et al.,2002).37Figure 2.7Idsat change due to external applied stress for (a) PMOSand (b) NMOS with 500 μm gate length (Chen andHuang, 2002).38Figure 2.83D process-induced strain components (Ge et al.,2003).39Figure 2.9STI mechanical x-stress effect on Id at different W(Chan et al., 2003).40Figure 2.10STI mechanical x-stress effect on Id at different L (Chanet al., 2003).40Figure 2.11Distance between STI edge and gate edge, “a” (Bianchiet al., 2002).43Figure 2.12Mobility change referenced to mobility at “a min”, plottedversus "a" (Bianchi et al., 2002).43Figure 2.13Mobility change reference to mobility at “a min”, plottedversus “(a – a min)/a” (Bianchi et al., 2002).44Figure 2.142D simulation results and transistor layout (Su et al.,2003).46ix
Figure 3.1Compressive STI mechanical stress on a CMOStransistor.51Figure 3.2Short channel Vtlin versus sa characteristics for 0.18 μmCMOS technology. N 32 dice. Published in (Tan et al.,2004a and Tan et al., 2004b).53Figure 3.3Short channel Idsat versus sa characteristics for 0.18 μmCMOS technology. N 32 dice. Published in (Tan et al.,2004a and Tan et al., 2004b).55Figure 3.4Effect of STI y-stress on wide width and narrow widthtransistors.56Figure 3.5Long channel Vtlin versus sa characteristics for 0.18 μmCMOS technology. N 32 dice. Published in (Tan et al.,2004a).57Figure 3.6Long channel Idsat versus sa characteristics for 0.18 μmCMOS technology. N 32 dice. Published in (Tan et al.,2004a).58Figure 3.7Short channel Vtlin versus sa characteristics for 0.13 μmCMOS technology. N 27 dice.60Figure 3.8Short channel Vtlin and Idsat versus sa characteristics for0.13 μm CMOS technology. N 27 dice. Published in(Tan et al., 2005a and Tan et al., 2006a).62Figure 3.9Accuracy of the proposed x-stress model on NMOS Vtlinversus sa characteristics. N 27 dice.65Figure 3.10Accuracy of the proposed x-stress model on NMOS Idsatversus sa characteristics. N 27 dice.65Figure 3.11Accuracy of the proposed x-stress model on PMOS Vtlinversus sa characteristics. N 27 dice.66Figure 3.12Accuracy of the proposed x-stress model on PMOS Idsatversus sa characteristics. N 27 dice.66Figure 3.13Fitting of the proposed W dependence model (Equation37) on NMOS Vtlin and Idsat versus sa characteristics. N 27 dice.68Figure 3.14Fitting of the proposed W dependence model (Equation38) on PMOS Vtlin and Idsat versus sa characteristics. N 27 dice.69Figure 3.15Standard deviation of delta Idsat versus 1/sqrt(W x L)mismatch characteristics. N 32 dice. Published in(Tan et al., 2003 and Tan et al., 2004c).72x
Figure 3.16Possible mechanism of STI x-stress effect on CMOStransistors mismatch.73Figure 3.17Fitting of the proposed mismatch model on NMOS Idsatmismatch characteristics. N 32 dice.75Figure 3.18Fitting of the proposed mismatch model on PMOS Idsatmismatch characteristics. N 32 dice.75Figure 4.1Actual silicon data showing a hook shaped Idsat curve.78Figure 4.2Percentage of Idsat change referenced to W 20 μm, for1.2 V NMOS transistors. N 171 dice. Published in(Tan et al., 2005d).80Figure 4.3Percentage of Idsat change referenced to W 20 μm, for1.2 V PMOS transistors. N 171 dice. Published in(Tan et al., 2005d).80Figure 4.4Transistor layout with artificial width defined by usingSelect layer.82Figure 4.5PMOS Idsat versus width curve with and without STI ystress. N 6 dice.83Figure 4.6NMOS Idsat versus width curve with and without STI ystress. N 6 dice.83Figure 4.7Standard versus the proposed empirical-based y-stressmodel on PMOS normal width and artificial width Idsatdata. N 1 die. Published in (Tan et al., 2006b).85Figure 4.8Artificial width method to characterize the STI y-stresseffect.86Figure 4.9Inverse exponential function fitting to Idsat degradationdue to STI y-stress.87Figure 4.10Fitting of 1/x and 1/(exp x) functions to the TCAD 2Dsimulation data of compressive STI stress intensity onsilicon.87Figure 4.11TCAD 2D simulation of the compressive STI stressintensity in transistor active area.88Figure 4.12Comparison of standard model versus STI y-stressmodel fitting for 1.2 V NMOS transistors. N 171 dice.91Figure 4.13Comparison of standard model versus STI y-stressmodel fitting for 1.2 V PMOS. N 171 dice.92Figure 4.14Effect of the STI y-stress parameters in fitting the hookshaped Idsat curve.93xi
Figure 4.15Parameters that control different regions of the hookshaped Idsat curve. Symbol is data and line is model.94Figure 4.16Effect of DW parameter, Pwint to the hook shaped Idsatcurve. Symbol is data, solid and dotted lines are beforeand after the parameter value change.95Figure 4.17Effect of first y-stress parameter, Pstyu01 to the hookshaped Idsat curve. Symbol is data, solid and dotted linesare before and after the parameter value change.95Figure 4.18Effect of second y-stress parameter, Pstyu02 to the hookshaped Idsat curve. Symbol is data, solid and dotted linesare before and after the parameter value change.95Figure 4.19Fitting of the proposed STI y-stress model on 1.2 VHigh-Vt NMOS Vtlin and Idsat. N 1 dice.98Figure 4.20Fitting of the proposed STI y-stress model on 1.2 VHigh-Vt PMOS Vtlin and Idsat. N 1 dice.99Figure 4.21Fitting of the proposed STI y-stress model on 2.5 VNMOS Vtlin and Idsat. N 1 dice.100Figure 4.22Fitting of the proposed STI y-stress model on 2.5 VPMOS Vtlin and Idsat. N 1 dice.101Figure 5.13D compressive stress directions in a CMOS transistor.103Figure 5.2Compressive stress induced by STI fabrication process.104Figure 5.3Current flow of conventional CMOS transistor in the[110] direction.105Figure 5.4Silicon lattice with outer electron orbit.106Figure 5.5Constant energy surface of conduction band.106Figure 5.6Constant energy surface of valence band (Thompson etal., 2004).107Figure 5.7Constant energy valleys of conduction band undercompressive x-stressed.107Figure 5.8Electrons effective mass in current flow direction.108Figure 5.9Conduction band splitting due to compressive x-, y- andz-stress.108Figure 5.10Constant energy valleys of valence band undercompressive x-stressed.109Figure 5.11Holes effective mass in current flow direction.109xii
Figure 5.12Holes redistribution in the constant energy valleys ofvalence band due to compressive x-, y- and z-stress.110Figure 5.13Constant energy valleys of conduction band for narrowwidth transistor under STI compressive x-stress.111Figure 5.14Constant energy valleys of valence band for narrowwidth transistor under STI compressive x-stress.112xiii
LIST OF SYMBOLS%Percent Greater or equalΔDeltaαPower term for L dependence STI stress effectπpi (3.142)μCarrier mobilityηIdeality factorμ0(a)Active space carrier mobilityμ0(a min)Minimum active space carrier mobilityμAmicro-AmpereμeffEffective carrier mobilityφfDifference of Fermi potential and substrate intrinsic potentialμmmicrometerδNPPositive sign for NMOS and negative sign for PMOSεoxOxide permittivity (12 x 8.85 x 10-12 F/m)εsSilicon permittivity (3.9 x 8.85 x 10-12 F/m) SmalleraActive spacea minMinimum active spaceAbulkBulk charge effectAgu0Gaussian distribution term for STI x-stress mismatchCCapacitanceCdepDepletion capacitance per unit area in the bulkCoxGate oxide capacitancedDistancexiv
EElectric Fieldf0, f1, f2Representation of complicated functionshPlanck's constant (6.6262 x 10-34 Js)ICurrentIdDrain currentId,0Ideal long channel IdIdlinLinear drain currentIdsatSaturation drain currentIoffLeakage current (off current)IsubSubstrate currentJCurrent densitykp x (h/2π)LChannel lengthLdrawnDrawn channel lengthLeffEffective channel lengthLodLength of transistor active area (length of oxide definition)LodActive lengthmmeterm*Effective ltNNumber of samplesncCarrier concentrationnmnanometerpMomentumPa0L dependence bulk charge parameterxv
PagsGate bias dependence bulk charge parameterPaidSTI x-stress mismatch magnitude parameterPalpha0First SCBE effect on Isub parameterPalpha1L dependence SCBE effect on Isub parameterPb0Channel width bulk charge parameterPb1Channel width offset bulk charge parameterPbeta0Second SCBE effect on Isub parameterPcdscDrain and source to channel coupling capacitance parameterPcdscbBody bias sensitivity of Pcdsc parameterPcdscdDrain bias sensitivity of Pcdsc parameterPcitInterface trap capacitance parameterPdsubVt L dependence exponent DIBL parameterPdvt0First SCE parameterPdvt0wFirst SS parameterPdvt1L dependence exponent SCE parameterPdvt1wL dependence exponent SS parameterPdvt2Body bias SCE parameterPdvt2wBody bias SS parameterPdwbBody bias channel width offset parameterPdwgGate bias channel width offset parameterPeta0Vt DIBL parameterPeta0 originalPeta0 without STI stress effectPetabVt body bias DIBL parameterPk1First-order body effect parameterPk2Second-order body effect parameterPk3NWE parameterPk3bBody effect NWE parameterxvi
PketaBody bias dependence bulk charge parameterPku0STI stress effect on Pu0 parameterPlintChannel length offset parameterPlku0, Pwku0, Ppku0STI stress effect of Pu0 binning parametersPlku1L fitting parameters for STI stress effectPll, Plw, Plwl, Plln, PlwnChannel length geometry scaling parametersPmobmodMobility mode parameterPmpSTI x-stress mismatch sensitivity parameterPnfactorSubthreshold turn-on swing parameterPngatePolysilicon gate doping concentration parameterPnlxRSCE parameterPnrdNumber of drain square parameterPnrsNumber of source square parameterPpclmChannel length modulation parameterPpdiblc1First DIBL correction on Va parameterPpdiblc2Second DIBL correction on Va parameterPpdiblcbBody bias DIBL correction on Va parameterPprwbBody bias dependence of Prdsw parameterPprwgGate bias dependence of Prdsw parameterPpscbe1First high Vd drain conductance modification parameterPpscbe2Second high Vd drain conductance modification parameterPpvagGate bias dependence Va parameterPrdswDrain and source resistance per μm of gate width parameterPrshSheet resistance parameterPsarefsa reference parameterPsbrefsb reference parameterPstxu01STI x-stress mobility parameterxvii
Pstxvth01STI x-stress Vt parameterPstxweSTI x-stress width dependence parameterPstxwepSTI x-stress width dependence exponential parameterPstyu01First STI y-stress parameterPstyu02Second STI y-stress parameterPtoxOxide thickness parameterPu0Zero field universal mobility parameterPu0 originalPu0 without STI stress effect or mismatch effectPuaFirst order mobility degradation parameterPubParabolic mobility degradation parameterPucBody bias mobility degradation parameterPvoffSubthreshold offset voltage parameterPvsatCarrier saturation velocity parameterPvsat originalPvsat without STI stress effectPvth0Zero back bias threshold voltage parameterPvth0 originalPvth0 without STI stress effectPw0Channel width offset NWE parameterPwintChannel width offset parameterPwl, Pww, Pwwl, Pwln, Pwwn Channel width geometry scaling parametersPwrExponent effective channel width of Prdsw parameterPwvth0Width binning parameter of Pvth0PwwChannel width offset parameterPxjSource/drain junction depth parameterPxlDelta widthPxwDelta lengthqElectron charge (1.6e-19 Coulombs)RdDrain resistancexviii
RdsDrain and source resistanceRoutOutput resistanceRsSource resistanceS0l, S1lL fitting parameters for STI stress effectsa, sbDistance between STI edge and gate edge (active space)TTemperatureTnomNominal temperatureVVoltageVaEarly voltageVbBulk voltageVbiBuilt-in voltageVdDrain voltageVd,effEffective drain voltage of linear to saturation smoothing functionVddOperating voltageVdsatSaturation drain voltageVgGate voltageVmμ0Maximum μ0(a) variation with respect to μ0(a min)VsSource voltageVtThreshold voltageVtlinLinear threshold voltageWChannel widthWdrawnDrawn channel widthWeffEffective channel widthxDistance from the center of the channelXdepChannel depletion thickness in the substrateXdep,0Channel depletion thickness in the substrate at zero back biasXpolyPoly depletion thicknessxix
LIST OF Active AreaBSIM3v3Berkeley Short-Channel IGFET Model – Version 3.3BSIM3v3.24Berkeley Short-Channel IGFET Model – Version 3.3.24BSIM3v3.3Berkeley Short-Channel IGFET Model – Version 3.3.3BSIM4Berkeley Short-Channel IGFET Model – Version 4BSIM4.3.0Berkeley Short-Channel IGFET Model – Version 4.3.0BSIM4.6.1Berkeley Short-Channel IGFET Model – Version 4.6.1BTBTBand-To-Band TunnelingCDCritical DimensionCLMChannel Length ModulationCMCCompact Modeling CouncilCMOSComplementary Metal Oxide SemiconductorCTECoefficient of Thermal ExpansionDCDirect CurrentDIBLDrain Induced Barrier LoweringDWDelta WidthEKVBulk-referencing SPICE modelexpExponentialGCAGradual Channel ApproximationGIDLGate Induced Drain LeakageHCEHot Carrier EffectHISIMHiroshima University SPICE modelHSPICECircuit simulation engine created by Meta-Softwarexx
ICIntegrated CircuitIEDMInternational Electron Devices MeetingIGFETInsulated Gate Field Effect TransistorINWEInverse Narrow Width EffectLDDLightly Doped DrainLOCOSLocalized-Oxidation-of-Silicon isolationMOSMetal Oxide SemiconductorNMOSN-type Metal Oxide SemiconductorNWENarrow Width EffectPMOSP-type Metal Oxide SemiconductorPSPPenn State Philips SPICE modelPSSProcess-strained SiliconRSCEReverse Short Channel EffectSCBESubstrate Current induced Body EffectSCEShort Channel EffectSDSource/drainSiSiliconSiO2Silicon dioxideSPICESimulation Program with Integrated Circuit EmphasissqrtSquare RootSSSmall SizestdevStandard DeviationSTIShallow Trench IsolationTCADTechnology Computer Aided DesignTSMCTaiwan Semiconductor Manufacturing CompanyXSIMNational Technology University SPICE modelxxi
PEMODELAN PADAT UNTUK TRANSISTOR CMOS DI BAWAHSUBMIKRON DENGAN KESAN TEKANAN MEKANIKAL PENGASINGANPEPARIT CETEKABSTRAKThesis ini memperkenalkan satu model padat, dua model berasaskan empirikaldan satu model berasaskan fizikal untuk kesan tekanan mekanikal PengasinganPeparit Cetek (STI) ke atas transistor CMOS di bawah submikron. Model tekanan-xSTI padat digunakan untuk menangkap tekanan dalam arah laluan transistor panjang.Model ini adalah lebih ringkas berbanding dengan model tekanan STI BSIM4, tetapidapat mencapai ketepatan yang serupa. Dua ciri-ciri baru tekanan-x STI telahdikenalpastikan. Ciri yang pertama adalah fakta bahawa kesan tekanan-x STI bagitransistor CMOS berubah untuk transistor lebar yang berlainan. Kesan ini telah dikesandalam teknologi-teknologi 0.18 μm dan 0.13 μm. Satu model kesan tekanan-x STIbergantung kepada lebar yang empirikal telah dicadangkan untuk menangkap kesanini. Ciri baru yang kedua adalah fakta bahawa kesan tekanan-x STI mengubah ciri-ciriketidaksamaan transistor CMOS. Satu model Monte Carlo yang empirikal telahdicadangkan untuk menangkap kesan ini. Satu lengkuk arus parit tepu (Idsat)berupabentuk cangkul berlawan dengan transistor lebar yang baru telah dikenalpasti.Lengkuk ini tidak dapat dimodelkan dengan mengunakan model tekanan STI BSIM4.Dengan mengunakan satu kaedah bentangan yang baru, ciri-ciri fizikal lengkuk initelah dikenalpasti. Lengkuk Idsat berupabentuk cangkul ini disebabkan oleh gabungankesan-kesan daripada tekanan-y STI (tekanan STI dalam arah laluan transistor lebar)yang menurunkan Idsat dan kesan Perubahan Lebar (DW) yang meningkatkan Idsat.Berdasarkan ciri-ciri fizikal ini, satu model tekanan-y STI yang fizikal diperkenalkanuntuk menangkap kelakuan Idsat berupabentuk cangkul ini. Ketepatan model-modelyang dicadangkan di dalam thesis ini dipastikan dengan mengunakan silikon databenar yang difabrikasikan dengan mengunakan teknologi-teknologi CMOS Silterra 0.18μm dan 0.13 μm yang berpiawaian industri. Model-model baru ini dibina dalam modelxxii
BSIM3v3 dengan mengunakan kaedah model makro (juga dikenali sebagai kaedahsublitar). Dua parameter SPICE, parameter voltan ambang tiada pincang belakang,Pvth0 dan parameter kelincahan pembawa, Pu0, telah digunakan untuk membina modelmodel ini. Perbezaan masa simulasi antara model makro dan model konventionaladalah tidak ketara ( 5 %).xxiii
COMPACT MODELING OF DEEP SUBMICRON CMOS TRANSISTORWITH SHALLOW TRENCH ISOLATION MECHANICAL STRESS EFFECTABSTRACTThis thesis introduces a compact model, two empirical-based models and aphysical-based model of Shallow Trench Isolation (STI) mechanical stress effect ondeep submicron CMOS transistor. The compact STI x-stress model is used to capturethe stress effect in the channel length direction. This model is simpler than the BSIM4STI stress model, but able to achieve the similar accuracy. Two new characteristics ofSTI x-stress have been identified. The first characteristic is the fact that the STI xstress effect on CMOS transistor varies for different transistor channel widths. Anempirical width dependence of STI x-stress effect model has been proposed to capturethis effect. The second new characteristic is the fact that STI x-stress effect changesthe CMOS transistor mismatch characteristics. An empirical Monte Carlo model isproposed to capture this effect. A new hook shaped saturation drain current, Idsat curveversus channel width has been identified. This curve cannot be modeled using theBSIM4 STI stress model. By using a new layout method, the physical characteristics ofthe curve are identified. The hook shaped Idsat curve is caused by the combined effectsof STI y-stress (stress in the channel width direction) that degrades the Idsat and theDelta Width (DW) effect that increases the Idsat. Based on the physical characteristics, anew physical-based STI y-stress model is proposed to capture the hook shaped Idsatbehavior. The accuracy of the models in this thesis is verified on actual silicon datafabricated using Silterra’s industry-standard 0.18 μm and 0.13 μm CMOS technologies.These new models are incorporated into the BSIM3v3 model by using macro modelmethod (also known as subcircuit method). The two SPICE parameters, the zero backbias threshold voltage parameter, Pvth0 and the carrier mobility parameter, Pu0, are usedfor developing these models. The difference in simulation time between the macromodel and the conventional model is insignificant ( 5 %).xxiv
CHAPTER 1INTRODUCTION1.0Chapter OverviewThis chapter introduces the compact modeling works in this thesis. First, thebasic concept of compact modeling is introduced. Then, the history of compactmodeling of CMOS transistor which started with the theory Gradual ChannelApproximation (GCA) is reviewed. How the important deep submicron effects of CMOStransistor are captured in BSIM3v3 equations are then discussed.After reviewing the theoretical concept of compact modeling, the reasons whythis research focuses on SPICE modeling of the STI stress effect on CMOS transistoris discussed. The background and objective of this research are then given. Finally, thecontribution of the proposed STI mechanical stress models to compact modelingresearch is discussed.1.1Introduction to Compact ModelingCompact model is basically a set of simplified physics equations that describethe behaviors of semiconductor devices and able to run with SPICE simulator atminimum time. Compact modeling is finding the parameter values for the compactmodel equations to achieve a good fit between the simulation data and the measureddata. The main objective of the compact modeling is to enable the accurate predictionof circuit performance before actual fabrication.When transistor scaling goes to deep submicron, more and more significantphysical phenomena need to be captured by compact model. The physical phenomenathat are negligible in the CMOS micron technology have dominated the behavior of theCMOS deep submicron technology.Many researchers have put in much effort in establishing the set of equations(Compact Model) that can provide the most accurate circuit simulation at the minimum1
time. Berkeley Short-Channel IGFET models (BSIM3v3 and BSIM4 models) arecurrently widely used by wafer fabrication foundries and IC design houses. OtherSPICE models such as PSP model, EKV model, HISIM model and XSIM model arealso popular. The standardization of these models is performed by an independentorganization called Compact Model Council (CMC).All the modeling works in this thesis is based on BSIM3v3.24, where the finalreleased version is BSIM3v3.3 model (Cheng et al., 2005). In short, these BSIM3v3family models, which built on similar source code, are known as BSIM3v3 model in thisthesis. The discussion in this thesis also references to BSIM4.3.0 (Xi et al., 2003) andBSIM4.6.1 (Dunga et al., 2007) models for STI stress model discussion. In short, all theBSIM4 family models are known as BSIM4 models in this thesis. The BSIM4 model isbuilt on a different source code compared to the BSIM3v3. Hence, the BSIM4 model isnot backward compatible to the BSIM3v3 model. The technology nodes of theexperimental transistors that are used in this thesis are 0.18 μm and 0.13 μm.1.2History of Compact ModelingCompact modeling is originally driven by the need to express the CMOStransistor behavior in quantitative form. Specifically, to design circuits with CMOStransistors, how much current is carried in the “on” state of a transistor and how muchleakage current flows in the “off” state must be calculated. In short, the current-voltage,I-V and capacitance-voltage, C-V characteristics of the CMOS transistor are needed,specifically the quantitative relationship between the drain current and terminalvoltages.In the beginning of the compact modeling era, there were four long-channelCMOS transistor models proposed for DC circuit simulation (or calcula
d change due to external x-stress (Kumagai et al., 2002). 37 Figure 2.5 I d change due to external y-stress (Kumagai et al., 2002). 37 Figure 2.6 I d change due to external z-stress (Kumagai et al., 2002). 37 Figure 2.7 I dsat change due to external applied stress for (a) PMOS and (b) NMOS with 500 μm gate length (Chen and Huang, 2002). 38
