WIXLIB

Analog Circuit Design withSubmicron TransistorsBernhard BoserUC BerkeleyDepartment of Electrical Engineering and Computer Sciencesboser@eecs.berkeley.eduAnalog Circuit Design with Submicron Transistors 2004 B. Boser 1

Analog Circuit Design Objective:Translate circuit specifications(gain, bandwidth, dynamic range, )into transistor sizes and bias currents Challenge:Accurate device models for deep submicrontransistors– “Square-law model”– Simulation models (BSIM, EVK, )– “Model” for analog designAnalog Circuit Design with Submicron Transistors 2004 B. Boser 2

Device Model Objectives Device Physics Simulation / Verification– Accuracy, efficiency (Analog) Circuit Design– Relate device characteristics to circuit specifications– E.g. BandwidthGainPower dissipationDynamic range (noise)– Accurate, simpleAnalog Circuit Design with Submicron Transistors 2004 B. Boser 3

Device Parameters for Analog Design Large signal– Current ID Æ power dissipation– Minimum VDS Æ available signal swing Small signal– Transconductance gm Æ speed / voltage gain– Capacitances CGS, CGD, Æ speed– Output impedance ro Æ voltage gainAnalog Circuit Design with Submicron Transistors 2004 B. Boser 4

Metrics for Design Transistor Objectives: High transconductance– Without large ID– Without large CGS Figures of Merit– Current efficiencygmID– Transit frequencygmC gsAnalog Circuit Design with Submicron Transistors 2004 B. Boser 5

Current Efficiency “Square-law transistor”:W1µCox (VGS VTH )22L2I Dgm VGS VTHID 2I DVdsatÅ Overdrive voltage High efficiency Æ low overdrive voltageAnalog Circuit Design with Submicron Transistors 2004 B. Boser 6

Current Efficiency gm/ID High efficiency is goodfor low power Higher gm/ID at low VGS Approaches BJT forVGS VTHgm/IC 1/Vt 40 V-1 Weak dependence ontransistor type andprocessAnalog Circuit Design with Submicron Transistors 2004 B. Boser 7

Transit Frequency ωT Unity current-gain bandwidthgmωT C gs C gd µVdsat2L(square - law model)Analog Circuit Design with Submicron Transistors 2004 B. Boser 8

Efficiency gm/ID versus fTSpeed-EfficiencyTradeoffNMOS faster thanPMOSAnalog Circuit Design with Submicron Transistors 2004 B. Boser 9

Device Scaling60500.18µmfT 0.40.5VGS-VTH [V]Short channel devices are significantly faster!Analog Circuit Design with Submicron Transistors 2004 B. Boser 10

Current Efficiency vs Transient frequency Tradeoff:gm1 satI D VdωT Vdsat What about:µgm ωT 2IDLAnalog Circuit Design with Submicron Transistors 2004 B. Boser 11

Device Figure-of-Merit4000.18µm350fT g m/ID .00.10.20.30.40.5V G S -V TH [V]Peak performance for low VGS-VTHAnalog Circuit Design with Submicron Transistors 2004 B. Boser 12

Device Scaling for Analog Circuits “Moore’s Law”– Lmin decreases 2x every 5 years– Lmin 10µm in 1970, 90nm in 2004 Benefits (for analog circuits):– Higher speed: increase gm/Cgs while keeping gm/IDconstant– Lower power: increase gm/ID while keepingbandwidth (gm/Cgs) constant In both cases, reducing L is advantageous!Analog Circuit Design with Submicron Transistors 2004 B. Boser 13

Short Channel Devices Short channel effects– Velocity saturation– Mobility degradation (thin oxide) Prior considerations assume “square law”models and ignore these effectsÆ Significant discrepancies Let’s fix this Analog Circuit Design with Submicron Transistors 2004 B. Boser 14

Efficiency gm/ID Important design parameter but a little unusual: units 1/V Let’s defineV* 2IDgmgm2 ID V * e.g. V* 200mV Æ gm/ID 10 V-1 Square-law devices only: V* VGS-VTH VdsatSquare law :gm 2ID2I DVGS VTH V *Analog Circuit Design with Submicron Transistors 2004 B. Boser 15

Saturation Voltage versus V* Saturation voltage– Minimum VDS for “high” output resistance– Poorly defined: transition is smooth inpractical devices “Long channel” (square law) devices:– VGS – VTH Vdsat Vov V*– Significance: Channel pinch-off2 I Vdsat with Submicron TransistorsAnalogDCircuit Design 2004 Boundary between triode and saturationB. Boser 16

Design ExampleExample: Common-source ampav0 100, fu 100MHz for CL 5pFDC AnalysisDevice VgsDC1 av0 100 Æ L 0.5µmsweep from 800m to 900m (1001 steps)AC AnalysisAC1log sweep from 1k to 10G (101 steps) g m 2πf uCL 3.14mSI1dc 393uAVoViVgsdc 820mVac 1VM138 / 0.5C15pF High fT (small CGS): V* 250mVg mV * 393µA ID 2Analog Circuit Design with Submicron Transistors 2004 B. Boser 17

Device SizingNMOSW / L 10 / 0.5 Pick LPick V*Determine gm0.5µm250mV3.14mS ID 0.5 gm V*393µA W from graph(generate with SPICE)Æ W 10µm (393µA /103µA) 38µm Analog Circuit Design with Submicron TransistorsCreate such graphs forseveral device length’ fordesign reference 2004 B. Boser 18

Common Source ExampleDead on!Analog Circuit Design with Submicron Transistors 2004 B. Boser 19

Device Sizing ChartW 10µm for all devicesVSB 0VVDS VGSAnalog Circuit Design with Submicron Transistors 2004 B. Boser 20

Device Sizing ChartW 10µm for all devicesVDS VGSVSB 0VAnalog Circuit Design with Submicron Transistors 2004 B. Boser 21

Device Parameters for Analog Design Large signal– Current ID Æ power dissipation– Minimum VDS Æ available signal swing Small signal– Transconductance gm Æ speed / voltage gain– Capacitances CGS, CGD, Æ speed– Output impedance ro Æ voltage gainAnalog Circuit Design with Submicron Transistors 2004 B. Boser 22

Output Resistance roHopeless to model thiswith a simple equation(e.g. gds λ ID)Analog Circuit Design with Submicron Transistors 2004 B. Boser 23

Process Variations for roL 0.35µmAnalog Circuit Design with Submicron Transistors 2004 B. Boser 24

Open-loop Gain av0More useful than roAnalog Circuit Design with Submicron Transistors 2004 B. Boser 25

Gain, av0 gm ro (gm/ID 10/V)L 0.35µm Strong tradeoff:av0 versus VDS range Create such plots forseveral device length’for design referenceAnalog Circuit Design with Submicron Transistors 2004 B. Boser 26

Gain, av0 gm ro (gm/ID 10/V)L 0. 5µmLÇÆav0 Çlike long channel deviceAnalog Circuit Design with Submicron Transistors 2004 B. Boser 27

Technology Trend800.5µm700.35µm60gm 4VDS [V]Short channel devices suffer from reduced per transistor gainAnalog Circuit Design with Submicron Transistors 2004 B. Boser 28

Transistor Gain Detail45400.5µm35g m r DS [V]For practical VDS the effect the “short-channel” gain penalty is less severe(remember: worst case VDS is what matters!)Analog Circuit Design with Submicron Transistors 2004 B. Boser 29

Current Sources (Biasing)Analog Circuit Design with Submicron Transistors 2004 B. Boser 30

CascodingHow choose Vbias2?Analog Circuit Design with Submicron Transistors 2004 B. Boser 31

Output ResistanceAnalog Circuit Design with Submicron Transistors 2004 B. Boser 32

Rout f(k)VDS 1 kV1*How choose k? Issues: Swing versus Ro Large k useful only for largeVmin simultaneously Note: small or no penalty forlarge k and small Vmin Æ typically choose k 1Analog Circuit Design with Submicron Transistors 2004 B. Boser 33

High-Swing Bias ExampleAnalog Circuit Design with Submicron Transistors M5 M10 replacequarter size device All devices same size Less sensitive tobody-effect Lcurrent-source Lcascode 2004 B. Boser 34

Noiseion2 id21 M 2 id2 2 4k BTγ (g m1 M 2 g m 2 ) f 4k BTγg m1 (1 M ) f1 4 k BT fRN1 γ 1RN g m1 1 Mro γ 1 Ro roav 0 1 M M2 (and Iref!) can add noise– Choose small M (power penalty), or– Filter at gate of M1 Current source FOMs– Output resistance Ro– Noise resistance RN– Active sources boost Ro, not RNAnalog Circuit Design with Submicron Transistors 2004 B. Boser 35

Vmin versus NoiseVmin k V *typ. k 1.2 Voltage required for large Ro(saturation): Vmin V* (based onintuition from square-law model) Minimizing noise (for given ID):Æ large RNÆ large Vmin (k 1) At odds with signal swing(to maximize the dynamic range)1 γ 1RN g m1 1 MVmin γ 1 2 KI D 1 MAnalog Circuit Design with Submicron Transistors 2004 B. Boser 36

Bipolar’s, GaAs, 221g m RE2ion2 icn2 iRn f1 g m RE1 g m RE1442443 1442443BJT(i2b 0)IrefioREQ2ion2 2k BTgm fa) g m RE 02 2VtRN gmICb) g m RE 1ion2 4k BTCbigVmin Vmin VcesatRN RE ICVmincompareRN , MOSREset by I C1 fREVmin γ 1 I D 2KQ1 REBJT and RE contribute noiseIncreasing RE lowers overall noiseBJT and MOS exhibit essentiallysame noise / Vmin tradeoffLowest possible noise source is aresistor (and large Vmin, VDD)Analog Circuit Design with Submicron Transistors 2004 B. Boser 37

Small Signal Design Summary Determine gm (from design objectives) Pick L–– Short channel Æ high fTLong channel Æ high ro, av0Pick V* 2ID/gm–––Small V* Æ large signal swingHigh V* Æ high fTDynamic range: Psig 1/V*, Pnoise V* Determine ID (from gm and V*) Determine W (SPICE / plot) Accurate for short channel devices Æ key for designAnalog Circuit Design with Submicron Transistors 2004 B. Boser 38

Device Parameter SummaryDeviceParameterCircuit ImplicationsV* Current efficiency, gm/IDPower dissipation (ID)Speed (gm)Cutoff frequency, fT Æ phase marginHeadroom, VDS,minL Cutoff frequency, fT Æ phase margin Intrinsic transistor gain (av0)W Obtain from L, ID Self loading (CGS, CDB, )Analog Circuit Design with Submicron Transistors 2004 B. Boser 39

Analog Circuit Design with Submicron Transistors 2004 B. Boser 3 Device Model Objectives Device Physics Simulation / Verification