WIXLIB

General4 General4.1 Absolute maximum ratingsNOTEFunctional operating conditions appear in the DC electricalcharacteristics. Absolute maximum ratings are stress ratingsonly, and functional operation at the maximum values is notguaranteed.Stress beyond the listed maximum values may affect devicereliability or cause permanent damage to the device.Table 2. Absolute maximum ratingsSymbol 1VDDE A, VDDE B,VDDE SDRVDD LP DECVDDAVDDEH ADCVSSAParameterConditionsMinMaxUnitInput/output supply voltage2—–0.33.6VDecoupling pin for low power regulators3—–0.321.32VADC supply voltage—–0.36.0VADC I/O supply voltage—–0.36.0VADC supply ground—–0.30.3VVDDA REF4ADC supply voltage—–0.36.0VVDDM SMDSMD supply voltage—–0.36.0VVSSM SMDSMD supply ground—–0.30.3VVDDE DDRDDR2 DRAM supply voltage—–0.32.3VDDR VREFDDR I/O Reference Voltage—–0.31.15VCore logic supply voltage—–0.31.32VRelative toVDDE A,VDDE B,VDDE SDR–0.3VDDE ADC 0.3V–0.3VDDE A 0.3VRelative toVDDE A,VDDE B,VDDE SDR–0.3VDDE x 0.3VAlways–55mA5VDD12VINAVoltage on ADC analog pin with respect toVSSAVoltage on Analog comparator pin (CMP)with respect to VSSVINVoltage on any digital pin with respect toground (VSS)IINJPADInjected input current on any pin duringoverload conditionIINJSUMAbsolute sum of all injected input currentsduring overload condition—–5050mATrampSupply ramp rate—0.5 V / min100 V/ms—Ta 6Ambient temperature—–40105 CTSTGStorage temperature—–55165 CSAC57D54H, Rev. 7, 05/2017NXP Semiconductors9

General1. All parameters are with reference to Vss unless otherwise specified.2. A crossover current of up to 2 mA may be experienced if VDD12 is ramped up before VDDE A supply. This current is only anelectrical crossover but has no functional implications, and should be removed when VDDE A ramps up to its functionaloperating range.3. Not available for input voltage, only for decoupling internal regulators.4. VDDA REF is only available on the 516 BGA package.5. DDR VREF is expected to be equal to 0.5 VDDE DDR and to track VDDE DDR DC variations as measured at the devicepins. Ensure VDD LV supply ramps up before VDDE DDR. In Standby mode, it should be ensured that VDDE DDR supplyshould be cut off.6. Tj 125 C. Assumes Ta 105 C. Assumes maximum θJA of 2s2p board. See Thermal attributes section for details.4.2 Recommended operating conditionsThe following table describes the operating conditions for the device, and for which allspecifications in the data sheet are valid, except where explicitly noted. The deviceoperating conditions must not be exceeded in order to guarantee proper operation andreliability. The ranges in this table are design targets and actual data may vary in thegiven range.For normal device operations, VDDE A, VDDA, VDDA REF, VDDEH ADC and VDD12supplies must be within operating range corresponding to the range mentioned infollowing tables. This is required even if some of the features are not used. If using theADC to convert SSD channels then VDDA should always be VDDM SMC.VDD12 should be supplied externally. VDDA REF, the supply port to 516 BGA is shorted toVDDA inside lower pin packages. Stepper Stall Detect module (SSD) should only beoperated in the 4.5 V to 5.5 V range and so cannot be used if VDDM SMD is in 3.3 Vrange.Table 3. Recommended operating conditionsSymbol 1ParameterConditionsMin2MaxUnitVDDE AInput/output supply voltage—3.153.6VVSSAADC supply ground, relative toVSS—-0.10.1VVDDAADC supply voltage3.155.5VVDDEH ADCADC I/O supply voltage3.155.5VVDDA REFADC reference voltageVDDA,VDDA REF and VDDEH ADCshould be within /-25 mV ofeach other3.155.5VVDDE B3VDDE SDR3VDDM SMDSMD supply voltage—3.155.5VVDDE DDRDDR2 supply voltage—1.71.9VDDR VREFDDR I/O Reference Voltage—VDDE DDR(min)/2VDDE DDR(max)/2VVDD124Core logic supply voltage—1.201.32VTable continues on the next page.SAC57D54H, Rev. 7, 05/201710NXP Semiconductors

GeneralTable 3. Recommended operating conditions (continued)Symbol 1ParameterConditionsMin2MaxUnitVSSEH ADCADC supply ground, relative toVSS—-0.30.3VIINJPADInjected input current on anypin during overload condition—-3.03.0mATa5Ambient temperature underbias–40105 C1. All parameters are with reference to Vss, unless otherwise specified.2. Device will be functional (and electrical specifications as per various datasheet parameters will be guaranteed) until one ofthe LVD/HVD resets the device. When voltage drops outside range for an LVD/HVD, device is reset.3. VDDE A, VDDE B and VDDE SDR are all independent supplies and can each be set to 3.3 V. However, care must be takenover LCD inputs that operate across the IO segments.4. Only applicable when supplying from external source. VDD12 supply pins should never be grounded (through a smallimpedance). If not driven, these should only be left floating.5. Tj 125 C. Assumes Ta 105 C. Assumes maximum θJA of 2s2p board. See Thermal attributes section for details.4.3 Voltage regulator electrical specificationsThe voltage regulator is composed of the following blocks: Connect an external 1.25 V nominal directly Low voltage detector - low threshold (LVD HV A) for VDDE A supply Low voltage detector (LVD FLASH) for 3.3 V flash supply Various low voltage detectors (LVD LV x) for digital core supply (VDD12) High voltage detector (HVD LV) for digital core supply (VDD12) Power on Reset (POR LV) for 1.25 V digital core supply (VDD12) Power on Reset (POR HV) for VDDE ASAC57D54H, Rev. 7, 05/2017NXP Semiconductors11

GeneralVDD LP DECULPREGCULPREGVssV DD12VssDEVICEFigure 3. Voltage regulator capacitance connectionTable 4. Voltage regulator electrical specificationsSymbolCulp regParameterConditionsExternal decoupling / stabilityMin, max values shall becapacitor for internal low power granted with respect toregulatortolerance, voltage, temperature,and aging variationsCombined ESR of ��0.1Ohm1. Typical values will vary over temperature, voltage, tolerance, drift, but total variation must not exceed minimum andmaximum values.4.3.1 Decoupling capacitor valuesFollowing are the requirements for supply decoupling on various power domains: For VDDE A, VDDE B, VDDE SDR, VDDM SMD, VDDE DDR, VDDA,VDDEH ADC,VDDA REF, DDR VREF supplies: 0.1 μF close to each VDD/VSS pin pair. 1 μF on each side of the chip for each supply domain. 10 μF near for each power supply source (except for VDDM SMD pins where ahigher capacitance value may be needed depending upon motor characteristics).SAC57D54H, Rev. 7, 05/201712NXP Semiconductors

General For VDD12, 0.1 μF close to each VDD/VSS pin pair is required.4.4 Voltage monitor electrical specificationsTable 5. Voltage monitor electrical specificationsSymbolParameterState ConditionsConfigurationPowerUp 1VPOR LVLV supplypower on oReset TypeDestructiveTrimmedVHVD LV coldVLVD LV PD2 hotVLVD LV PD0 hotVPOR HVVLVD IO A LOLV supply high Fallvoltagemonitoring,detecting at the Risedevice pinUntrimmedLV supply low Fallvoltagemonitoring,detecting in the RisePD2 core (hot)areaUntrimmedLV supply low Fallvoltagemonitoring,detecting in the RisePD0 core (hot)areaUntrimmedHV supplypower on resetdetectorUntrimmedFallRiseHV IO A supply Falllow voltagemonitoring - lowRiserangeVLVD LV PD2 COL LV supply low FallvoltageDmonitoring,detecting at the Risedevice Disabled at StartTrimmed1.3250UntrimmedDisabled at tiveFunctionalDisabled at StartTrimmed1.14001.1550UntrimmedDisabled at StartTrimmed1.16001.17501. All monitors that are active at power up will gate the power up recovery and prevent exit from POWERUP phase until theminimum level is crossed. These monitors can in some cases be masked during normal device operation, but when activewill always generate a destructive reset.SAC57D54H, Rev. 7, 05/2017NXP Semiconductors13

General4.5 Power consumptionThe following table shows the power consumption for the device in the various modes ofoperation.Table 6. Power consumptionModeConfigurationTypMaxUnitRUN ModeCA5 320 MHz, CM4160 MHz, DDR2 320MHz, Dual Display (516BGA)8001500mARUN ModeCA5 320 MHz, CM4160 MHz, SDR 160MHz, Single Display(208 QFP)6001200mASTOP ModeCores halted, devicefully powered.240700mASTANDBY Mode1, 2ARTC/32 KHz 32 KBSRAM poweredμAARTC/32 KHz 8 KBSRAM powered50 (25 C)70 (25 C)500 (55 C)900 (55 C)1500 (85 C)2500 (85 C)2000 (105 C)4000 (105 C)45 (25 C)65 (25 C)500 (55 C)900 (55 C)1500 (85 C)2500 (85 C)2000 (105 C)4000 (105 C)μA1. Weak pull functionality provided in I/O pads must be used to configure I/Os in a known state (that does not causecontention with external connection on the pin) to avoid floating input to cause crow-bar currents and hence increasedleakage during low power modes.2. During STANDBY modes, it is recommended to keep VDDE A, VDDEH ADC, VDDAand VDDA REF powered to their respectivefunctional levels to obtain best power performance of the device. All other supplies are recommended be kept unpoweredin these low power modes.The following diagrams show the supply configuration of the device.SAC57D54H, Rev. 7, 05/201714NXP Semiconductors

GeneralFigure 4. Supply configuration4.6 Electrostatic discharge (ESD) specificationsElectrostatic discharges (a positive then a negative pulse separated by 1 second) areapplied to the pins of each sample according to each pin combination. The sample sizedepends on the number of supply pins in the device (3 parts (n 1) supply pin). Thistest conforms to the AEC-Q100-002/-003/-011 standard.NOTEA device will be defined as a failure if after exposure to ESDpulses the device no longer meets the device specificationrequirements. Complete DC parametric and functional testingshall be performed per applicable device specification at roomtemperature followed by hot temperature, unless specifiedotherwise in the device specification.Table 7. ESD 1Electrostatic dischargeTA 25 C(Human Body Model)conforming to AECQ100-002Electrostatic dischargeTA 25 CClassMax value2UnitH1C2000VC3A500VSAC57D54H, Rev. 7, 05/2017NXP Semiconductors15

I/O parametersTable 7. ESD ratingsSymbolConditions1Parameter(Charged Device Model)Classconforming to AECQ100-011Max value2Unit750 (corners)1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.2. Data based on characterization results, not tested in production.4.7 Electromagnetic Compatibility (EMC) specificationsEMC measurements to IC-level IEC standards are available from NXP on request.5 I/O parameters5.1 AC specifications @ 3.3 V rangeTable 8. Functional Pad AC Specifications @ 3.3 V rangeSymbolRise/Fall Edge (ns)Minpad sr hv(output)Drive Load (pF)MaxDrive/Slew Rate SelectMSB, 3.75/3.52511 (Recommended 5100112/1136/455000pad i hv/pad sr hv01001(input)2pad fc hv(output)0.6/0.61. Slew rate control modes2. Input slope 2 nsSAC57D54H, Rev. 7, 05/201716NXP Semiconductors

I/O parameters5.2 DC electrical specifications @ 3.3 V rangeTable 9. DC electrical specifications @ 3.3 V rangeSymbolVddeParameterValueI/O Supply VoltageUnitMinMax3.153.63VVihCMOS Input Buffer High Voltage (withhysteresis disabled)0.55 x VddeVdde 0.3VVilCMOS Input Buffer Low Voltage (withhysteresis disabled)Vss 0.30.40 x VddeVVih hysCMOS Input Buffer High Voltage (withhysteresis enabled)0.65 x VddeVdde 0.3VVil hysCMOS Input Buffer Low Voltage (withhysteresis enabled)Vss 0.30.35 x VddeVCMOS Input Buffer Hysteresis0.1 x VddeVhysVPull Ioh vil hysWeak Pullup Current measured whenpad 0.35 x Vdde2580µAPull Ioh vih hysWeak Pulldown Current measured whenpad 0.65 x Vdde2580µAIinact dDigital Pad Input Leakage Current (weakpull inactive) 2.52.5µA0.8 x Vdde—V—0.2 x VddeVVohOutput High Voltage1VolVoltage2Output LowVih ttlTTL High Level Input VoltageVil ttlTTL Low Level Input Voltage1.8VVhyst ttlTTL Input Hysteresis VoltageVih autoAutomotive High Level Input Voltage0.75 x VddeVdde 0.3VVil auto3Automotive Low Level Input Voltage 0.30.35 VddeVVhyst autoAutomotive Input Hysteresis Voltage0.11 x Vdde0.6V0.25VV1. Measured when pad is sourcing 2 mA.2. Measured when pad is sinking 2 mA.3. Auto levels are applicable to the ‘input only' channels (CH0-7) of the ADC pins5.3 AC specifications @ 5 V rangeTable 10. Functional pad AC specifications @ 5 V rangeSymbolRise/Fall Edge (ns)Minpad sr hv(output)Drive Load (pF)MaxDrive/Slew Rate SelectMSB, LSB1.2/1.2252.5/25011 (Recommended setting)Table continues on the next page.SAC57D54H, Rev. 7, 05/2017NXP Semiconductors17

I/O parametersTable 10. Functional pad AC specifications @ 5 V range (continued)SymbolRise/Fall Edge (ns)MinDrive Load (pF)Drive/Slew Rate SelectMaxpad fc hv(output)MSB, .32005.6/4.85021/1920041/4150151/1512001001001. Slew rate control modes5.4 DC electrical specifications @ 5 V rangeTable 11. DC electrical specifications @ 5 V rangeSymbolVddeParameterI/O Supply VoltageValueUnitMinMax4.55.5VVihCMOS Input Buffer High Voltage (with hysteresisdisabled)0.55 VddeVdde 0.3VVilCMOS Input Buffer Low Voltage (with hysteresisdisabled)Vss 0.30.40 VddeVVih hysCMOS Input Buffer High Voltage (with hysteresisenabled)0.65 VddeVdde 0.3VVil hysCMOS Input Buffer Low Voltage (with hysteresisenabled)Vss 0.30.35 VddeVVhysCMOS Input Buffer Hysteresis0.1 VddeVPull Ioh vil h ysWeak Pullup Current measured when pad 0.35 x Vdde(Vil hys)40120µAPull Ioh vih hysWeak Pulldown Current measured when pad 0.65 xVdde (Vih hys)40120µAIinact dDigital Pad Input Leakage Current (weak pull inactive) 2.52.5µATable continues on the next page.SAC57D54H, Rev. 7, 05/201718NXP Semiconductors

I/O parametersTable 11. DC electrical specifications @ 5 V range (continued)SymbolParameterValueUnitMinMaxVohOutput High Voltage10.8 x Vdde—VVolOutput Low Voltage2—0.2 x VddeVVih ttlTTL High Level Input Voltage2.0Vil ttlTTL Low Level Input VoltageVhyst ttlTTL Input Hysteresis Voltage0.3Vih autoAutomotive High Level Input Voltage3.8Vdde 0.3VAutomotive Low Level Input Voltage 0.32.2VVhyst autoAutomotive Input Hysteresis Voltage0.5Vih auto3Automotive High Level Input Voltage0.7 VddeVdde 0.3VVil auto3Automotive Low Level Input Voltage 0.30.47 VddeVAutomotive Input Hysteresis Voltag

- 32 KB Instruction cache, 32 KB Data cache - NEON SIMD Media Processing Engine - FPU supporting double precision floating point operations - Memory Management Unit - GIC Interrupt Controller - Up to 320 MHz ARM Cortex-M4, 32-bit CPU - Supports ARMv7 - ISA - 16 KB Instruction cache, 16 KB Data cache