Transcription
EECS 151/251ASpring 2020Digital Design and IntegratedCircuitsInstructor:J. WawrzynekLecture 5: FPGAs
FPGAs are in widespread useFar more different designs areimplemented in FPGAs than incustom chips.EE141
CS150 Project platform: Xilinx ML505-110Spring 2013EE141EECS150 - Lec02-SDS-FPGAsPage3 47
EECS151 FPGA Lab Board4EE141
FPGA: Xilinx Virtex-5 XC5VLX110TVirtex-5 enhanced die photoEE141A die is an unpackaged part
From die to PC board .Ball GridArray(BGA)6EE141
FPGA Overview Basic structure: two-dimensional array of logic blocks and flip-flops witha means for the user to configure (program):1. the interconnection between the logic blocks,2. the function of each block.EE141Simplified version of FPGA internal architecture7
Why are FPGAs Interesting? Technical viewpoint: For hardware/system-designers, like ASICs only better: “Tape-out” new design every fewminutes/hours. “reconfigurability” or “reprogrammability” mayoffer other advantages over fixed logic?– In-field reprogramming? Dynamic reconfiguration?Self-modifying hardware, evolvable hardware?Of course, the relative flexibility comes at theexpense of larger die area, slower circuits, and moreenergy per operation.8EE141
9EE141
Why are FPGAs Interesting? Staggering logic capacitygrowth (10000x):Year IntroducedDeviceLogic Cells“logic 954,56015,636,480 FPGAs have trackedMoore’s Law betterthan any otherprogrammable device.10EE141
Die Photos: Virtex FPGA vs. Pentium IV FGPA Vertex chip looks remarkably structured– Very dense, very regular structure “Full-Custom” Pentium chip somewhat more random in structure– Large on-chip memories (caches) are visible11EE141
Why are FPGAs Interesting? Logic capacity now only part of the story: on-chipRAM, high-speed I/Os, “hard” function blocks, . Modern FPGAs are “reconfigurable systems ona chip”Xilinx ZYNQ - embedded ARM coresXilinx Virtex-5 LX110T10GBps SerdesEthernet MACsPCI express Phy64 ALUs148 36Kb SRAM Blocks12EE141
FPGA InternalsEE141
Background for upcoming technical details A MUX or multiplexor is acombinational logic circuit that choosesbetween 2N inputs under the control ofN control signals. A latch is a 1-bit memory (similar to aSRAM storage cell).14EE141
FPGA Programmability FPGA programmability allows users to:1.define function of configurable logic blocks (CLBs),2.establish interconnection pathsbetween CLBs3.set other options, such as clock,reset connections, and I/O. Most FPGAs have “SRAM based”programmability. ––Programmable Cross-pointsLatch-based (Xilinx, Intel/Altera, )reconfigurablevolatilerelatively large.MOSFET usedas a “switch”15EE141
User Programmability Latches store theconfiguration.Configuration bitstream isloaded under user control.“partial reconfiguration”: aselective part of the arraycan be reprogrammedwithout disturbing the otherparts.Dynamic / runtimereconfiguration:reprogramming during acomputation.Most commonly the entiredevice is programmedwhen the system is booted.EE14116
Simplified FPGA Logic BlockFunction defined byconfiguration bit-stream Look up table (LUT) implements combinational logic function Register (Flip-flop) optionally stores output of LUT17EE141
4-LUT Implementation LUTLUT n-bit LUT is implemented as a2n x 1 memory: inputs choose one of 2nmemory locations. memory locations (latches)are loaded with values fromuser’s configuration bitstream. Inputs to mux control arethe logic block inputs.Result is a general purpose“logic gate”. n-LUT can implement anyfunction of n inputs!18EE141
LUT as general logic gate An n-lut is a direct implementation of afunction truth-table.Each latch location holds the value ofthe function corresponding to one inputcombination.Example: 4-lutExample: 2-input functionsA 2-lut Implements any function of 2inputs.How many of these are there?How many functions of n inputs?19EE141
FPGA Generic Design Flow Design Entry:– Create your design files using: HDL (hardware description languages: Verilog, VHDL)Design Implementation:– Logic synthesis (from HDL) followed by, Partition, place, and route to create configurationbit-stream file Design verification:– Reports from tools give estimated cost,performance, power– Optionally use simulator to check function,– Load design onto FPGA device (cable connects PC todevelopment board), optional “logic scope” on FPGAEE141 check operation at full speed in real environment.20
Example Partition, Placement, and Route Simplified FPGA structure: Example Circuit: collection of gates and flip-flopsCircuit combinational logic must be “covered” by 4-input 1-output LUTs.Flip-flops from circuit must map to FPGA flip-flops.(Best to preserve “closeness” to CL to minimize wiring.)Best placement in general attempts to minimize wiring.Vdd, GND, clock, and global resets are all “prewired”.21EE141
Example Partition, Placement, and RouteOUTIN Example Circuit: collection of gates and flip-flopsAABBTwo partitions. Each has single output, no more than 4 inputs, andno more than 1 flip-flop. In this case, inverter goes in both partitions.Note: the partition can be arbitrarily large as long as it has not morethan 4 inputs and 1 output, and no more than 1 flip-flop.22EE141
Xilinx FPGAs (interconnect detail)23EE141
Colors representdifferent types ofresources:LogicBlock RAMDSP (ALUs)ClockingI/OSerial I/O PCIA routing fabricruns throughoutthe chip to wireeverythingtogether.Spring 2013EE141EECS150 - Lec02-SDS-FPGAsPage6424
State-of-the-Art - Xilinx FPGAsVirtex Ultra-scale25EE141
Configurable Logic Blocks (CLBs)Slices define regular connections to the switchingfabric, and to slices inCLBs above and below it on the die.26EE141
Atoms: 5-input Look Up Tables (LUTs)QComputes any 5input logic 1).DTiming isindependentof sset duringconfiguration.27
Virtex 6-LUTs: Composition of 5-LUTsMay be usedas one6-input LUT(D6 out) . or as two5-input LUTS(D6 and D5)Combinationallogic(post configuration)28EE141
The simplest view of a sliceFour 6-LUTsFour Flip-FlopsSwitching fabric may seecombinational and registeredoutputs.An actual Virtex slice adds manysmall features to this simplifieddiagram. We show them one byone .Spring 2013EE14129
Two 7-LUTs per slice .Extramultiplexers(F7AMUX,F7BMUX)Extra inputs(AX and CX)Spring 2013EE14130
Or one 8-LUTs per slice .Thirdmultiplexer(F8MUX)Third input(BX)Spring 2013EE14131
Extra muxes to chose LUT option .From eight 5-LUTs. to one 8-LUT.Combinationalor registered outs.Flip-flops unused byLUTs can be usedstandalone.Spring 2013EE14132
Virtex Vertical LogicWe can mapripple-carry additiononto carry-chain block.The carry-chain blockalso useful for speedingup other adderstructures andcounters.Spring 2013EE14133
Putting it all together . a SLICEL.The previousslides explain allSLICEL features.About 50% of theare SLICELs.The other slicesare SLICEMs,and have extrafeatures.Spring 2013EE141EECS150 - Lec02-SDS-FPGAs34
Recall: 5-LUT architecture .32 Latches.Configured to 1 or 0.Q(1)Q(0)A[6:2]D000000000100010101.Q.DQ001Spring 2013EE141Some parts of a logicdesign need manystate s replace normal5-LUTs with circuits thatcan act like 5-LUTs, butcan alternatively use the32 latches as RAM,ROM, shift registers.35
Virtex DSP48E SliceEfficient implementation of multiply, add, bit-wise logical.36EE141
To be continued .Throughout thesemester, we will lookat different FPGAfeatures in-depth.Switch fabricBlock RAMDSP48 (ALUs)ClockingI/OSerial I/O PCIEE141EECS150 - Lec02-SDS-FPGAsPage7837
Lecture 5: FPGAs. EE141 FPGAs are in widespread use Far more different designs are implemented in FPGAs than in custom chips. EE141 Spring 2013 EECS150 - Lec02-SDS-FPGAs Page 3 CS150 Project platform: Xilinx ML505-110 47. EE141 EECS151 FPGA Lab Board 4. EE141 FPGA: Xilinx Virtex-5 XC5VLX110T
