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LTC2942OperationPower-Up SequenceWhen SENSE rises above a threshold of approximately2.5V, the LTC2942 generates an internal power-on reset(POR) signal and sets all registers to their default state.In the default state, the coulomb counter is active whilethe voltage and temperature ADC is switched off. Theaccumulated charge register is set to mid-scale (7FFFh),all low threshold registers are set to 0000h and all highthreshold registers are set to FFFFh. The alert mode isenabled and the coulomb counter prescaling factor M isset to 128.Applications InformationI2C/SMBus InterfaceThe LTC2942 communicates with a bus master using a2-wire interface compatible with I2C and SMBus. The 7-bithard-coded I2C address of the LTC2942 is 1100100.The LTC2942 is a slave-only device. Therefore the serialclock line (SCL) is an input only while the serial data line(SDA) is bidirectional. The device supports I2C standardand fast mode. For more details refer to the I2C Protocolsection.Internal RegistersThe LTC2942 integrates current through a sense resistor,measures battery voltage and temperature and stores theresults in internal 16-bit registers accessible via I2C. Highand low limits can be programmed for each measurementquantity. The LTC2942 continuously monitors these limitsand sets a flag in the onboard status register when a limitis exceeded. If the alert mode is enabled, the AL/CC pinpulls low.The sixteen internal registers are organized as shown inTable 1.Table 1. Register MapADDRESSNAME REGISTER DESCRIPTIONR/WDEFAULT00hAStatusRSee Below01hBControlR/W3Ch02hCAccumulated Charge MSBR/W7Fh03hDAccumulated Charge LSBR/WFFh04hECharge Threshold High MSBR/WFFh05hFCharge Threshold High LSBR/WFFh06hGCharge Threshold Low MSBR/W00h07hHCharge Threshold Low LSBR/W00h08hIVoltage MSBRXXh09hJVoltage LSBRXXh0AhKVoltage Threshold HighR/WFFh0BhLVoltage Threshold LowR/W00h0ChMTemperature MSBRXXh0DhNTemperature LSBRXXh0EhOTemperature Threshold HighR/WFFh0FhPTemperature Threshold LowR/W00hR Read, W Write, XX Unknown2942fa8

LTC2942Applications InformationStatus Register (A)The status of the charge, voltage and temperature alertsis reported in the status register shown in Table 2.Table 2. Status Register A (Read only)BITNAMEA[7] Chip IdentificationOPERATIONDEFAULT0: LTC29421: LTC29410A[6] Reserved0A[5] Accumulated Charge Indicates that the value of theOverflow/Underflow ACR hit either top or bottom.0A[4] Temperature AlertIndicates one of thetemperature limits wasexceeded.0A[3] Charge Alert HighIndicates that the ACR valueexceeded the charge thresholdhigh limit.0A[2] Charge Alert LowIndicates that the ACR valuedropped below the chargethreshold low limit.0A[1] Voltage AlertIndicates one of the batteryvoltage limits was exceeded.0A[0] UndervoltageLockout AlertIndicates recovery fromundervoltage. If set to 1, aUVLO has occurred and thecontents of the registers areuncertain.XAll status register bits except A[7] are cleared after beingread by the host, if the conditions which set these bitshave been removed.As soon as one of the three measured quantities exceedsthe programmed limits, the corresponding bit A[4], A[3],A[2] or A[1] in the status register is set.Bit A[5] is set if the LTC2942’s accumulated charge registers(ACR) overflows or underflows. In these cases, the ACRstays at FFFFh or 0000h and does not roll over.The undervoltage lockout (UVLO) bit of the status registerA[0] is set if, during operation, the voltage on SENSE pin drops below 2.7V without reaching the POR level.The analog parts of the coulomb counter are switched offwhile the digital register values are retained. After recovery of the supply voltage the coulomb counter resumesintegrating with the stored value in the accumulatedcharge registers but it has missed any charge flowingwhile SENSE 2.7V.The hard-coded bit A[7] of the status register enables thehost to distinguish the LTC2942 from the pin compatibleLTC2941, allowing the same software to be used withboth devices.Control Register (B)The operation of the LTC2942 is controlled by programming the control register. Table 3 shows the organizationof the 8-bit control register B[7:0].Table 3. Control Register BBITNAMEOPERATIONDefaultB[7:6] ADC Mode[11] Automatic Mode.Performs voltage and temperatureconversion every second.[10] Manual Voltage Mode.Performs single voltageconversion, then sleeps.[01] Manual Temperature Mode.Performs single temperatureconversion, then sleeps.[00] Sleep.[00]B[5:3] Prescaler MSets coulomb counter prescalingfactor M between 1 and 128.Default is 128.M 2(4 B[5] 2 B[4] B[3])[111]B[2:1] AL/CC Configure Configures the AL/CC pin.[10] Alert Mode.Alert functionality enabled.Pin becomes logic output.[01] Charge Complete Mode.Pin becomes logic input andaccepts “charge complete” signal(e.g., from a charger) to setaccumulated charge register (C, D)to FFFFh.[00] AL/CC pin disabled.[11] Not allowed.B[0]ShutdownShut down analog section toreduce ISUPPLY.[10][0]Power Down B[0]Setting B[0] to 1 shuts down the analog parts of theLTC2942, reducing the current consumption to less than1µA. All analog circuits are inoperative while the valuesin the registers are retained. Note that any charge flowingwhile B[0] is 1 is not measured and the charge informationbelow 1LSB of the accumulated charge register is lost.2942fa9

LTC2942Applications InformationAlert/Charge Complete Configuration B[2:1]The AL/CC pin is a dual function pin configured by thecontrol register. By setting bits B[2:1] to [10] (default)the AL/CC pin is configured as an alert pin following theSMBus protocol. In this configuration the AL/CC pin is adigital output and is pulled low if one of the three measured quantities (charge, voltage, temperature) exceedsits high or low threshold or if the value of the accumulatedcharge register overflows or underflows. An alert responseprocedure started by the master resets the alert at theAL/CC pin. For further information see the Alert ResponseProtocol section.Setting the control bits B[2:1] to [01] configures the AL/CCpin as a digital input. In this mode, a high input on theAL/CC pin communicates to the LTC2942 that the batteryis full and the accumulated charge register is set to itsmaximum value FFFFh. The AL/CC pin would typicallybe connected to the “charge complete” output from thebattery charger circuitry.If neither the alert nor the charge complete functionalityis desired, bits B[2:1] should be set to [00]. The AL/CCpin is then disabled and should be tied to GND.Avoid setting B[2:1] to [11] as it enables the alert and thecharge complete modes simultaneously.Choosing RSENSETo achieve the specified precision of the coulomb counter,the differential voltage between SENSE and SENSE– muststay within 50mV. For differential input signals up to 300mV the LTC2942 will remain functional but the precision of the coulomb counter is not guaranteed.The required value of the external sense resistor, RSENSE,is determined by the maximum input range of VSENSE andthe maximum current of the application:RSENSE 50mVIMAXThe choice of the external sense resistor value influencesthe gain of the coulomb counter. A larger sense resistorgives a larger differential voltage between SENSE andSENSE– for the same current which results in more precisecoulomb counting. Thus the amount of charge representedby the least significant bit (qLSB) of the accumulated charge(registers C, D) is equal to:qLSB 0.085mAh 50mΩ M RSENSE 128qLSB 0.085mAh 50mΩRSENSEorwhen the prescaler is set to its default value of M 128.Note that 1mAh 3.6C (coulomb).Choosing RSENSE 50mV/IMAX is not sufficient in applications where the battery capacity (QBAT) is very largecompared to the maximum current (IMAX):QBAT IMAX 5.5 HoursFor such low current applications with a large battery,choosing RSENSE according to RSENSE 50mV/IMAX canlead to a qLSB smaller than QBAT/216 and the 16-bit accumulated charge register may underflow before the batteryis exhausted or overflow during charge. Choose, in thiscase, a maximum RSENSE of:RSENSE 0.085mAh 216 50mΩQBATIn an example application where the maximum current isIMAX 100mA, calculating RSENSE 50mV/IMAX wouldlead to a sense resistor of 500mΩ. This gives a qLSB of8.5µAh and the accumulated charge register can representa maximum battery capacity of QBAT 8.5µAh 65535 557mAh. If the battery capacity is larger, RSENSE must belowered. For example, RSENSE must be reduced to 150mΩif a battery with a capacity of 1800mAh is used.2942fa10

LTC2942Applications InformationChoosing Coulomb Counter Prescaler M B[5:3]If the battery capacity (QBAT) is very small compared tothe maximum current (IMAX) (QBAT IMAX 0.1 Hours)the prescaler value M should be changed from its defaultvalue (128).In these applications with a small battery but a highmaximum current, qLSB can get quite large with respectto the battery capacity. For example, if the battery capacityis 100mAh and the maximum current is 1A, the standardequation leads to choosing a sense resistor value of50mΩ, resulting in:qLSB 0.085mAh 306mCThe battery capacity then corresponds to only 1176 qLSBsand less than 2% of the accumulated charge register isutilized.To preserve digital resolution in this case, the LTC2942includes a programmable prescaler. Lowering the prescaler factor M allows reducing qLSB to better match theaccumulated charge register to the capacity of the battery.The prescaling factor M can be chosen between 1 and itsdefault value 128. The charge LSB then becomes:qLSB 0.085mAh 50mΩ M RSENSE 128Note that the internal digital resolution of the coulombcounter is higher than indicated by qLSB. The digitizedcharge qINTERNAL is M 8 times smaller than qLSB. qINTERNALis typically 299µAs for a 50mΩ sense resistor.ADC Mode B[7:6]The LTC2942 features an ADC which measures eithervoltage on SENSE– (battery voltage) or temperature viaan internal temperature sensor. The reference voltage andclock for the ADC are generated internally.The ADC has four different modes of operation, as shownin Table 3. These modes are controlled by bits B[7:6] ofthe control register. At power-up, bits B[7:6] are set to[00] and the ADC is in sleep mode.A single voltage conversion is initiated by setting the bitsB[7:6] to [10]. A single temperature conversion is startedby setting bits B[7:6] to [01]. After a single voltage ortemperature conversion, the ADC resets B[7:6] to [00]and goes to sleep.The LTC2942 also offers an automatic scan mode wherethe ADC converts voltage, then temperature, then sleepsfor approximately two seconds before repeating the voltageand temperature conversions. The LTC2942 is set to thisautomatic mode by setting B[7:6] to [11] and stays in thismode until B[7:6] are reprogrammed by the host.To use as much of the range of the accumulated chargeregister as possible the prescaler factor M should bechosen for a given battery capacity QBAT and a senseresistor RSENSE as:Programming B[7:6] to [00] puts the ADC to sleep. Ifcontrol bits B[7:6] change within a conversion, the ADCwill complete the current conversion before entering thenewly selected mode.RSENSE 0.085mAh 50mΩM can be set to 1, 2, 4, 8, 128 by programming B[5:3] ofthe control register as M 2(4 B[5] 2 B[4] B[3]). The defaultvalue after power up is M 128 27 (B[5:3] 111).A conversion of either voltage or temperature requires 10msconversion time (typical). At the end of each conversion,the corresponding registers are updated. If the convertedquantity exceeds the values programmed in the thresholdregisters, a flag is set in the status register and the AL/CCpin is pulled low (if alert mode is enabled).In the above example of a 100mAh battery and an RSENSEof 50mΩ, the prescaler should be programmed to M 4.The qLSB then becomes 2.656µAh and the battery capacitycorresponds to roughly 37650 qLSBs.During a voltage conversion, the SENSE– pin is connectedthrough a small resistor to a sampling circuit with anequivalent resistance of 2MΩ, leading to a mean inputcurrent of I VSENSE–/2MΩ.M 128 162QBAT 2942fa11

LTC2942Applications InformationAccumulated Charge Register (C, D)The coulomb counter of the LTC2942 integrates currentthrough the sense resistor. The result of this charge integration is stored in the 16-bit accumulated charge register(registers C, D). As the LTC2942 does not know the actualbattery status at power-up, the accumulated charge register(ACR) is set to mid-scale (7FFFh). If the host knows thestatus of the battery, the accumulated charge (C[7:0]D[7:0])can be either programmed to the correct value via I2C orit can be set after charging to FFFFh (full) by pulling theAL/CC pin high if charge complete mode is enabled viabits B[2:1]. Before writing the accumulated charge registers, the analog section should be shut down by settingB[0] to 1. In order to avoid a change in the accumulatedcharge registers between reading MSBs C[7:0] and LSBsD[7:0], it is recommended to read them sequentially, asshown in Figure 10.Voltage and Temperature Registers (I, J), (M, N)The result of the 14-bit ADC conversion of the voltage atSENSE– is stored in the voltage registers (I, J), whereasthe temperature measurement result is stored in the temperature registers (M, N). The voltage and temperatureregisters are read only.As the ADC resolution is 14-bit in voltage mode and 10-bitin temperature mode, the lowest two bits of the combinedvoltage registers (I, J) and the lowest six bits of thecombined temperature registers (M, N) are always zero.From the result of the 16-bit voltage registers I[7:0]J[7:0]the measured voltage can be calculated as:VSENSE – 6V RESULTDECRESULTh 6V FFFFh65535Example: a register value of I[7:0] B0h and J[7:0] 1Chcorresponds to a voltage on SENSE– of:45084DECB01ChVSENSE – 6 V 6V 4.12776V65535FFFFhThe actual temperature can be obtained from the two byteregister C[7:0]D[7:0] by:T 600K RESULTDECRESULTh 600K FFFFh65535Example: a register value of C[7:0] 80h D[7:0] 00hcorresponds to 300K or 27 C.Threshold Registers (E, F, G, H, K, L, O, P)For each of the measured quantities (battery charge, voltage and temperature) the LTC2942 features a high and alow threshold registers. At power-up, the high thresholdsare set to FFFFh while the low thresholds are set to 0000h.All thresholds can be programmed to a desired value viaI2C. As soon as a measured quantity exceeds the highthreshold or falls below the low threshold, the LTC2942sets the corresponding flag in the status register andpulls the AL/CC pin low if alert mode is enabled via bitsB[2:1]. Note that the voltage and temperature thresholdregisters are single-byte registers and only the 8 MSBs ofthe corresponding quantity are checked. To set a low levelthreshold for the battery voltage of 3V, register L shouldbe programmed to 80h; a high temperature limit of 60 Cis programmed by setting register O to 8Eh.I2C ProtocolThe LTC2942 uses an I2C/SMBus compatible 2-wire opendrain interface supporting multiple devices and masterson a single bus. The connected devices can only pull thebus wires LOW and they never drive the bus HIGH. Thebus wires must be externally connected to a positive supply voltage via a current source or pull-up resistor. Whenthe bus is idle, both SDA and SCL are HIGH. Data on theI2C bus can be transferred at rates of up to 100kbit/s instandard mode and up to 400kbit/s in fast mode.Each device on the I2C/SMBus is recognized by a uniqueaddress stored in that device and can operate as either atransmitter or receiver, depending on the function of thedevice. In addition to transmitters and receivers, devicescan also be classified as masters or slaves when performing data transfers. A master is the device which initiates adata transfer on the bus and generates the clock signalsto permit that transfer. At the same time any device ad2942fa12

LTC2942Applications Informationdressed is considered a slave. The LTC2942 always actsas a slave.Figure 3 shows an overview of the data transmission forfast and standard mode on the I2C bus.START and STOP ConditionsWhen the bus is idle, both SCL and SDA must be HIGH. Abus master signals the beginning of a transmission with aSTART condition by transitioning SDA from HIGH to LOWwhile SCL is HIGH. When the master has finished communicating with the slave, it issues a STOP condition bytransitioning SDA from LOW to HIGH while SCL is HIGH.The bus is then free for another transmission. Whenthe bus is in use, it stays busy if a repeated START (Sr)is generated instead of a STOP condition. The repeatedSTART (Sr) conditions are functionally identical to theSTART (S).Data TransmissionAfter a START condition, the I2C bus is considered busyand data transfer begins between a master and a slave.As data is transferred over I2C in groups of nine bits(eight data bits followed by an acknowledge bit), eachSDAa6 - a0SCL1-789ADDRESSR/WACKgroup takes nine SCL cycles. The transmitter releasesthe SDA line during the acknowledge clock pulse and thereceiver issues an acknowledge (ACK) by pulling SDALOW or leaves SDA HIGH to indicate a not acknowledge(NACK) condition. Change of data state can only happenwhile SCL is LOW.Write ProtocolThe master begins a write operation with a START condition followed by the seven bit slave address 1100100and the R/W bit set to zero, as shown in Figure 4. TheLTC2942 acknowledges this by pulling SDA LOW andthen the master sends a command byte which indicateswhich internal register the master is to write. The LTC2942acknowledges and latches the command byte into itsinternal register address pointer. The master delivers thedata byte, the LTC2942 acknowledges once more andlatches the data into the desired register. The transmissionis ended when the master sends a STOP condition. If themaster continue

voltage and chip temperature in handheld PC and portable product applications. Its operating range is perfectly suited for single-cell Li-Ion batteries. A precision coulomb counter integrates current through a sense resistor between the battery's positive terminal and the load or charger. Battery voltage and on-chip temperature are measured .