Transcription
10G/25G High SpeedEthernet Subsystem v3.3Product GuideVivado Design SuitePG210 (v3.3) December 16, 2020
Table of ContentsChapter 1: Introduction. 5Features. 5IP Facts .6Chapter 2: Overview.7Navigating Content by Design Process. 7Subsystem Overview.7Feature Summary. 8Applications.11Licensing and Ordering. 11Chapter 3: Product Specification. 14Standards. 16Performance and Resource Utilization.16Latency.17Port Descriptions – MAC PCS Variant.17Port Descriptions – PCS Variant.44Port Descriptions – 10G Ethernet MAC (64-bit) Variant. 49Register Space. 63Chapter 4: Designing with the Subsystem. 120Clocking. 120Resets.127LogiCORE Example Design Clocking and Resets.128Support for IEEE Standard 1588v2. 132RS-FEC Support. 142Ethernet Datapath Parity .145802.1cm Preemption Feature.146Status/Control Interface.151Pause Processing. 152Auto-Negotiation.156Link Training. 159PG210 (v3.3) December 16, 202010G/25G High Speed EthernetSend Feedbackwww.xilinx.com2
Chapter 5: Design Flow Steps.164Customizing and Generating the Subsystem. 164Constraining the Subsystem.173Simulation. 174Synthesis and Implementation. 176Chapter 6: Example Design. 177Overview.177Example Design Hierarchy (GT in Example Design). 180User Interface. 184Core xci Top Level Port List. 186Duplex Mode of Operation. 229Runtime Switchable. 229Shared Logic Implementation. 231AXI4-Lite Interface Implementation. 233IEEE Clause 108 (RS-FEC) Integration. 238PTP 1588 Timer Syncer IP. 239Chapter 7: Batch Mode Test Bench. 252Appendix A: Upgrading. 253Changes from v2.3 to v2.4.253Changes from v2.3 (10/04/2017) to v2.3 (12/20/2017). 255Changes from v2.2 to v2.3.256Changes from v2.1 to v2.2.257Changes from v2.0 to v2.1.257Changes from v2.0 (10/05/2016) to v2.0 (11/30/2016) version. 259Migrating from the Legacy XGEMAC. 263Appendix B: Debugging.275Finding Help on Xilinx.com. 275Debug Tools. 276Simulation Debug.277Hardware Debug. 280Protocol Interface Debug.283Appendix C: Additional Resources and Legal Notices. 288Xilinx Resources.288PG210 (v3.3) December 16, 202010G/25G High Speed EthernetSend Feedbackwww.xilinx.com3
Documentation Navigator and Design Hubs. 288References.289Revision History. 289Please Read: Important Legal Notices. 296PG210 (v3.3) December 16, 202010G/25G High Speed EthernetSend Feedbackwww.xilinx.com4
Chapter 1: IntroductionChapter 1Introduction The Xilinx 10G/25G High Speed Ethernet Subsystem implements the 25G Ethernet MediaAccess Controller (MAC) with a Physical Coding Sublayer (PCS) as specified by the 25G EthernetConsortium. MAC and physical coding sublayer/physical medium attachment (PCS/ PMA) orPCS/PMA alone are available. Legacy operation at 10 Gb/s is supported.Features Designed to the Ethernet requirements for 10/25 Gb/s operation specified by IEEE 802.3Clause 49, IEEE 802.3 by, and the 25G Ethernet Consortium Includes complete Ethernet MAC and PCS/PMA functions or standalone PCS/PMA for 25Gb/s operation Includes complete Ethernet MAC and PCS/PMA functions, standalone MAC or standalonePCS/PMA for 10 Gb/s operation. Includes standalone 64-bit Ethernet MAC Simple packet-oriented user interface Comprehensive statistics gathering Status signals for all major functional indicators Delivered with a top-level wrapper including functional transceiver wrapper, IP netlist, sampletest scripts, and Vivado Design Suite tools compile scripts BASE-R PCS sublayer operating at 10.3125 Gb/s or 25.78125 Gb/s Optional clause 74 BASE-KR FEC sublayer Optional Auto-Negotiation/Link Training Optional clause 108 25G Reed-Solomon Forward Error Correction (RS-FEC) sublayer (Soft RS-FEC TX, Hard RS-FEC RX option toreduce logic utilization by leveraging the embedded 100G RS-FEC function that exists withinthe CMAC block in UltraScale devices). Custom Preamble mode Optional IEEE 1588 1-step and 2-step timestamping Runtime switchable between 10G and 25GPG210 (v3.3) December 16, 202010G/25G High Speed EthernetSend Feedbackwww.xilinx.com5
Chapter 1: Introduction Optional fee-based Time Sensitive Networking (TSN) feature designed to IEEE standard 802.1CM Supports interspersing express traffic with low priority traffic Supports frame preemptionIP FactsFacts TableSubsystem SpecificsSupported DeviceFamily1Versal ACAPZynq UltraScale RFSoCZynq UltraScale MPSoCVirtex UltraScale Kintex UltraScale Virtex UltraScale Kintex UltraScaleSupported User InterfacesAXI4-Stream for variants with MACXGMII or 25GMII for PCS-only variantsResourcesPerformance and Resource Utilization web pageDesign FilesEncrypted register transfer level (RTL)Example DesignVerilogTest BenchVerilogConstraints FileXilinx Design Constraints (XDC)Simulation ModelVerilogSupported S/W DriverLinuxProvided with SubsystemTested Design Flows2Design EntryVivado Design SuiteSimulationFor supported simulators, see the Xilinx Design Tools: Release Notes Guide.SynthesisSynopsys or Vivado SynthesisSupportRelease Notes and Known IssuesMaster Answer Record: 64710All Vivado IP Change LogsMaster Vivado IP Change Logs: 72775Xilinx Support web pageNotes:1.For a complete list of supported devices, see the Vivado IP catalog.2.For the supported versions of third-party tools, see the Xilinx Design Tools: Release Notes Guide.Note: To access the 25G specification, go to the 25G Ethernet Consortium website.PG210 (v3.3) December 16, 202010G/25G High Speed EthernetSend Feedbackwww.xilinx.com6
Chapter 2: OverviewChapter 2OverviewNavigating Content by Design Process Xilinx documentation is organized around a set of standard design processes to help you findrelevant content for your current development task. This document covers the following designprocesses: Hardware, IP, and Platform Development: Creating the PL IP blocks for the hardwareplatform, creating PL kernels, subsystem functional simulation, and evaluating the Vivado timing, resource use, and power closure. Also involves developing the hardware platform forsystem integration. Topics in this document that apply to this design process include: Port Descriptions Port Descriptions – MAC PCS Variant Port Descriptions – PCS Variant Port Descriptions – 10G Ethernet MAC (64-bit) Variant Register Space Clocking Resets Customizing and Generating the Subsystem Chapter 6: Example DesignSubsystem OverviewThis document details the features of the 10G/25G Ethernet Subsystem as defined by the 25GEthernet Consortium. PCS functionality is defined by IEEE Standard 802.3, 2015, Clause 49,Physical Coding Sublayer (PCS) for 64B/66B, type 10GBASE-R. For 25G operation, clockfrequencies are increased to provide a serial interface operating at 25.78125 Gb/s to leveragethe latest high-speed serial transceivers. The low latency design is optimized for UltraScale architecture devices.PG210 (v3.3) December 16, 202010G/25G High Speed EthernetSend Feedbackwww.xilinx.com7
Chapter 2: OverviewFeature SummarySee the following table for compatibility of options with the different variants of the LogiCORE IPsubsystem.25G Supported Features Complete Ethernet MAC and PCS functions Designed to Schedule 3 of the 25G Consortium Statistics and diagnostics 66-bit serializer/deserializer (SerDes) interface using the Xilinx GTY transceiver operatingwith Asynchronous Gearbox enabled Pause Processing including IEEE std. 802.3 Annex 31D (Priority based Flow Control) Low latency Custom preamble and adjustable Inter Frame Gap Configurable for operation at 10.3125 Gb/s (Clause 49) Optional Clause 73 Auto-negotiation Optional Clause 72.6.1
Ethernet Consortium. PCS functionality is defined by IEEE Standard 802.3, 2015, Clause 49, Physical Coding Sublayer (PCS) for 64B/66B, type 10GBASE-R. For 25G operation, clock frequencies are increased to provide a serial interface operating at 25.78125 Gb/s to leverage the latest high-speed serial transceivers. The low latency design is .
