EVALUATION, OPTIMIZATION, AND RELIABILITY OF NO-FLOW UNDERFILL . - Engent

Transcription

EVALUATION, OPTIMIZATION, AND RELIABILITY OFNO-FLOW UNDERFILL PROCESSMichael ColellaAdvanced Assembly Process Technology LaboratoryPackaging Research CenterGeorgia Institute of TechnologyAtlanta, GA, USADaniel Baldwin, Ph.D.Engent, Inc. – Enabling Next Generation TechnologiesNorcross, GA, USAdan.baldwin@engentaat.comABSTRACTThe advent of no-flow fluxing underfills for Flip Chip onBoard application has required a new investigation ofoptimal processing for increased reliability. This researchprovides a systematic development of optimal processparameters for four commercially available fluxingunderfills. The impact of the dispensing pattern on voidformation is determined. DOE1 includes dispense pattern at3 levels, and speed at 2 levels. Metrics include yield,material voiding, and fillet shape. Low temperature cure isused to isolate the effects of dispensing by avoiding anyvolatility of a standard reflow cure. The impact of theplacement process is determined in a second experiment,DOE2, involving placement force, speed, and dwell time at2 levels. Metrics include yield, underfill voiding, soldervoiding, and electrical yield. The results of theseexperimental studies are used to select an optimal placementprocess for each material. Reflow parameters areinvestigated using a parametric approach. The followingparameters are varied at 2 levels individually off a baselineprofile: Peak Temperature, Time 183 C, Peak Ramp Rate,Soak Time, and Soak Temperature. The results of theseinitial studies will be used to choose an optimal process foreach material. Test boards were assembled according to theoptimal process for each material, and AATC thermalcycling test was performed.Key Words: Underfill, Flip Chip, Process OptimizationINTRODUCTIONUnderfills are typically used in flip chip packaging to helpmitigate the effects of the large Coefficient of ThermalExpansion (CTE) mismatch between the silicon chip and thelaminate circuit board. The underfill acts to reduce the strainon the solder joints resulting in improved interconnectfatigue life [1].The capillary flow underfill process involves fluxing,placing, and reflowing the flip chip first, and thendispensing the underfill along the sides of the chip. Theunderfill flows by capillary action to fill the area underneaththe chip. Finally, a cure must be completed in an oven.No-flow underfill processing utilizes fluxing underfills thatare dispensed onto the substrate before placement. The dieis then placed onto the dispensed underfill causing squeezeflow of the material during placement. The assembly is thenreflowed and cured simultaneously in a standard reflowoven [2].This paper presents a systematic optimization of theplacement and reflow parameters for a no-flow processusing four commercially available underfill materials.EXPERIMENTAL METHODOLOGYFour types of no-flow underfill materials were investigated:Underfill A, B, C, and D. One test vehicle was used for allassemblies. Prior to assembly the boards were baked out at125 ºC for 3 hours. This bakeout time was determined froma previous bakeout experiment, and was sufficient to avoidoutgassing of the boards. The boards were stored in adesiccant chamber after bakeout, for no more than 2 hoursbefore assembly. Test vehicles for each experiment wereassembled according to the procedures outlined later in theassembly process section. After assembly, the boards wereanalyzed using acoustic microscopy, x-ray, cross sectioning,and SEM.Test Vehicle DescriptionThe test vehicle consisted of an area array die mounted on aFR-4 substrate with six sites. The test die were supplied byFlip Chip Technologies and had daisy chain structures. Thedie were area array FA10-200x200 with 10 mil pitch. Thetrace metallization on the boards was copper, electroplatednickel, and immersion gold. The bond pads were hybridhaving two sides mask defined and two sides pad defined.There are probe points on the substrates that allowcontinuity testing of the rows of interconnects. Duringcontinuity testing the row was considered failed if the loop

resistance deviated by more than 10% from the baselineresistance.Assembly Process (DOE1)Dispensing was done with an Asymtek millennium using a22-gauge needle. Placement was done with a Siemens F5Siplace for speed 1 (70 mm/s), and a K&S 6900 for speed 2(5 mm/s). Both machines were calibrated for force andspeed using a high-speed camera prior to running theexperiment. The force used during DOE1 was 5N. Thedwell time used was 0.10 seconds.Boards were assembled according to the design matrixshown in Figure 1, for each underfill A, B, C, and D.Dispense patterns are shown in Figure 2. Each row of thematrix corresponds to one treatment in the DOE; fourreplicates were assembled for each treatment. The targetdispense weight was 8 mg; actual dispense weight variedbetween 7.5 mg and 8.5 mg. The assemblies were lowtemperature cured at 130 ºC for 1 hour in an oven. Thetemperature was chosen to avoid reflow and any materialvolatility so that the effects of the factors included in theDOE could be studied in relative isolation from the reflowprocess.Underfill A, B, C, DPatternSpeed(mm/s)11 dot7012 dot521 line7022 line531 cross7032 cross5Figure 1. DOE1 Design MatrixDotLineanalysis. Response was reported in number of voids, ratherthan in % area. This technique can be expected to yieldaccurate data for comparison, because all the voids wereroughly the same size, and most parts had many voids( 100) so that any differences in size can be expected toaverage out. JMP software was used to perform thestatistical analysis.Assembly Process (DOE2)For each material, a full factorial DOE was used with threevariables. Based on the results of the DOE1, dispensepattern was included with 2 levels: dot and line. Placementforce was included at 2 levels: 1N and 5N. Dwell time wasincluded at 2 levels: 0 and 0.1 seconds. All treatments wereperformed in replicates of 4. Interconnect yield percent wasthe primary metric; void area and fillet shape serve as asecondary metrics. Based on these experimental results, anoptimal placement process for each material will be selectedfor further reflow profile experimentation.Dispensing was done with a CAMALOT 3300 dispenserusing a 22-gauge needle, due to the removal of the Asymtekmillennium machine from the laboratory. Placement wasdone with a Siemens F5 Siplace. Reflow was accomplishedusing a BTU 7-zone reflow oven.Boards were assembled according to the design matrixshown in table 2, for each underfill A, B, C, and D. Eachrow of the matrix corresponds to one treatment in the DOE;four replicates were assembled for each treatment. Thetarget dispense weight was 8 mg; actual dispense weightvaried between 7.5 mg and 8.5 mg. The assemblies werereflowed according to a baseline process; the reflow profileswere designed based on the material suppliersrecommendations and were determined to yield 100%reliably when using both the dot or line pattern with force of5N and .5 seconds dwell.CrossFigure 2. Underfill dispense patternsAfter curing the boards were scanned using acousticmicroscopy (CSAM) to identify voids. The captured imageswere analyzed with digital image analysis (DIA) software toobtain voiding reported in % area. After all the parts werescanned, they were then planar cross-sectioned and viewedoptically under a microscope to determine if the CSAMimage analysis was adequate for data analysis. For eachunderfill the CSAM images do not show many of the voidsthat are clearly present under microscope inspection aftercross sectioning. Therefore, a manual count of the voidsvisible by optical microscope was used for statistical111112121122211212221222Underfill A, B, C, DPatternForce (N)dot1dot1dot5dot5line1line1line5line5Dwell (s)00.100.100.100.1Figure 3. DOE2 Design MatrixAfter the boards were assembled according to theparameters in Figure 3, electrical continuity tests wereperformed to determine the percent interconnect yield. Theboards were then scanned using acoustic microscopy(CSAM) to identify voids. The captured images wereanalyzed with digital image analysis (DIA) software to

obtain voiding reported in percent of total die area. Theresults were analyzed using JMP statistical software withpercent voiding as the response.value, while keeping all other parameters at or near theirbaseline value, see Figure 6.Temp ( C)Reflow StudyThere are two distinct types of reflow profiles that wereutilized in this experimental work; these types are describedas either a step (Figure 4) or a ramp profile (Figure 5).Temp ( C)HighRamp Rate BaselineLowHighSoak Temp BaselineRamp Rate ( C/s)LowPeak Temp183Soak TempTime (s)Figure 6. Reflow Profile VariationTime (s)Soak TimeTime above 183CFigure 4. Step profileFor the step profile this hi/low variation produces 2 profilesfor each reflow parameter shown in Figure 4, for a total of10 distinct profiles for analysis. The ramp profile produces 8profiles, 2 from each of the 4 parameters shown in Figure 5.Replicates of 4 die were assembled for each reflow profile,using the optimal dispense process from DOE1 and DOE2.For each reflow profile, die were assembled in replicates of4.Temp ( C)RESULTSRamp Rate ( C/s)Peak Temp183 CTime (s)Time above183 CTime to PeakFigure 5. Ramp profileThere were two main goals of this experiment: to determinethe optimal reflow profile for each material, and to define areflow process window for each material. The experimentaldesign was chosen to be a parametric study due tolimitations on time and materials, as the requirements for afull factorial DOE would have been excessive.A baseline reflow profile was developed for each materialbased on the manufacturers suggested profile. This profilewas validated by placing 4 die and sending the assemblythrough reflow. The assemblies were then checked forcontinuity by resistance measurement. After a baselineprofile was established, new profiles were generated byvarying each of the profile parameters individually by anamount higher or lower than that of the baseline parameterDOE1ANOVA shows very low p-values ( .001) for pattern,observed for all three underfills, indicating that dispensepattern is a significant factor affecting the number of voidsoccurring during placement. The Mean response for dot,line, and cross patterns was 141.3 voids, 3.7 voids, and 126voids respectively. It seems likely that the capillary flowprocess associated with the line pattern is better at filling thesolder mask openings without capturing voids during theprocess. The dot and cross patterns result in squeeze flowthat has a tendency to capture voids during the rapid flow ofthe material. Line pattern was chosen to be included inDOE2 because it resulted in minimal voiding. The dotpattern was chosen instead of the cross pattern because themean response was similar and the dot pattern is faster forultimate use in a production process.

Figure 7. Underfill A, dot, speed 5 mm/s. Underfillvoiding can be seen easilySpeed is a factor at .10 significance level for Underfill Aand B. The difference in mean response for speed 1 andspeed 2 was only about 20%. The relatively high p-valueand the small difference in mean response led us toeliminate speed as a significant factor for furtherexperiments.DOE2The only interconnect failures observed were for the 111treatment (dot, 1N, 0 s). All materials show similarcharacteristics with respect to interconnect yield. All threeplacement parameters affect the response. The line patternresulted in 100% yield for all materials regardless of theforce or dwell used. This is interpreted as due to therelatively small force resulting from die placement onto theline pattern, rather than the full force from squeeze flowunder the usual dot pattern placement. The F5 placementmachine triggers the onset of dwell time after reaching thecritical force of placement, and then after the dwell time hascompleted the chip is released. The line pattern evidentlyresults in a placement force small enough that even with themachine dialed to 1N and no dwell time, the chiprelease is not triggered until the chip meets the board. Whenusing the dot pattern with minimum force and no dwell, thedie release must happen above the substrate resulting inmisalignment after reflow and therefore a low percentinterconnect yield. X-ray confirmed misalignment of thoseassembles that failed continuity testing.ReflowA material ranking was developed for each material basedon the observable metrics: yield, underfill material voiding,resitance, and a grain size ratio. Data was collected for eachmaterial, an example is shown in Figure 9.Material CB a s e lin eVoidingResistanceGrain(% area)(Ω)( ra tio )Ranking1 .0 51 .7 0 70 .0 3 70 .4 6 2R rh ig h0 .8 2 81 .7 1 40 .0 4 30 .4 3 7R rlo w0 .6 7 51 .7 1 30 .0 4 40 .4 8 0S kTe m phi0 .4 9 31 .6 7 60 .0 3 30 .8 1 9S k T e m p lo w0 .8 6 31 .6 7 70 .0 2 80 .7 4 6S k T im e h i0 .5 5 81 .7 1 10 .0 3 90 .5 7 3S k T im e lo w1 .0 8 51 .7 2 60 .0 5 30 .2 0 7T 1 8 3 h ig h0 .2 71 .6 8 00 .0 4 20 .7 8 2T 1 8 3 lo w0 .6 81 .7 0 50 .0 5 90 .3 7 3P kTe m phi0 .7 4 31 .6 7 40 .0 4 20 .6 6 0P k T e m p lo w1 .5 5 31 .6 6 20 .0 3 80 .5 0 1O p tim a l0 .1 7 81 .7 2 80 .0 30 .7 0 0Figure 9. Material Ranking Data for ReflowOptimizationFigure 8. Underfill B, line, 70mm/sA weighted ranking system was chosen to place 40 percentweight on the underfill voiding data, and 30 percent each onthe resistance and grain ratio data. The data for eachmaterial was scaled using the high and low values from eachmetric. This is shown in the following equation:

Rank 0.4(Vhi V )Vhi Vlow 0.3(Rhi R )Rhi Rlow 0.3(Ghi G )Ghi GlowWhere:V Voiding area as a percentageR Electrical resistanceG Grain ratioThe voiding percent area was determined using the DIAsoftware as in DOE1 and DOE2. The resistance data wastaken by adding the resistance measurements fromindividual trace measurements for each die.The grain data was determined using an area ratiotechnique, where a grid was overlaid onto SEM images andthe ratio of points was calculated that fell inside of the largegrain boundaries. See Figures 10 & 11.The ranking in the provided ‘Rank’ equation gives aweighted score from 0 to 1, with the higher numbercorresponding to low values of voiding, resistance, andgrain ratio.For each material, the highest ranking profile was selectedfor use in the final reliability build of 30 replicates.ReliabilityA total of 120 samples, 4 underfill materials with 30replicates each, have been subjected to air-air temperaturecycle testing. The temperature cycle test ranged from -40 Cto 125 C with 12 minute dwells at each temperatureextreme. Assemblies built for final reliability testing havecompleted 2000 cycles thus far without an electrical failure.The parts will continue cycling in order to obtain failuredata.CONCLUSIONA near void free no flow underfill dispense process wasdeveloped including a novel ranking methodology forimproved reflow process characterization. Test vehiclesproduced with this process have exhibited superiorreliability performance – 2000 temperature cycles withoutan electrical failure.ACKNOWLEDGEMENTThe authors would like to thank the Georgia Tech Center forBoard Assembly Research and Siemens AG for supportingthis work.Figure 10. SEM Image of a cross section to be used forgrain ratio analysis.Figure 11. SEM Image with grain boundaries and apartial grid overlay.REFERENCES[1]. John H. Lau, Flip Chip Technologies, McGraw-Hill,1996.[2]. Ryan Thorpe and Daniel Baldwin Ph.D., “HighThroughput Flip Chip Processing and Reliability AnalysisUsing No-Flow Underfills” , 1999 Electronic Componentsand Technology Conference.

The capillary flow underfill process involves fluxing, placing, and reflowing the flip chip first, and then dispensing the underfill along the sides of the chip. The underfill flows by capillary action to fill the area underneath the chip. Finally, a cure must be completed in an oven.