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ConfidentialA Complete Reliability Solution: ReliabilityModeling, Applications, and Integration inAnalog Design EnvironmentTianlei Guo, Jushan XieCadence Design Systems, Inc.June 19, 2018

Project VisionDesign for ReliabilityFailure is NOT an Option Make reliability analysis relevant by providing– Predictive aging models– Aging analysis accelerated by temperature, process variation, – Support mission profiles2 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.

Simulating Device Aging3 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.

Terminology for Device Reliability Analysis Age– Device age is a parameter that represents the device degradation physicalphenomena Age (or lifetime or degradation) model– Predicts the degradation in device characteristics due to a physicalphenomena, such as HCI, NBTI, PBTI, TDDB, Aged (or degraded) model– is a device SPICE model that represents the effects of all kind ofdegradations at particular future time value Fresh Simulation– Is a simulation without degradation or a simulation at time 0 Stress Simulation– Is a simulation that represents the stress condition Aging (or EOL) simulation– is a simulation with worst case device degradation due to electrical stress, asimulation at the end of life4 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.

HCI (Hot Carrier Injection)Ben Kaczer, 2016 IEDM tutorial5 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.

BTI (Bias Temperature Instability)NBTI: NMOS BTIPBTI: PMOS BTI strong6 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.

TDDB (Time-Dependent Dielectric Breakdown)Ben Kaczer, 2016 IEDM tutorial7 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.

Cadence Aging Reliability Support8 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.

Aging Analysis in Spectre9 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.

Aging Reliability AnalysisHCI and NBTI/PBTI Analysis FlowCircuitNetlist ReliabilityModelFreshFresh SimulationStressDevice Degradation, LifetimeStressingAgingAging/EOLDegraded model/netlistGenerationAging SimulationWaveform CompareCircuit degradation Check10 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.

Reliability Models supported Reliability effects supported:– Built-in HCI, NBTI and PBTI– other mechanisms possible via URI (eg. TDDB, GOI) SPICE Models supported for degradation:– BSIM3, BSIM3V3, BSIM4, BSIMSOI, MOS9, MOS11, PSP 102, PSP 103,HVMOS, HISIM2 and HISIM HV.– BSIMCMG, BSIMIMG, UTSOI, UTSOI2– BJT: VBIC, HiCUM and MEXTRAM– Resistor: native and R3– Diode– Verilog-A Reliability models:– ageMOS: Cadence proprietary reliability model for HCI, NBTI and PBTI (withrecovery) and degraded model generation (for legacy nodes).– ageMOS2: Cadence proprietary reliability model for advance nodes.– URI: API to allow customer implement own reliability models.– TMI-aging, TMI self-heating models, TMI TDDB11 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.

Virtuoso Unified Reliability Interface (URI)Using Custom Reliability Models The Virtuoso Unified Reliability Interface (URI) allows you to add yourown (custom/proprietary) reliability equations/models and supportsuser-defined degradation modelsC codeCustom/Proprietaryreliability equationsURINetlist with yourown reliabilitymodel12RelXpertSpectre APS/XPS 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.ReliabilitySimulationResults

TMI Simulation flow TMI Aging model offered three simulation flows with .option tmiAge 1– Aging only simulation flow. (tmishe 0)– Aging stress w/o self-heating effect ( calculate degradation rates under TempE )– Measurement simulation w/o self-heating effect.– Self-Heating only simulation flow. (tmishe 1)– w/o aging stress.– Measurement simulation w/i self-heating effect.– Aging simulation with self-heating effect. (tmishe 2)– Aging stress w/i self-heating effect ( calculate degradation rates underTempE dtemperature ).– Measurement simulation either w/i or w/o self-heating effect.13tmiSheSelf-heatingaging0-Yes1Yes-2YesYes 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.default

Spectre/TMI interface in ADE14 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.

Reliability models support matrixRelXpertSpectre NativeageMOSHCI, NBTI, PBTI, TDDB*XXageMOS2HCI, NBTI, PBTI, TDDB*XXExtractionX (verification)TMIHCI, BTI, TDDBXXURIRunningXXModel development, 3rd party spice XSelf-heatingMC-agingBuilt-in (bsimcmg, bsimimg)XXSpectre-SHEXXTMI-SHEXXageMOS, ageMOS2XTMIXTDDB*: prototype15 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.

New Aging Model16 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.

Model HCI Degradation Saturation EffectDegradationsaturationHCI (Vgs 1V)1.E-011.E-031.E-051.E-071.E-091.E-11Vds 0.8V1.E-131.E-081.E-061.E-041.E-021.E 001.E 021.2V1.E 041.6V1.E 061.E 08V. Huard, IEDM, 2007“New Generation Reliability Model”, S.-Y. Liao, C. Huang, T. Guo, A. Chen, Jushan Xie, Cadence Design Systems, Inc.S. Guo, R. Wang, Z. Yu, P. Hao, P. Ren, Y. Wang, R. Huang, Peking University, MOS-AK December 2016http://www.mos-ak.org/berkeley 2016/publications/T11 Xie MOS-AK Berkeley 2016.pdf17 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.

ConventionalRDmodel model A(b)1E-7 1E-5 1E-3 0.1Time(s)18(d)10 1000FinFET silicon dataNBTI recvoeryRDmodel model AConvertional(Power law)1E-7 1E-5 1E-3 0.1Time(s)(c)10 1000ConventionalTDmodel model B(Log law)1E-71E-51E-3 0.1 10 1000Time(s)Normalized ΔVTH (a.u.)Convertional model B(Log law)Normalized ΔVTH (a.u.)Normalized ΔVTH (a.u.)(a)(Power law)1E-71E-51E-3 0.1 10 1000Time(s)FinFET silicon dataNBTI recoveryFinFET silicon dataNBTI stress 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.FinFET silicon dataNBTI recoveryConvertionalTDmodel model B(Log law)1E-7 1E-5 1E-3 0.1Time(s)(d)Normalized ΔVTH (a.u.)FinFET silicon dataNBTI stressΔVTH(a.u.)ΔVTH(a.u.)Model limitation in FinFET BTI effect (log-log nonlinear)10 1000FinFET silicon dataNBTI recvoeryConvertional model A(Power law)1E-7 1E-5 1E-3 0.1Time(s)(c)10 1000

Model result demonstration – New BTI modelsNew model equations for FinFET: DC verification(a)NBTI stresslines: new modelsymbols: FinFET silicon dataVg -1.3V,-1.4V,-1.5V, -1.6VStressphaseSlope 22StageNBTI RecoveryVgs dep. 2Slope 1(a)Stage 2 (c)ΔVTH (a.u.)Stage 2Stage 1Stage 1ΔVTHTH (a.u.)(a.u.)ΔVStageStage1 1Stage 1StageStage2 (b) 2 (a)StageNBTI stressNBTI stressNBTIlines: new modellines: new modelsymbols: FinFET silicon datasymbols: FinFET silicon dataT 50 C,75Recovery C, 100 C, 125 C -1.6VphaseVg -1.3V,-1.4V,-1.5V,Stage22Stage1 1 StageStageSlope11StageΔVTH (a.u.)ΔVTH (a.u.)Stage 1Stage 1NBTI RecoveryNBTI recoveryStage 2 (b)(d)lines: new modelsymbols: FinFET siliT 50 C, 75 C, 100 C,StageNBTI r(c)NBTI stressSlope 2NBTI stressVgsdep.1T 50 C,75 C,T 50 C, 75 C,Vg 0V,Vgs-0.2V,Vg 0V, 100 C, -0.4V,125 C -0.6V1 model100 C, 125 Csymbols:FinFETsilicondatasymbols:FinFET silicon datalines:new modellines: newlines:modelnew modellines: new modelT 50 C,75 C,100 C,125 CVg ymbols: FinFET siliconVgs dep.1E-51E-30.1101000 1E-51E-51E-31E-3 0.1 0.1 10 10 10001000 1E-51E-30.1Stage 1TimeStage(s) 2Stage 1ΔVTH (a.u.)NBTI Recovery19StageTime(s) 2(s)TimeNBTI recovery Curve slope changed against time (in log-log, or log-lin scale)(c)changed Gate bias dependency(d)T 50 C, 75 C,Vg 0V, -0.2V,-0.4V, -0.6V100 C, 125 Clines: new modellines: new modelsymbols: FinFET silicon datasymbols: FinFET silicon data1E-51E-30.1101000 1E-51E-30.1101000 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.Time (s)Time (s)Time (s)

Model result demonstration – New BTI modelsHistory effect: sequential simulation stepVgs3Vgs1VgsstressStressphaseStress phaseVgs2RecoveryphaseTimeΔDeg020t1 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.t2t3Time

BTI model with recovery effect -New Model-1.6VDegradation [a. u.)-1.4V-1.2V-1VStress onlySimu. ResultVgs0V00.020.040.060.080.1Time [s]21 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.0.120.140.160.18

BTI model prediction with recovery effectTimeA periodic square waveform isapplied on an invertor during afew milliseconds.Then prediction for 3 years.2210-3 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.w/ recoverywo/ recoveryTypeOver-estimationin 3 yearsΔVTH (a.u.)Duty 50%ΔVTH (a.u.)VgsAType BIterated resultsDegradation resIteration step:@3yearsN 10(a)34105 10100 103 106 109 10 10Frequency(HzTime(s)

Comparison of AgeMOS and AgeMOS2AgeMOS§§§§§Developed around 1995Based on Lucky-Electron modelDegradation log-log linearMany enhancementsUsing skew parameters Vth, U0, Ua, Ub, Nfactor, Vsat, § Simple recovery model linear extrapolationAgeMOS2§ Developed around 2015§ Based on trapping/de-trappingmodel§ Degradation log-log nonlinear§ Degradation saturation/historyeffect§ Using degradation directly Vth and Ids degradation§ Recovery with step-wise model§ Current CMC Approach23 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only. More accurate Frequency dependency

AgeMos2 Model Extraction (Standalone tool)Grouped reliabilitycharacteristics, suchas degradation vs.time curves withvarying Vds for afixed temperature.Loading the data,and treating it forextractionpreparation, such assorting, regrouping,data checking, etc.DatacompleteYesFitting error reportcompared to theinput data, simulationresults in text files,graphically, etc.Specified reliabilitymodel parameterextractionOutput EDA readablereliability modelcard24 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.No

Reliability Monte Carlo25 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.

Reliability Variation 26 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.Agingvariation(AV)

Simulation Diagram for Flow I (1 N flow)(Aged model Process Variation))StressFreshMean transistorlevel simulationMean spice modelMean freshMean AgingcalculationsMean reliability modelMC RUNs:1 NMC AgingAged spice modelgenerationsDegradationPV transistorlevel simulation27variation Can perform Aging MC with current foundry aging MC model Not expensive 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.N

Simulation Diagram for Flow II (N N flow)(Age Variation Process Variation)MC StressMC FreshPV transistorlevel simulationPV spice modelAV agingcalculationsAV reliability modelMC RUNs:N NAged spice modelgenerationsPV transistor-levelsimulation28Freshvariation 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.NMC AgingDegradationvariationNN

VTH Comparison between Flow Zero, I and II100Flow IIFlow I8060Agedµ -0.487σ 0.0044Flow Zero& Flow IFlow Zero4020Freshµ -0.437σ 0.0045µ -0.487σ 0.01200-0.52-0.5-0.48-0.46-0.44-0.42VTH (V)Ø Variation distribution (Y-axis)Ø Variation of aged VTH of flow I (only PV) is smaller than flow II (PV AV)29 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.

Process Variation and Aging Variation CorrelationSpectre syntax for correlationanalysisØ Aged VTH and IDS variation become smaller after considering correlation betweenPV/AV30 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.

Scatter Points for Operation OutputsØ The scatter points between aged VTH and aged IDS, GM, GDS, ROUT, IGS, and VDSATØ The correlation between PV/AV makes the outputs correlation more complicated31 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.