Computer Organization And ArChiteCture Designing For Performance - Pearson

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Computer Organizationand ArchitectureDesigning for PerformanceNinth EditionWilliam StallingsBoston Columbus Indianapolis New York San Francisco Upper Saddle RiverAmsterdam Cape Town Dubai London Madrid Milan Munich Paris Montréal TorontoDelhi Mexico City São Paulo Sydney Hong Kong Seoul Singapore Taipei Tokyo 2013 Pearson Education, Inc., Upper Saddle River, NJ 07458. All Rights ReservedA01 STAL6330 09 SE FM.indd 12/2/12 3:11 AM

Editorial Director: Marcia HortonExecutive Editor: Tracy DunkelbergerAssociate Editor: Carole SnyderDirector of Marketing: Patrice JonesMarketing Manager: Yez AlayanMarketing Coordinator: Kathryn FerrantiMarketing Assistant: Emma SniderDirector of Production: Vince O’BrienManaging Editor: Jeff HolcombProduction Project Manager: Kayla Smith-TarboxProduction Editor: Pat BrownManufacturing Buyer: Pat BrownCreative Director: Jayne ConteDesigner: Bruce KenselaarManager, Visual Research: Karen SanatarManager, Rights and Permissions: Mike JoyceText Permission Coordinator: Jen RoachCover Art: Charles Bowman/Robert HardingLead Media Project Manager: Daniel SandinFull-Service Project Management: Shiny Rajesh/Integra Software Services Pvt. Ltd.Composition: Integra Software Services Pvt. Ltd.Printer/Binder: Edward BrothersCover Printer: Lehigh-Phoenix Color/HagerstownText Font: Times Ten-RomanCredits: Figure 2.14: reprinted with permission from The Computer Language Company, Inc. Figure 17.10:Buyya, Rajkumar, High-Performance Cluster Computing: Architectures and Systems, Vol I, 1st edition, 1999. Reprinted and Electronically reproduced by permission of Pearson Education, Inc. Upper SaddleRiver, New Jersey, Figure 17.11: Reprinted with permission from Ethernet Alliance.Credits and acknowledgments borrowed from other sources and reproduced, with permission, in thistextbook appear on the appropriate page within text.Copyright 2013, 2010, 2006 by Pearson Education, Inc., publishing as Prentice Hall. All rightsreserved. Manufactured in the United States of America. This publication is protected by Copyright,and permission should be obtained from the publisher prior to any prohibited reproduction, storage ina retrieval system, or transmission in any form or by any means, electronic, mechanical, photocopying,recording, or likewise. To obtain permission(s) to use material from this work, please submit a writtenrequest to Pearson Education, Inc., Permissions Department, One Lake Street, Upper Saddle River,New Jersey 07458, or you may fax your request to 201-236-3290.Many of the designations by manufacturers and sellers to distinguish their products are claimed astrademarks. Where those designations appear in this book, and the publisher was aware of a trademarkclaim, the designations have been printed in initial caps or all caps.Library of Congress Cataloging-in-Publication Data available upon request10 9 8 7 6 5 4 3 2 1ISBN 10: 0-13-293633-XISBN 13: 978-0-13-293633-0 2013 Pearson Education, Inc., Upper Saddle River, NJ 07458. All Rights ReservedA01 STAL6330 09 SE FM.indd 22/2/12 3:11 AM

To Tricia (ATS),my loving wife, the kindestand gentlest person 2013 Pearson Education, Inc., Upper Saddle River, NJ 07458. All Rights ReservedA01 STAL6330 09 SE FM.indd 32/2/12 3:11 AM

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ContentsOnline Resources xiPreface xiiiAbout the Author xxiChapter 0 Reader’s and Instructor’s Guide 10.1Outline of the Book 20.2A Roadmap for Readers and Instructors 20.3Why Study Computer Organization and Architecture? 30.4Internet and Web Resources 5Part One Overview 6Chapter 1 Introduction 61.1Organization and Architecture 71.2Structure and Function 81.3Key Terms and Review Questions 14Chapter 2 Computer Evolution and Performance 152.1A Brief History of Computers 162.2Designing for Performance 372.3Multicore, MICs, and GPGPUs 432.4The Evolution of the Intel x86 Architecture 442.5Embedded Systems and the Arm 452.6Performance Assessment 492.7Recommended Reading 592.8Key Terms, Review Questions, and Problems 60Part Two  The Computer System 65Chapter 3 A Top-Level View of Computer Functionand Interconnection 653.1Computer Components 663.2Computer Function 683.3Interconnection Structures 843.4Bus Interconnection 853.5Point-To-Point Interconnect 933.6PCI Express 983.7Recommended Reading 1083.8Key Terms, Review Questions, and Problems 108Chapter 4 Cache Memory 1124.1Computer Memory System Overview 1134.2Cache Memory Principles 1204.3Elements of Cache Design 123v 2013 Pearson Education, Inc., Upper Saddle River, NJ 07458. All Rights ReservedA01 STAL6330 09 SE FM.indd 52/2/12 3:11 AM

vi   Contents4.4Pentium 4 Cache Organization 1414.5Arm Cache Organization 1444.6Recommended Reading 1464.7Key Terms, Review Questions, and Problems 147Appendix 4A Performance Characteristics of Two-Level Memories 152Chapter 5 Internal Memory 1595.1Semiconductor Main Memory 1605.2Error Correction 1705.3Advanced Dram Organization 1745.4Recommended Reading 1805.5Key Terms, Review Questions, and Problems 181Chapter 6 External Memory 1856.1Magnetic Disk 1866.2Raid 1956.3Solid State Drives 2056.4Optical Memory 2106.5Magnetic Tape 2156.6Recommended Reading 2176.7Key Terms, Review Questions, and Problems 218Chapter 7 Input/Output 2217.1External Devices 2237.2I/O Modules 2267.3Programmed I/O 2287.4Interrupt-Driven I/O 2327.5Direct Memory Access 2407.6I/O Channels and Processors 2467.7The External Interface: Thunderbolt and Infiniband 2487.8IBM zEnterprise 196 I/O Structure 2567.9Recommended Reading 2607.10Key Terms, Review Questions, and Problems 260Chapter 8 Operating System Support 2658.1Operating System Overview 2668.2Scheduling 2778.3Memory Management 2838.4Pentium Memory Management 2948.5ARM Memory Management 2998.6Recommended Reading 3048.7Key Terms, Review Questions, and Problems 304Part three Arithmetic and Logic 309Chapter 9 Number Systems 3099.1The Decimal System 3109.2Positional Number Systems 3119.3The Binary System 3129.4Converting Between Binary and Decimal 312 2013 Pearson Education, Inc., Upper Saddle River, NJ 07458. All Rights ReservedA01 STAL6330 09 SE FM.indd 62/2/12 3:11 AM

Contents   vii9.5Hexadecimal Notation 3159.6Recommended Reading 3179.7Key Terms and Problems 317Chapter 10 Computer Arithmetic 31910.1The Arithmetic and Logic Unit 32010.2Integer Representation 32110.3Integer Arithmetic 32610.4Floating-Point Representation 34110.5Floating-Point Arithmetic 34910.6Recommended Reading 35810.7Key Terms, Review Questions, and Problems 359Chapter 11 Digital Logic 36411.1Boolean Algebra 36511.2Gates 36811.3Combinational Circuits 37011.4Sequential Circuits 38811.5Programmable Logic Devices 39711.6Recommended Reading 40111.7Key Terms and Problems 401Part Four The Central Processing Unit 405Chapter 12 Instruction Sets: Characteristics and Functions 40512.1Machine Instruction Characteristics 40612.2Types of Operands 41312.3Intel x86 and Arm Data Types 41512.4Types of Operations 41812.5Intel x86 and ARM Operation Types 43112.6Recommended Reading 44112.7Key Terms, Review Questions, and Problems 441Appendix 12A Little-, Big-, and Bi-Endian 447Chapter 13 Instruction Sets: Addressing Modes and Formats 45113.1Addressing Modes 45213.2x86 and ARM Addressing Modes 45913.3Instruction Formats 46413.4x86 and ARM Instruction Formats 47313.5Assembly Language 47713.6Recommended Reading 47913.7Key Terms, Review Questions, and Problems 479Chapter 14 Processor Structure and Function 48314.1Processor Organization 48414.2Register Organization 48614.3Instruction Cycle 49114.4Instruction Pipelining 49514.5The x86 Processor Family 512 2013 Pearson Education, Inc., Upper Saddle River, NJ 07458. All Rights ReservedA01 STAL6330 09 SE FM.indd 72/2/12 3:11 AM

viii   Contents14.614.714.8Chapter 1515.115.215.315.415.515.615.715.815.915.10Chapter 1616.116.216.316.416.516.6The Arm Processor 520Recommended Reading 526Key Terms, Review Questions, and Problems 527Reduced Instruction Set Computers 531Instruction Execution Characteristics 533The Use of a Large Register File 538Compiler-Based Register Optimization 543Reduced Instruction Set Architecture 545RISC Pipelining 551MIPS R4000 556Sparc 562RISC Versus CISC Controversy 568Recommended Reading 569Key Terms, Review Questions, and Problems 569Instruction-Level Parallelism and Superscalar Processors 573Overview 574Design Issues 579Pentium 4 589Arm Cortex-A8 595Recommended Reading 603Key Terms, Review Questions, and Problems 605Part Five Parallel Organization 611Chapter 17 Parallel Processing 61117.1Multiple Processor Organizations 61317.2Symmetric Multiprocessors 61517.3Cache Coherence and the MESI Protocol 61917.4Multithreading and Chip Multiprocessors 62617.5Clusters 63317.6Nonuniform Memory Access 64017.7Vector Computation 64417.8Recommended Reading 65617.9Key Terms, Review Questions, and Problems 657Chapter 18 Multicore Computers 66418.1Hardware Performance Issues 66518.2Software Performance Issues 66918.3Multicore Organization 67418.4Intel x86 Multicore Organization 67618.5ARM11 MPCore 67918.6Ibm zEnterprise 196 Mainframe 68418.7Recommended Reading 68718.8Key Terms, Review Questions, and Problems 687 2013 Pearson Education, Inc., Upper Saddle River, NJ 07458. All Rights ReservedA01 STAL6330 09 SE FM.indd 82/2/12 3:11 AM

Contents   ixAppendix AA.1A.2A.3A.4A.5A.6A.7Projects for Teaching Computer Organizationand Architecture 691Interactive Simulations 692Research Projects 694Simulation Projects 694Assembly Language Projects 695Reading/Report Assignments 696Writing Assignments 696Test Bank 696Appendix BAssembly Language and Related Topics 697B.1Assembly Language 698B.2Assemblers 706B.3Loading and Linking 710B.4Recommended Reading 718B.5Key Terms, Review Questions, and Problems 719Online Chapters1Part SixChapter 1919.119.219.319.419.5Chapter 2020.120.220.320.420.520.6The Control Unit 19-1Control Unit Operation 19-1Micro-operations 19-3Control of the Processor 19-13Hardwired Implementation 19-30Recommended Reading 19-35Key Terms, Review Questions, and Problems 19-35Microprogrammed Control 20-1Basic Concepts 20-3Microinstruction Sequencing 20-16Microinstruction Execution 20-26TI 8800 20-45Recommended Reading 20-59Key Terms, Review Questions, and Problems 20-60Online AppendicesAppendix CHash TablesAppendix DVictim Cache StrategiesD.1Victim CacheD.2Selective Victim Cache1Online chapters, appendices, and other documents are Premium Content, available via the access cardat the front of this book. 2013 Pearson Education, Inc., Upper Saddle River, NJ 07458. All Rights ReservedA01 STAL6330 09 SE FM.indd 92/2/12 3:11 AM

x   ContentsAppendix EInterleaved MemoryAppendix FThe International Reference AlphabetAppendix GVirtual Memory Page Replacement AlgorithmsG.1OptimalG.2Least Recently UsedG.3First-In-First-OutG.4Other Page Replacement AlgorithmsAppendix HRecursive ProceduresH.1RecursionH.2Activation Tree RepresentationH.3Stack ProcessingH.4Recursion and IterationAppendixI.1I.2I.3I.4IAdditional Instruction Pipeline TopicsPipeline Reservation TablesReorder BuffersTomasulo’s AlgorithmScoreboardingAppendixJ.1J.2J.3JLinear Tape Open TechnologyLTO GenerationsLTO FormatLTO OperationAppendix KDDR SRAMAppendix LProtocols and Protocol ArchitecturesL.1IntroductionL.2The TCP/IP Protocol ArchitectureL.3The Role of an Internet ProtocolL.4IPv4L.5IPv6L.6The OSI Protocol ArchitectureAppendix MScramblingAppendix NTiming DiagramsAppendix OStacksO.1Stack StructureO.2Stack ImplementationO.3Expression EvaluationGlossary 723References 733Index 745 2013 Pearson Education, Inc., Upper Saddle River, NJ 07458. All Rights ReservedA01 STAL6330 09 SE FM.indd 102/2/12 3:11 AM

Online ResourcesSiteCompanion zationDescriptionStudent Resources link: Useful linksand documents for students.Instructor Resources link: Useful linksand documents for instructors.Premium ContentClick on Premium Content linkat Companion Website or atpearsonhighered.com/stallings andenter the student access code foundon the card in the front of the book.Online chapters, appendices, and otherdocuments that supplement the book.Instructor ResourceCenter (IRC)Click on Pearson Resources forInstructors link at CompanionWebsite or on Instructor Resourcelink at pearsonhighered.com/stallings.Solutions manual, projects manual,slides, and other useful documents.Computer ScienceStudent Resource SiteComputerScienceStudent.comUseful links and documents forcomputer science students.xi 2013 Pearson Education, Inc., Upper Saddle River, NJ 07458. All Rights ReservedA01 STAL6330 09 SE FM.indd 112/2/12 3:11 AM

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PrefaceWhat’s New In The Ninth EditionIn the four years since the eighth edition of this book was published, the field has seen continued innovations and improvements. In this new edition, I try to capture these changeswhile maintaining a broad and comprehensive coverage of the entire field. To begin thisprocess of revision, the eighth edition of this book was extensively reviewed by a numberof professors who teach the subject and by professionals working in the field. The result isthat, in many places, the narrative has been clarified and tightened, and illustrations havebeen improved.Beyond these refinements to improve pedagogy and user-friendliness, there have beensubstantive changes throughout the book. Roughly the same chapter organization has beenretained, but much of the material has been revised and new material has been added. Themost noteworthy changes are as follows: Point-to-point interconnect: The traditional bus architecture has increasingly been replaced with high-speed point-to-point interconnect schemes. A new section exploresthis technology, using Intel’s QuickPath Interconnect (QPI) as an example. PCI Express: PCI Express (PCIe) has become a standard peripheral interconnect architecture, replacing PCI and other bus-based architectures. A new section covers PCIe. Solid state drive and flash memory: Solid state drives are increasingly displacing harddisk drives over a range of computers. A new section covers SSDs and the underlyingflash memory technology. IEEE 754 Floating-Point Standard: The coverage of IEEE 754 has been updated toreflect the 2008 standard. Contemporary mainframe organization: Chapters 7 and 18 include sections on thezEnterprise 196, IBM’s latest mainframe computer offering (at the time of this writing),introduced in 2010. I/O standards: The book has been updated to reflect the latest developments, includingThunderbolt. Multicore architecture: The material on multicore architecture has been expanded significantly. Student study aids: Each chapter now begins with a list of learning objectives.xiii 2013 Pearson Education, Inc., Upper Saddle River, NJ 07458. All Rights ReservedA01 STAL6330 09 SE FM.indd 132/2/12 3:11 AM

xiv   Preface Sample syllabus: The text contains more material than can be conveniently covered inone semester. Accordingly, instructors are provided with several sample syllabi thatguide the use of the text within limited time (e.g., 16 weeks or 12 weeks). These samplesare based on real-world experience by professors with the eighth edition. Test bank: A set of review questions, including yes/no, multiple choice, and fill in theblank is provided for each chapter.With each new edition it is a struggle to maintain a reasonable page count while addingnew material. In part this objective is realized by eliminating obsolete material and tightening the narrative. For this edition, chapters and appendices that are of less general interesthave been moved online, as individual PDF files. This has allowed an expansion of materialw ithout the corresponding increase in size and price.ObjectivesThis book is about the structure and function of computers. Its purpose is to present, asclearly and completely as possible, the nature and characteristics of modern-day computersystems.This task is challenging for several reasons. First, there is a tremendous variety of products that can rightly claim the name of computer, from single-chip microprocessors costinga few dollars to supercomputers costing tens of millions of dollars. Variety is exhibited notonly in cost but also in size, performance, and application. Second, the rapid pace of changethat has always characterized computer technology continues with no letup. These changescover all aspects of computer technology, from the underlying integrated circuit technologyused to construct computer components to the increasing use of parallel organization concepts in combining those components.In spite of the variety and pace of change in the computer field, certain fundamentalconcepts apply consistently throughout. The application of these concepts depends on thecurrent state of the technology and the price/performance objectives of the designer. Theintent of this book is to provide a thorough discussion of the fundamentals of computerorganization and architecture and to relate these to contemporary design issues.The subtitle suggests the theme and the approach taken in this book. It has alwaysbeen important to design computer systems to achieve high performance, but never has thisrequirement been stronger or more difficult to satisfy than today. All of the basic performance characteristics of computer systems, including processor speed, memory speed, memorycapacity, and interconnection data rates, are increasing rapidly. Moreover, they are increasing at different rates. This makes it difficult to design a balanced system that maximizes theperformance and utilization of all elements. Thus, computer design increasingly becomes agame of changing the structure or function in one area to compensate for a performancemismatch in another area. We will see this game played out in numerous design decisionsthroughout the book.A computer system, like any system, consists of an interrelated set of components.The system is best characterized in terms of structure—the way in which components areinterconnected, and function—the operation of the individual components. Furthermore, acomputer’s organization is hierarchical. Each major component can be further described bydecomposing it into its major subcomponents and describing their structure and function. 2013 Pearson Education, Inc., Upper Saddle River, NJ 07458. All Rights ReservedA01 STAL6330 09 SE FM.indd 142/2/12 3:11 AM

Preface   xvFor clarity and ease of understanding, this hierarchical organization is described in this bookfrom the top down: Computer system: Major components are processor, memory, I/O. Processor: Major components are control unit, registers, ALU, and instruction execution unit. Control unit: Provides control signals for the operation and coordination of all processorcomponents. Traditionally, a microprogramming implementation has been used, inwhich major components are control memory, microinstruction sequencing logic, andregisters. More recently, microprogramming has been less prominent but remains animportant implementation technique.The objective is to present the material in a fashion that keeps new material in a clearcontext. This should minimize the chance that the reader will get lost and should providebetter motivation than a bottom-up approach.Throughout the discussion, aspects of the system are viewed from the points of viewof both architecture (those attributes of a system visible to a machine language programmer) and organization (the operational units and their interconnections that realize thearchitecture).Example SystemsThis text is intended to acquaint the reader with the design principles and implementationissues of contemporary operating systems. Accordingly, a purely conceptual or theoreticaltreatment would be inadequate. To illustrate the concepts and to tie them to real-world designchoices that must be made, two processor families have been chosen as running examples: Intel x86 architecture: The x86 architecture is the most widely used for nonembeddedcomputer systems. The x86 is essentially a complex instruction set computer (CISC)with some RISC features. Recent members of the x86 family make use of superscalarand multicore design principles. The evolution of features in the x86 architecture provides a unique case study of the evolution of most of the design principles in computerarchitecture. ARM: The ARM architecture is arguably the most widely used embedded processor,used in cell phones, iPods, remote sensor equipment, and many other devices. TheARM is essentially a reduced instruction set computer (RISC). Recent members of theARM family make use of superscalar and multicore design principles.Many, but by no means all, of the examples in this book are drawn from these two computerfamilies. Numerous other systems, both contemporary and historical, provide examples ofimportant computer architecture design features.Plan Of The TextThe book is organized into six parts (see Chapter 0 for an overview): Overview The computer system 2013 Pearson Education, Inc., Upper Saddle River, NJ 07458. All Rights ReservedA01 STAL6330 09 SE FM.indd 152/2/12 3:11 AM

xvi   Preface Arithmetic and logicThe central processing unitParallel organization, including multicoreThe control unitThe book includes a number of pedagogic features, including the use of interactivesimulations and numerous figures and tables to clarify the discussion. Each chapter includesa list of key words, review questions, homework problems, and suggestions for further reading. The book also includes an extensive glossary, a list of frequently used acronyms, and abibliography.Intended AudienceThe book is intended for both an academic and a professional audience. As a textbook,it is intended as a one- or two-semester undergraduate course for computer science, computer engineering, and electrical engineering majors. It covers all the core topics in thebody of knowledge category, Architecture and Organization, in the IEEE/ACM ComputerCurriculum 2008: An Interim Revision to CS 2001. This book also covers the core areaCE-CAO Computer Architecture and Organization from the IEEE/ACM ComputerEngineering Curriculum Guidelines 2004.For the professional interested in this field, the book serves as a basic reference volume and is suitable for self-study.Instructor Support MaterialsSupport materials for instructors are available at the Instructor Resource Center (IRC) forthis textbook, which can be reached through the Publisher’s Website www.pearsonhighered.com/stallings or by clicking on the link labeled “Pearson Resources for Instructors” at thisbook’s Companion Website at WilliamStallings.com/ComputerOrganization. To gain accessto the IRC, please contact your local Pearson sales representative via esRep.page or call Pearson Faculty Services at1-800-526-0485. The IRC provides the following materials: Projects manual: Project resources including documents and portable software, plussuggested project assignments for all of the project categories listed subsequently inthis Preface. Solutions manual: Solutions to end-of-chapter Review Questions and Problems. PowerPoint slides: A set of slides covering all chapters, suitable for use in lecturing. PDF files: Copies of all figures and tables from the book. Test bank: A chapter-by-chapter set of questions. Sample syllabuses: The text contains more material than can be conveniently coveredin one semester. Accordingly, instructors are provided with several sample syllabusesthat guide the use of the text within limited time. These samples are based on realworld experience by professors with the first edition. 2013 Pearson Education, Inc., Upper Saddle River, NJ 07458. All Rights ReservedA01 STAL6330 09 SE FM.indd 162/2/12 3:11 AM

Preface   xviiThe Companion Website, at WilliamStallings.com/ComputerOrganization (click onInstructor Resources link) includes the following: Links to Websites for other courses being taught using this book. Sign-up information for an Internet mailing list for instructors using this book to exchange information, suggestions, and questions with each other and with the author.Student ResourcesFor this new edition, a tremendous amount of original supporting material for studentshas been made available online, at two Web locations. The Companion Website, atWilliamStallings.com/ComputerOrganization (click on Student Resources link), includes alist of relevant links organized by chapter and an errata sheet for the book.Purchasing this textbook new grants the reader six months of access to the PremiumContent Site, which includes the following materials: Online chapters: To limit the size and cost of the book, two chapters of the book areprovided in PDF format. The chapters are listed in this book’s table of contents. Online appendices: There are numerous interesting topics that support material foundin the text but whose inclusion is not warranted in the printed text. A total of 13 appendices cover these topics for the interested student. The appendices are listed in thisbook’s table of contents. Homework problems and solutions: To aid the student in understanding the material, aseparate set of homework problems with solutions are available. Students can enhancetheir understanding of the material by working out the solutions to these problems andthen checking their answers. Key papers: Several dozen papers from the professional literature, many hard to find,are provided for further reading. Supporting documents: A variety of other useful documents are referenced in the textand provided online.Finally, I maintain the Computer Science Student Resource Site at WilliamStallings.com/StudentSupport.html.Projects And Other Student ExercisesFor many instructors, an important component of a computer organization and architecture course is a project or set of projects by which the student gets hands-on experience toreinforce concepts from the text. This book provides an unparalleled degree of support forincluding a projects component in the course. The instructor’s support materials availablethrough Prentice Hall not only includes guidance on how to assign and structure the projectsbut also includes a set of user’s manuals for various project types plus specific assignments,all written especially for this book. Instructors can assign work in the following areas: Interactive simulation assignments: Described subsequently. 2013 Pearson Education, Inc., Upper Saddle River, NJ 07458. All Rights ReservedA01 STAL6330 09 SE FM.indd 172/2/12 3:11 AM

xviii   Preface Research projects: A series of research assignments that instruct the student to researcha particular topic on the Internet and write a report. Simulation projects: The IRC provides support for the use of the two simulation packages: SimpleScalar can be used to explore computer organization and architecturedesign issues. SMPCache provides a powerful educational tool for examining cachedesign issues for symmetric multiprocessors. Assembly language projects: A simplified assembly language, CodeBlue, is used andassignments based on the popular Core Wars concept are provided. Reading/report assignments: A list of papers in the literature, one or more for eachchapter, that can be assigned for the student to read and then write a short report. Writing assignments: A list of writing assignments to facilitate learning the material. Test bank: Includes T/F, multiple choice, and fill-in-the-blanks questions and answers.This diverse set of projects and other student exercises enables the instructor to usethe book as one component in a rich and varied learning experience and to tailor a courseplan to meet the specific needs of the instructor and students. See Appendix A in this bookfor details.Interactive SimulationsAn important feature in this edition is the incorporation of interactive simulations. Thesesimulations provide a powerful tool for understanding the complex design features of a modern computer system. A total of 20 interactive simulations are used to illustrate key functionsand algorithms in computer organization and architecture design. At the relevant point in thebook, an icon indicates that a relevant interactive simulation is available online for student use.Because the animations enable the user to set initial conditions, they can serve as the basis forstudent assignments. The instructor’s supplement includes a set of assignments, one for eachof the animations. Each assignment includes several specific problems that can be assignedto students. For access to the animations, click on the rotating globe at this book’s Website .AcknowledgmentsThis new edition has benefited from review by a number of people, who gave generouslyof their time and expertise. The following professors and instructors reviewed all or alarge part of the manuscript: Branson Murrill (Virginia Commonwealth University), PanDeng (Florida International University), Bob Broeg (Western Oregon University), CurtisMeadow (University of Maine, Orono), Charles Weems (University of Massachusetts), andMike Jochen (East Stroudsberg University).Thanks also to the many people who provided detailed technical reviews of one ormore chapters: Kauser Johar, Todd Bezenek (Quantum), Moustafa Mohamed (Universityof Colorado at Boulder), Dharmesh Parikh, Qigang Wang, Rajiv Dasmohapatra (WIPROLtd), Anup Holey (University of Minnesota, Twin Cities), Alexandre Keunecke Ignacio deMendonca, Douglas Tiedt, Kursad Albayraktaroglu (Advanced Micro Device), NilanjanGoswami (University of Florida, Gainesville), Adnan Khaleel (Cray, Inc.), Geri Lamble, 2013 Pearson Education, Inc., Upper Saddle River, NJ 07458. All Rights ReservedA01 STAL6330 09 SE FM.indd 182/2/12 3:11 AM

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3.2 Computer Function 68 3.3 Interconnection Structures 84 3.4 Bus Interconnection 85 3.5 Point-To-Point Interconnect 93 3.6 PCI Express 98 3.7 Recommended Reading 108 3.8 Key Terms, Review Questions, and Problems 108 Chapter 4 Cache Memory 112 4.1 Computer Memory System Overview 113 4.2 Cache Memory Principles 120 4.3 Elements of Cache Design .