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101101010101SAR ADC’s vs. Delta-Sigma ADC’s:Different Architectures for Different Applications1

Common ADC TopologiesADC TopologyData RateSAR:ADC0x/1xADS7xxxADS8xxxADS9xxx 5 MSPSDelta-Sigma ( xxxADS5xxxResolutionComments 20-bit Easy to UseZero LatencyLow Power 10 MSPS 32-bit High ResolutionHigh Integration 1000 MSPS 16-bit Higher SpeedHigher Power2

Common ADC TopologiesADC TopologyData RateSAR:ADC0x/1xADS7xxxADS8xxxADS9xxx 5 MSPSDelta-Sigma ( xxxADS5xxxResolutionComments 20-bit Easy to UseZero LatencyLow Power 10 MSPS 32-bit High ResolutionHigh Integration 1000 MSPS 16-bit Higher SpeedHigher Power3

SAR ArchitectureCommon ADC TopologiesAdvantages Low Latency-time High Accuracy Typically Low Power Easy to Use 24Converter Resolution (bits)32DisadvantagesDelta-Sigma20 Max FSAMP of version Rate (SPS)4

Common ADC TopologiesADC TopologyData RateSAR:ADC0x/1xADS7xxxADS8xxxADS9xxx 5 MSPSDelta-Sigma ( xxxADS5xxxResolutionComments 20-bit Easy to UseZero LatencyLow Power 10 MSPS 32-bit High ResolutionHigh Integration 1000 MSPS 16-bit Higher SpeedHigher Power5

Delta-Sigma ArchitectureCommon ADC TopologiesAdvantages High Resolution Low Noise High Stability High Integration 24Converter Resolution (bits)32Disadvantages20 100K1M10M100M1GConversion Rate (SPS)6

Common ADC TopologiesADC TopologyData RateSAR:ADC0x/1xADS7xxxADS8xxxADS9xxx 5 MSPSDelta-Sigma ( xxxADS5xxxResolutionComments 20-bit Easy to UseZero LatencyLow Power 10 MSPS 32-bit High ResolutionHigh Integration 1000 MSPS 16-bit Higher SpeedHigher Power7

Pipeline ArchitectureADC TechnologiesAdvantages Higher Speeds Higher Bandwidth 24Converter Resolution (bits)32Disadvantages Lower Resolution Pipeline Delay/Latency Higher 10M100M1GConversion Rate (SPS)8

SAR vs. Delta-SigmaWhat is the ADC actually converting?SARSAR ADC takes “snapshots”Each conversion command captures thesignal level, at that point in time, onto thesample/hold ADC calculates an averageThe signal is sampled continuously9

SAR vs. Delta-SigmaHow does the ADC control happen? SAR conversions have Start Conversion Signal Delta-Sigma’s are always sampling/convertingSAR ConverterStart ConversionConversion DoneDelta-Sigma ConverterInput SamplingConversion Done10

How Does a SAR ADC Work? Similar to a balance scale?1½¼11

How Does a SAR ADC Work? Similar to a balance scale?1½¼12

How Does a SAR ADC Work? Similar to a balance scale?1½¼13

How Does a SAR ADC Work? Similar to a balance scaleThe MSB is determined first1?MSB1½¼14

How Does a SAR ADC Work? Similar to a balance scaleThe test is repeated for eachBinary weighted bit?1½MSBMid10¼15

How Does a SAR ADC Work? Similar to a balance scaleThe LSB is determined last?1¼MSBMidLSB101½16

Typical Topology of a SAR ADC17

SAR ADC Acquisition PhaseVINDACSAMPLE & HOLDData RegisterS1COMPARATORS2VINSARCN-bit SearchDAC18

SAR ADC Acquisition PhaseVINDACSAMPLE & HOLDData RegisterS1S2VINSARCOMPARATORCVIN1/2 LSBN-bit SearchDACVCSH(t)VSH0t0tAQTime19

SAR ADC Acquisition PhaseVINDACSAMPLE & HOLDCOMPARATORVIN1/2 LSBVCSH(t)VCSH (t ) VCSH (t0 ) [VIN VCSH (t0 )] (1 eVSH0t0tAQTime t ) RS1 CSH20

SAR ADC Conversion PhaseFSBit 0VDAC3/4FS1/2FSBit 1Bit 0Bit 0AnalogInputBit 1TESTMSBTESTMSB -1TESTMSB -2TESTMSB -3TESTLSB1/4FS0TimeDAC OutputDigital Output Code 1010021

SAR ADCs Very Popular Topology Attractive in “Point in Time” or Multiplexed MeasurementsSAR ADC Advantages– “no latency” input is sampled once “balancing” done internally– good tradeoff between speed, resolution and power Speed: DC to 5 MSPS Resolution: 8 to 20 bits TI Part 2

Delta-Sigma utputDigital Decimating Filter23

Delta-Sigma Topology(2)High frequency, 1 bit PCM data streamSAMPLING RATE es at High atorDigitalOutputDigital Decimating Filter24

Delta-Sigma Topology(3)High frequency, 1 bit PCM data streamSAMPLING RATE (Fs)Delta-SigmaModulatorModulatorAnalogInputInput imatorDigital Decimating FilterDigitalOutputDATA RATE (Fd)Lower data rate, very highresolution digital output25

Oversampling(1)PowerInputSignalIdeal N-Bit ADCSNR 6.02 N 1.76 dBAverage NoiseFloorDCfs/2fsAverage Noise energydistributed from DC tofs/226

Oversampling(2)OversamplingPowerDigital Low PassfilterPowerInputSignalIdeal N-Bit ADCSNR 6.02 N 1.76 dBSNR 6.02 N 1.76 dB 10 log (OSR)Average NoiseFloorDCfs/2Average Noise energydistributed from DC tofs/2fsAverage NoiseFloorDCK fs/2Average Noise energy distributed over awider range from DC to K fs/2K fs– On a Delta-Sigma Converter, the analog input issampled at a Frequency much higher than theNyquist rate27

Delta Sigma r28

First Order Delta-Sigma Modulator(1)Noise ShapingQuantizationNoiseeiInputSignalXi -Integrator(Low-Pass)A(f) 1/f Yi1-BitADC1-BitDAC29

First Order Delta-Sigma ModulatorNoise Shaping(2)QuantizationNoiseeiInputSignalXi Integrator(Low-Pass)A(f) 1/f - Yi1-BitADC1-BitDAC𝑌 𝑋 𝑌 𝐴 𝑓 𝑒 𝑛𝑌 𝑒 𝑛(1)𝑓1 𝑋1 𝑓1 30

First Order Delta-Sigma ModulatorNoise Shaping(3)QuantizationNoiseeiInputSignalXi Integrator(Low-Pass)A(f) 1/f - Yi1-BitADC1-BitDAC𝑌 𝑒 𝑛𝑓1 𝑋1 𝑓1 (2)Magnitude𝑌 𝑋 𝑌 𝐴 𝑓 𝑒 𝑛SignalQuantizationNoise31

First Order Delta-Sigma Modulator(4)Noise ShapingModulator Output:TIME DOMAINSignalBelieve it or not, the sinewave is in there!10(drawing is approximate)32

First Order Delta-Sigma Modulator(5)Noise ShapingModulator Output:TIME DOMAINSignalBelieve it or not, the sinewave is in there!10(drawing is approximate)33

First Order Delta-Sigma Modulator(6)Noise ShapingModulator Output:Modulator Output:TIME DOMAINFREQUENCY DOMAINSignalBelieve it or not, the sinewave is in there!SIGNAL10Fs(drawing is approximate)QUANTIZATIONNOISE34

Higher Order Delta-Sigma ModulatorsThird Order ModulatorSecond Order ModulatorFirst Order ModulatorFrequencyFS35

Delta-Sigma A/D Signal PathDelta-SigmaModulatorDigitalFilterDecimator36

Modulator Noise Shaping and Digital Filter(1) ModulatorNoise ShapingFrequencyFS37

Modulator Noise Shaping and Digital Filter(2) ModulatorNoise ShapingFrequencyFS38

Modulator Noise Shaping and Digital Filter(3) ModulatorNoise ShapingFilter set byOversamplingRatioFrequencyFS39

Digital Filter Digital filter architecture determines overall ADC response. Common filters: “Sinc” and “Flat Passband”Sinc FilterFlat Passband Filter40

Sinc Digital Filter Sinc filter response0Sinc 1Sinc 3Sinc 5-20Attentuation, dBTypically used for DCmeasurements, or slow movingsignalsAdvantages Economical silicon area, easy toimplement– Low cost– Low power Low latency Filter notches can target specificfrequencies (ex. 50/60 Hz)Disadvantages Pass band signal droop Weak Stop band attenuation forlow-order Sinc filters-40-60-80Fdata-1000123456Frequency (x Fdata)41

Sinc Digital Filter SettlingUncertainty of Analog Edge 4 Data Cycles01230123Fdata periodsAnalog Inputs3 full cycles3 full cycles4 cyclesValid dataValid dataSettling time for an input step change, Sinc3 filterNeed n cycles to settle for a Sincn filter42

Delta-Sigma: Zero Cycle Latency(1)Single CycleConversionAnalog INN 0N 2N 1N 3N-1N 0N 1N 2N 3Data OUTDataInvalid Zero cycle Latency – Zero latency– Single cycle conversion– Single cycle settling– No Latency43

Delta-Sigma: Zero Cycle Latency(2)Single CycleConversionAnalog INN 0N 2N 1N 3N-1N 0N 1N 2N 3Data OUTDataInvalid Zero cycle Latency – Zero cycle latency– Single cycle conversion– Single cycle settling– No Latency“Hidden Conversions”44

Flat Pass Band FilterAdvantages Frequency Response Very low ripple pass band Sharp Nyquist transition band Large stopband attenuation: lower than-100dB (simplify aliasing requirement)Frequency response scalable with masterclockLow Ripple Passband100dB stop bandDisadvantages Large area – Costly Higher-order / high-tap filter – large latency45

Delta-Sigma: Flat Passband Digital Filter Settling The latency of the filter depends on the number of delay blocks used Flat Passband filters require a lot delay blocks to maintain desired AC response Many Delta-Sigma Converters incorporate filters with programmable settings:– Optimize for lower latency, power consumption or for AC performance/higher resolutionModulatorDataInputFIR filter blocktopologydelaydelaydelaydelaydelayΣDigital FilterOutput46

ΔΣ ADCs: Simplifying the Signal ChainCTPassive Network Protection InR1Passive Network OutMUXR2Gain StageMuxADC DriveCircuitryADC DriveADCADCProcessorIsoMCU47

ΔΣ ADCs: Simplifying the Signal ChainCTPassive Network Protection InR1Passive Network OutMUXR2Gain StageMuxADC DriveCircuitryADC DriveADCADCProcessorIsoMCUDelta-Sigma ADCs integrate many signal chain elements into one device48

Delta-Sigma ADCs Useful for Lower Bandwidth Signals Very High Resolution Very High Linearity Incorporate a Digital Filter Frequency Response, and Latency dependent on Digital Filter Very Low Power Typically Highly Integrated devices:– Digital Filter, Buffer, PGA, MUX, Vref, Calibration/diagnostics Simple Anti-Aliasing Filter Typically Requires Configuration of RegistersΔΣ ADC49

SAR ADCs Very Popular Topology Attractive in “Point in Time” or Multiplexed MeasurementsSAR ADC Advantages– “no latency” input is sampled once “balancing” done internally– good tradeoff between speed, resolution and power Speed: DC to 5 MSPS Resolution: 8 to 20 bits TI Part 0

Input Driver Circuit for SAR ADC-Data RegisterS2S1SAR CN-bit SearchDACHIGH GBWFaster load transient responseCF is an ideal source tohigh frequency transients51

Input Driver Circuit for SAR ADC-Data RegisterS2S1SAR CN-bit SearchDACIsolation ResistorStabilizes op amp by isolating it from the capacitive load.In addition, the RC network slows the load transient seen bythe op amp and provides noise and anti-aliasing filtering.52

Fully Differential ADC InputsTHS4551 Based Single-Ended Input to Differential Output withMultiple Feedback Filter Interface to the 24-bit, 512 kSPS ADS127L01 Delta-Sigma ADCADS127L01 AINNTHS4551 -ΔΣ ADCCoreInput Range24-bitDifferential Input512 kSPSVin: VREFAINPOn ChipDecimationFilterSPI & FrameSync DigitalInterfacePassband: 230 kHz5-pin SPI115.5 dB SNR-129 dB THDDaisy ChainCapable53

THS4551 Fully Differential ADC DriverPopular Texas Instruments ADCFamilies Supported by the THS4551VS VOCMIN 24-bit512 kSPSADS8900BSAR20-bit1 MSPSADS8910BSAR18-bit1 MSPSADS9110SAR18-bit2 MSPSADC3241Pipeline14-bit25 MSPSOUT-THS4551 DeviceOUT 54

More Analog Signal Chain InformationPrecision ADC Web Page: www.ti.com/precisionadcFully Differential Amplifier Web Page: www.ti.com/fda Data Sheets & Technical Reference Manuals Application Notes Software, Tools & SPICE Model Downloads Order Evaluation & Performance Demonstration KitsPrecision ADC E2E Support Forum:www.ti.com/precisionadcsupport Ask Technical Questions Search for Technical ContentPrecision HUB Blog Series:e2e.ti.com/blogs /b/precisionhubTips, tricks and techniquesfrom TI precision analog expertsTI Designs - Precision:www.ti.com/precisiondesigns Reference Designs Board Schematics & Verification Results55

Special ThanksSpecial thanks to the following people for contributing to this presentation: Ryan Callaway – Delta-Sigma ADC Tony Calabria – Delta-Sigma ADC Anthony Vaughan – High Speed Amplifiers Michael Steffes – High Speed Amplifiers Luis Choye – SAR ADC Vinay Agarwal – SAR 01110110101010156

– On a Delta-Sigma Converter, the analog input is sampled at a Frequency much higher than the Nyquist rate fs/ 2 fs Power Average Noise energy dist ribut ed from DC t o fs/ 2 Ideal N-Bit ADC SNR 6.02 N 1.76 dB DC Input Signal Average Noise Floor Average Noise l or K fs/ 2 K fs Power Average Noise energy dist ribut ed over a