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DLP471TEwww.ti.comDLPS170A – SEPTEMBER 2020 – REVISED JUNE 20216 Specifications6.1 Absolute Maximum RatingsStresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These arestress ratings only, and functional operation of the device is not implied at these or any other conditions beyond thoseindicated under Recommended Operating Conditions. Exposure above or below the Recommended Operating Conditions forextended periods may affect device reliability.MINMAXUNITSUPPLY VOLTAGEVDDSupply voltage for LVCMOS core logic and LVCMOS low speed interface(LSIF)(1)–0.52.3VVDDASupply voltage for high speed serial interface (HSSI) receivers(1)–0.32.2VVOFFSETSupply voltage for HVCMOS and micromirror electrode(1) (2)–0.511VVBIASSupply voltage for micromirrorelectrode(1)–0.519VVRESETSupply voltage for micromirror electrode(1)–150.5V VDDA – VDD Supply voltage delta (absolutevalue)(3)0.3V VBIAS – VOFFSET Supply voltage delta (absolute value)(4)11Vvalue)(5)34V–0.52.45V–0.2VDDAV VBIAS – VRESET Supply voltage delta (absoluteINPUT VOLTAGEInput voltage for other inputs – LSIF and LVCMOS(1)Input voltage for other inputs –HSSI(1) (6)LOW SPEED INTERFACE (LSIF)fCLOCKLSIF clock frequency (LS CLK)130MHz VID LSIF differential input voltage magnitude(6)810mVIIDLSIF differential input current10mAHIGH SPEED SERIAL INTERFACE (HSSI)fCLOCKHSSI clock frequency (DCLK)1.65GHz VID HSSI differential input voltage magnitude Data Lane(6)700mV700mV090 C–4090 C VID HSSI differential input voltage magnitude ClockLane(6)ENVIRONMENTALTWINDOW and TARRAYTemperature, non-operating(7) TDELTA Absolute temperature delta between any point on the window edge and theceramic test point TP1(8)30 CTDPDew point temperature, operating and non–operating (noncondensing)81 C(1)(2)(3)(4)(5)(6)(7)(8)6Temperature, operating(7)All voltage values are with respect to the ground terminals (VSS). The following required power supplies must be connected for properDMD operation: VDD, VDDA, VOFFSET, VBIAS, and VRESET. All VSS connections are also required.VOFFSET supply transients must fall within specified voltages.Exceeding the recommended allowable absolute voltage difference between VDDA and VDD may result in excessive current draw.Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current draw.Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current draw.This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. LVDS and HSSIdifferential inputs must not exceed the specified limit or damage may result to the internal termination resistors.The highest temperature of the active array (as calculated using Micromirror Array Temperature Calculation) or of any point along thewindow edge as defined in Figure 7-1. The locations of thermal test points TP2, TP3, TP4 and TP5 in Figure 7-1 are intended tomeasure the highest window edge temperature. If a particular application causes another point on the window edge to be at a highertemperature, that point should be used.Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown inFigure 7-1. The window test points TP2, TP3, TP4, and TP5 shown in Figure 7-1 are intended to result in the worst case delta. If aparticular application causes another point on the window edge to result in a larger delta temperature, that point should be used.Submit Document FeedbackCopyright 2021 Texas Instruments IncorporatedProduct Folder Links: DLP471TE

DLP471TEwww.ti.comDLPS170A – SEPTEMBER 2020 – REVISED JUNE 20216.2 Storage ConditionsApplicable for the DMD as a component or non-operating in a system.TDMDDMD temperatureTDP-AVGAverage dew point temperature, non-condensing(1)non-condensing(2)TDP-ELRElevated dew point temperature range,CTELRCumulative time in elevated dew point temperature range(1)(2)MINMAX–4080 C28 C28UNIT36 C24monthsThe average temperature over time (including storage and operating temperatures) that the device is not in the elevated dew pointtemperature range.Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a totalcumulative time of CTELR.6.3 ESD RatingsV(ESD)(1)(2)ElectrostaticdischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)Charged device model (CDM), per JEDEC specificationVALUEUNIT 2000V 500VJESD22-C101(2)JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.6.4 Recommended Operating #GUID-DB050334-17E7-422B-91B0-D62FF359059DOver operating free-air temperature range and supply voltages (unless otherwise noted). The functional performance of thedevice specified in this data sheet is achieved when operating the device within the limits defined by the RecommendedOperating Conditions. No level of performance is implied when operating the device above or below the RecommendedOperating Conditions limits.SUPPLY VOLTAGESMINTYPMAXUNIT(1) (2)VDDSupply voltage for LVCMOS core logic and low speedinterface (LSIF)1.711.81.95VVDDASupply voltage for high speed serial interface (HSSI) receivers1.711.81.95Velectrode(3)VOFFSETSupply voltage for HVCMOS and micromirror9.51010.5VVBIASSupply voltage for micromirror electrode17.51818.5VVRESETSupply voltage for micromirror electrode–14.5–14–13.5V VDDA – VDD Supply voltage delta, absolute value(4)0.3Vvalue(5)10.5V33V VBIAS – VOFFSET Supply voltage delta, absolute VBIAS – VRESET Supply voltage delta, absolute valueLVCMOS INPUTVIHHigh level input voltage(6)VILvoltage(6)Low level input0.7 x VDDV0.3 x VDDVLOW SPEED SERIAL INTERFACE (LSIF)fCLOCKLSIF clock frequency (LS CLK)(7)DCDINLSIF duty cycle distortion (LS CLK) VID LSIF differential input voltageVLVDSLSIF 30MHz56%440mV1520mVmVVCMCommon mode7009001300ZLINELine differential impedance (PWB/trace)90100110ΩZINInternal differential termination resistance80100120Ω1.6GHzHIGH SPEED SERIAL INTERFACE (HSSI)fCLOCKHSSI clock frequency (DCLK)(8)1.2Submit Document FeedbackCopyright 2021 Texas Instruments IncorporatedProduct Folder Links: DLP471TE7

DLP471TEwww.ti.comDLPS170A – SEPTEMBER 2020 – REVISED JUNE 2021Over operating free-air temperature range and supply voltages (unless otherwise noted). The functional performance of thedevice specified in this data sheet is achieved when operating the device within the limits defined by the RecommendedOperating Conditions. No level of performance is implied when operating the device above or below the RecommendedOperating Conditions limits.DCDINHSSI duty cycle distortion (DCLK)Lane(8) VID DataHSSI differential input voltage magnitude Data VID CLKHSSI differential input voltage magnitude Clock C DataInput common mode voltage (DC) DataVCMDC CLKInput common mode voltage (DC) Clk Lane(8)VCMACp-pAC peak to peak (ripple) on common mode voltage of DataLane and Clock Lane(8)ZLINELine differential impedance (PWB/trace)ZINInternal differential termination resistance. ( RXterm )80Array temperature, long–term operational(9) (10) (11) (12) 40 to 70 C010 CENVIRONMENTALTARRAYArray temperature, short-term operational, 500 hr max(10) (14)operational(15)TWINDOWWindow temperature,85 C TDELTA Absolute temperature delta between any point on the windowedge and the ceramic test point TP1(16)14 CTDP-AVGAverage dew point temperature (non–condensing)(17)28 C(non-condensing)(18)TDP-ELRElevated dew point temperature range36 CCTELRCumulative time in elevated dew point temperature range2824monthsILLθIllumination marginal ray angle(19)55degrees2mW/cm2LAMP ILLUMINATIONILLUVIllumination wavelength 395 nm(9)ILLVISIllumination wavelengths between 395 nm and 800 nm(13)ILLIRIllumination wavelength 800 nm0.6836.8W/cm210mW/cm23mW/cm2SOLID STATE ILLUMINATIONIllumination wavelength 410 nm(9)ILLUVILLVISIllumination wavelengths between 410 nm and 800ILLIRIllumination wavelength 800 15)8nm(13)44.910W/cm2mW/cm2All power supply connections are required to operate the DMD: VDD, VDDA, VOFFSET, VBIAS, and VRESET. All VSS connections arerequired to operate the DMD.All voltage values are with respect to the VSS ground pins.VOFFSET supply transients must fall within specified max voltages.To prevent excess current, the supply voltage delta VDDA – VDD must be less than specified limit.To prevent excess current, the supply voltage delta VBIAS – VOFFSET must be less than specified limit.LVCMOS input pin is DMD DEN ARSTZ.See the low speed interface (LSIF) timing requirements in Timing Requirements.See the high speed serial interface (HSSI) timing requirements in Timing Requirements.Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illuminationreduces device lifetime.The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point(TP1) shown in Figure 7-1 and the package thermal resistance using the Micromirror Array Temperature Calculation.Per Figure 6-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that theDMD experiences in the end application. Refer to Micromirror Landed-On/Landed-Off Duty Cycle for a definition of micromirror landedduty cycle.Long-term is defined as the usable life of the device.The maximum optical power that can be incident on the DMD is limited by the maximum optical power density and the micromirrorarray temperatureShort-term is the total cumulative time over the useful life of the device.The locations of thermal test points TP2, TP3, TP4, and TP5 shown in Figure 7-1 are intended to measure the highest window edgetemperature. For most applications, the locations shown are representative of the highest window edge temperature. If a particularapplication causes additional points on the window edge to be at a higher temperature, test points should be added to those locations.Submit Document FeedbackCopyright 2021 Texas Instruments IncorporatedProduct Folder Links: DLP471TE

DLP471TEwww.ti.comDLPS170A – SEPTEMBER 2020 – REVISED JUNE 2021Maximum Recommended Array Temperature - Operational (¹C)(16) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shownin Figure 7-1. The window test points TP2, TP3, TP4, and TP5 shown in Figure 7-1 are intended to result in the worst case deltatemperature. If a particular application causes another point on the window edge to result in a larger delta in temperature, that pointshould be used.(17) The average over time (including storage and operating) that the device is not in the ‘elevated dew point temperature range'.(18) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a totalcumulative time of CTELR.(19) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including pond of micromirrors(POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarilybeen designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has notbeen tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM)will contribute to thermal limitations described in this document, and may negatively affect 30/7035/6540/6045/55 5/4550/50Micromirror Landed Duty CycleFigure 6-1. Maximum Recommended Array Temperature - Derating Curve6.5 Thermal InformationDLP471TETHERMAL METRICFYN PACKAGEUnit149 PINSThermal Resistance, active area to test point 1 (TP1)(1)(1)0.8 C/WThe DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable ofmaintaining the DMD within the temperature range specified in the Section 6.4. The total heat load on the DMD is largely driven bythe incident light absorbed by the active area; although other contributions include light energy absorbed by the window aperture andelectrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling outside the windowclear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.6.6 Electrical CharacteristicsOver operating free-air temperature range and supply voltages (unless otherwise noted)PARAMETER (1) (2)TEST CONDITIONS (1)MINTYPMAX UNITCURRENT – TYPICALIDDSupply current VDD (3)8001200mAIDDASupply current VDDA (3)10001200mAIDDASupply current VDDA(3)500600mAIOFFSETSupply current VOFFSET (4) (5)2025mASingle macro modeSubmit Document FeedbackCopyright 2021 Texas Instruments IncorporatedProduct Folder Links: DLP471TE9

DLP471TEwww.ti.comDLPS170A – SEPTEMBER 2020 – REVISED JUNE 2021Over operating free-air temperature range and supply voltages (unless otherwise noted)PARAMETER (1) (2)IBIASSupply current VBIASIRESETTEST CONDITIONS (1)MIN(4) (5)Supply current VRESETTYP2.5(5)-9.3MAX UNIT4.0-6.9mAmAPOWER – TYPICALPDDSupply power dissipation VDD (3)14402437.5mWPDDASupply power dissipation VDDA (3)16202340mWPDDASupply power dissipation VDDA 367.55mWsingle macro mode(4) (5)POFFSETSupply power dissipation VOFFSETPBIASSupply power dissipation VBIAS (4) (5)PRESETSupply power dissipation VRESETPTOTALSupply power dissipation Total(5)LVCMOS INPUTIILLow level input current (6)IIH(6)High level input currentVDD 1.95 V, VI 0 V–100VDD 1.95 V, VI 1.95 VnA135uALVCMOS OUTPUTVOHDC output high voltage (7)IOH -2 mAVOLDC output low voltage (7)IOL 2 mA0.8 x VDDV0.2 x VDDVRECEIVER EYE CHARACTERISTICSMinimum data eye opening (8) (9)100600mV295600mV600mVX1Maximum data eye closure(8)0.275UIX2Maximum data eye closure (8)0.4UI tDRIFT Drift between Clock and Data betweenTraining Patterns20psA1Minimum clock eye opening(8) (9)Maximum data signal swing (8) (9)A2CAPACITANCECINInput capacitance LVCMOSf 1 MHz10pFCINInput capacitance LSIF (low speedinterface)f 1 MHz20pFCINInput capacitance HSSI (high speed serialf 1 MHzinterface)20pFCOUTOutput capacitance10pF(1)(2)(3)(4)(5)(6)(7)(8)(9)10f 1 MHzAll power supply connections are required to operate the DMD: VDD, VDDA, VOFFSET, VBIAS, and VRESET. All VSS connections arerequired to operate the DMD.All voltage values are with respect to the ground pins (VSS).To prevent excess current, the supply voltage delta VDDA – VDD must be less than specified limit.To prevent excess current, the supply voltage delta VBIAS – VOFFSET must be less than specified limit.Supply power dissipation based on 3 global resets in 200 µs.LVCMOS input specifications are for pin DMD DEN ARSTZ.LVCMOS output specification is for pins LS RDATA A and LS RDATA B.Refer to Figure 6-11, Receiver Eye Mask (1e-12 BER).Defined in Recommended Operating Conditions.Submit Document FeedbackCopyright 2021 Texas Instruments IncorporatedProduct Folder Links: DLP471TE

DLP471TEwww.ti.comDLPS170A – SEPTEMBER 2020 – REVISED JUNE 20216.7 Switching CharacteristicsOver operating free-air temperature range and supply voltages (unless otherwise noted)PARAMETERtpd(1)TEST CONDITIONSMINTYPMAXUNITOutput propagation, Clock to Q (C2Q), rising edge ofLS CLK (differential clock signal) input to LS RDATAoutput.(1)CL 5 pF11.1nsCL 10 pF11.3nsSlew rate, LS RDATA20%-80%, CL 10pF0.5Output duty cycle distortion, LS RDATA A andLS RDATA B50-(C2Q rise - C2Qfall )*130e6*10040V/ns60%See Figure 6-2LS CLK P1010011010LS CLK N1 periodLS WDATA PStop (1)Start (0)LS WDATA NtPDLS RDATA ABIST AAcknowledgeFigure 6-2. Switching CharacteristicsSubmit Document FeedbackCopyright 2021 Texas Instruments IncorporatedProduct Folder Links: DLP471TE11

DLP471TEwww.ti.comDLPS170A – SEPTEMBER 2020 – REVISED JUNE 20216.8 Timing RequirementsOver operating free-air temperature range and supply voltages (unless otherwise noted)PARAMETERTEST CONDITIONSMINTYPMAXUNITLVCMOSRise time(1)trtfFalltime(1)20% to 80% reference points25ns80% to 20% reference points25nsLOW SPEED INTERFACE (LSIF)trRise time(2)20% to 80% reference points450pstfFall time(2)80% to 20% reference points450pshigh(3)tW(H)Pulse durationLS CLK. 50% to 50% reference points3.1nstW(L)Pulse duration low(3)LS CLK. 50% to 50% reference points3.1nstsuSetup time(4)LS WDATA valid before rising edge of LS CLK(differential)1.5nsthHold time(4)LS WDATA valid after rising edge of LS CLK(differential)1.5nsHIGH SPEED SERIAL INTERFACE (HSSI)trRise time(5) (6) - datafrom -A1 to A1 minimum eye height specification50115psRise time(5) (6) - clockrom -A1 to A1 minimum eye height specification50135pspsFalltime(5) (6)from A1 to -A1 minimum eye height specification50115Fall time(5) (6) - clockfrom A1 to -A1 minimum eye height specification50135tW(H)Pulse duration high(7)DCLK. 50% to 50% reference points0.275nstW(L)Pulse duration low(7)DCLK. 50% to 50% reference points0.275nstf(1)(2)(3)(4)(5)(6)(7)- dataSee Figure 6-9 for rise time and fall time for LVCMOS.See Figure 6-5 for rise time and fall time for LSIF.See Figure

HSSI Maco Ar Data Paisr HSSI Maco r B Data Paisr DMD DCLKA DMD DCLKB 8 8 P roew Managnteme TPS65145 Votffse Vtseer Vbias VREG 1.8 V TMP411 Tpm e 2 I2C DMD P roew En DMD VDD En 12 V DLPC7540 Display Coonlrtlre VREG 3.3 V Simplified Application www.ti.com DLP471TE DLPS170 - SEPTEMBER 2020