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Tech Talks LIVE Schedule – Presentation will begin shortlySILICON LABS LIVEInternet Infrastructure andIndustrial Automation Tech TalksWednesday, June 17thDigital Isolation for Industrial Automation EquipmentWednesday, June 24thClock Builder Pro Tips and TricksWednesday, July 1stEvolution of Isolated Gate Driver in an Energy Conscious WorldWednesday, July 8thSilicon Labs’ Latest Timing Portfolio and Reference DesignsWednesday, July 15thPower Over Ethernet PD and PSE SolutionsWednesday, July 22ndDiscover, Evaluate and Develop with Silicon Labs’ Timing ToolsWednesday, July 29thDigital Isolation for Safety and Reliability in Industrial Power SuppliesWednesday, August 5thFast and Easy Measurements with PCIe Clock Jitter ToolWednesday, August 12thIEEE 1588 and Silicon Lab’ Timing ModulesTiming Portfolio:https://www.silabs.com/timingFind Past Recorded Sessions at:https://www.silabs.com/support/training
WELCOMESILICON LABS LIVEInternet Infrastructure andIndustrial Automation Tech Talks
Silicon Labs IEEE 1588/SyncE SolutionsAUG 2020
Comprehensive Timing Portfolio Leader in high performance clocks and oscillators Frequency flexibility ultra-low jitter Best-in-class integration single IC clock trees Highly programmable with quick-turn samples4XO/VCXOClock GeneratorsClock BuffersSyncE/IEEE 1588Clocks, Modules,SoftwareJitter Attenuating ClocksWireless ClocksSilicon Labs Confidential
New Applications Require Optimized IEEE 1588 Solutions5GFINANCIAL TRADINGBROADCAST VIDEO/MACHINE VISIONCarrierAggregationCoMP5G NR features require precise syncEnables higher user bandwidthImproves coordination between cellsTime stamps financial tradesImproves accuracy and reliabilityEnsures regulatory complianceReal-time sync between camerasEases transition to Ethernet-basedvideoSilicon Labs Confidential
Mobile Network Synchronization TDD/TDMA networks need to be tightly synchronized to prevent dropped calls Mobile networks rely on Frequency and Phase (Time) synchronization Synchronization distributes accurate Time of Day (ToD) across a networkCell ARRU 50 ppb freq 1.5 µs*phaseBBURRUCell B6* 130 ns for emerging 5G applicationsSilicon Labs Confidential
Synchronous Ethernet Frequency Synchronization Prior to IEEE 1588, network synchronization was implemented using older synchronous protocols,such as SONET and SDH. When these networks were changed to use Ethernet standards, a method was needed to preventthat synchronization from being broken. Synchronous Ethernet provides the solution, where the continuous Ethernet clock is propagatedthrough each node.7Silicon Labs Confidential
Distribution of Time (ToD) using IEEE 1588Goal of 1588: Synchronize Time of Day (ToD) acrossevery node in the network 30-100 ns max time error hop-hop 130 ns or 1.5 us end-end accuracyfor 5G mobile networks1588 Messaging: Keeps ToD synchronized hop-hop Measures & compensates for one-waydelay and ToD offset between hops Requires both 1588 stack & servosoftware at every node8
IEEE 1588/PTP Synchronization (t1, t2, t3, t4) Time is synchronized with four message types: Sync – From Master to Slave (t1) The slave records the timestamp of when the Sync Message is received(t2) Follow-up is optional If the correct time is in the Sync message, there is no follow-up message,but if a 2nd message is needed to send the correct time, the Follow-Upmessage is used. Note: Timestamping a packet accurately with high resolution at theinstant the packet is being transmitted is HARD Delay Req, asks the Master to send back a timestamp Slave records the transmit timestamp (t3) Delay Resp (t4) Master’s timestamp when Delay Req is received t1, t2, t3, t4 calculations: One way propagation delay (Master to Slave): t2 – t1One way propagation delay (Slave to Master): t4- t3Average Propagation delay: ((t2 – t1) (t4 – t3))/2Average Offset Error: ((t2 – t1)-(t4- t3))/2 This is the error that needs to be driven to zero to synchronize the clocksSee: n-notes/an1202-itu-t precision time protocol grandmaster.pdf
Time ErrorTime ErrorMax TE cTEdTE0Time Need an accurate time reference - no meaning without a reference Maximum Absolute Time Error (Max TE ) is the maximum distance fromzero of the time error function Sign doesn’t matter: excursions may be positive or negative Constant Time Error (cTE) is the mean of the time error function Period over which mean is measured is not specified; depends on signal Dynamic Time Error (dTE) is the change of the time error function Effectively this is the phase or time wander, analysed using MTIE and TDEV10Source: Calnex
IEEE 1588 Software Application challenge: Packet Delay Variation (PDV)140 us10usperdiv High performance IEEE 1588 stack and servo Servo algorithm supports statistical packet selection0 us0 hrs2hrs/div Dynamically adjusts to changing network load conditions28 hrs Packet transit time across network can vary significantly Different delay for different routes Random packet buffering Sensitive to network load conditions Mitigates PDV effects Achieves 30ns max time error hop-hop Field-proven – deployed in Tier I networks for 5 years Unified software solution for clocks and modules ITU G.8273.2 and G.8261 compliance reports available Open-source LinuxPTP can’t compensate for variable loading11Silicon Labs Confidential
High Performance IEEE 1588 Servo Mitigates PDV Effects ITU G.8261 requires testing IEEE 1588 undernetwork load conditions Test equipment simulates network congestion load Maximum Time Interval Error (MTIE) and TimeDeviation (TDEV) are measures of network wandernoise AccuTimeTM servo algorithm supports statisticalpacket selection Dynamically adjusts to changing network loadconditions to mitigate PDV effects Open-source LinuxPTP servo uses simple PIcontroller No added intelligence for varying networkconditions, only the PI K-constants can be adjusted12Full suite of Calnex equipment for compliance testing 1M investment for compliance testSilicon Labs Confidential
vs LinuxPTP 1PPS TDEV PerformanceSilicon LabsPasses G.8261 RequirementsLinuxPTPFails G.8261 RequirementsMargin toSpec LimitExceedsSpecLimitFull compliance reports available upon request13Silicon Labs Confidential
Highly Differentiated TechnologyM U LT I S Y N T HDSPLLXOPhaseDetectorLoopFilterI N T E G R AT I O ase ErrorCancellationDSPLL Inner LoopfOUTeDivider Select(DIV1, DIV2)fINfINPhaseDetectorPhase&DetectorADC& TFrac-NDividerFrac-NDividerSiliconLabs ClockDSPLL Outer Loop #1DSPLL Outer Loop #2Any-frequency clock synthesis1 ppt control of phase edgeRemoves uneven clocking for frac 100 / 150 fs jitter for int / frac14Nested LC-VCO multiple DSPLLReplaces DPLLs and APLLsMinimizes crosstalk & powerEliminates VCXO & loop filterClock-tree-on-a-chipAny-frequency any-outputSingle-IC clocks and jitter cleanersIEEE1588 clocks eliminate JA clockSilicon Labs Confidential
The Silicon Labs IEEE 1588 Network Synchronizer Solution1. Silicon Labs IEEE 1588 StackSi5388Host Processor/SoC1588 SystemReference ClockTime Stamp Unit(Time of Day)1588 PPS Clock Extracts IEEE 1588 timestamps from Ethernet packets3IEEE 1588DSPLL DCO Interfaces with upstream master clocks Operates best master clock algorithm (BMCA) Sends 1588 data to servo on the Si5388 via SPIMAC2. Silicon Labs IEEE 1588 servo1588 Packets1Silicon LabsIEEE 1588 Stack Dedicated MCU servo inside Si5388DCO Commands1588 Time Stamp DataSilicon LabsIEEE 1588 Servo(MCU FW)2 Controls DCO with no host processor service required Configured via API/command line interface3. Silicon Labs IEEE 1588 DCO Generates system reference and 1 PPS clock 1ppt step resolution Proven DSPLL technology15Silicon Labs Confidential
Silicon Labs 1588 SolutionsNetworkSynchronizersWith 5G and other highSee:accuracy applications: Radio unit (RRH or NR) – Si5388/89 and Si538x wireless clocks Distributed unit (DU) – Si5388/89 Centralized unit / VRAN Datacenter NIC card – Si5388/89 Reference design using Xilinx MPSOC or RFSOC More reference designs plannedModules Aerospace & Defense, Video, HV power distribution, IndustrialAutomation Secondary markets: Test & Measurement, Medical, 4G small cells Doesn’t require customer knowledge of network synchronization Work well in applications with 100 Mbps or 1 Gbps Ethernet port16
Comprehensive Timing Portfolio Leader in high performance clocks and oscillators Frequency flexibility ultra-low jitter Best-in-class integration single IC clock trees Highly programmable with quick-turn samples17XO/VCXOClock GeneratorsClock BuffersSyncE/IEEE 1588Clocks, Modules,SoftwareJitter Attenuating ClocksWireless ClocksSilicon Labs Confidential
More IEEE 1588 information IEEE-1588 Timing Solutions: s AN1202: ITU-T Precision Time Protocol Grandmaster, Boundary Clock, and Slave Clock ation-notes/an1202-itut precision time protocol grandmaster.pdf AN1208: Choosing the Correct Oscillator to Meet Your IEEE 1588v2 Network SynchronizationHoldover Requirements eting solutions use AN1170: Holdover Using the Si5348 Network Synchronizer pdf Clockbuilder Pro: software/clockbuilderpro-software IEEE-1588 Whitepaper: ard Contact sales: icon Labs Confidential
Clock Talk – September Through JanuarySILICON LABS LIVEInternet Infrastructure andIndustrial Automation Tech TalksTopicDate (AMER/EMEA)9:00 CST/16:00 CETDate (APAC)10:30 HKTIEEE 1588 Timing Solutions for Non-Telecom ApplicationsTuesday, Sept 15Wednesday, Sept 16Clock Jitter Demystified and Jitter Requirements for 56/112 SerdesTuesday, Sept 29Wednesday, Sept 23Design Considerations When Selecting a XO/VCXO Clock Reference for 56G/112G SerDesTuesday, Oct 13Wednesday, Oct 14Stop Guessing, Use Silicon Labs Timing Tools to Build Your Clock TreeTuesday, Oct 27Wednesday, Oct 28Optimize Timing Solutions for High Speed FPGA and Application Processor DesignsTuesday, Nov 10Wednesday, Nov 11PCIe Gen 4/5/6 Specifications and Jitter Measurement ExplainedTuesday, Nov 17Wednesday, Nov 18Timing Solutions for 5G O-RAN SystemsTuesday, Dec 1Wednesday, Dec 2AECQ-100 Timing Products for Automotive ApplicationsTuesday, Jan 12Wednesday, Jan 13Timing Solutions for Open-Compute SystemsTuesday, Jan 26Wednesday, Jan 27Register for g-webinar-series
The Largest Smart Home Developer EventS E P T E M B E R 9 – 1 0, 2 0 2 0Immerse yourself in two days of technical training designedespecially for engineers, developers and productmanagers. Learn how to "Work With" ecosystems includingAmazon and Google and join hands-on classes on how tobuild door locks, sensors, LED bulbs and more.Don't miss out, register today!workswith.silabs.com
List of Acronyms PTP - Precision Time Protocol NTP – Network Time Protocol GPS – Global Positioning System GNSS – Global Navigation Satellite System BBU – Baseband Unit RRU – Remote Radio Unit GM – Grand Master BC – Boundary Clock SC – Slave Clock cTE – Constant Time Error dTE – Dynamic Time Error PDV – Packet Delay Variation TDEV – Time Deviation ToD – Time of Day SyncE – Synchronous Ethernet21Silicon Labs Confidential
Removes uneven clocking for frac 100 / 150 fs jitter for int / frac DSPLL Nested LC-VCO multiple DSPLL . Controls DCO with no host processor service required Configured via API/command line interface 3. Silicon Labs IEEE 1588 DCO . Doesn't require customer knowledge of network synchronization Work well in applications with 100 Mbps or .
