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Architectural overview2Architectural overviewThe following subsections provide an architectural overview of the i.MX RT1020 processor system.2.1Block diagramFigure 2 shows the functional modules in the i.MX RT1020 processor system1.System ControlCPU PlatformConnectivityARM Cortex-M7eMMC 4.5 / SD 3.0 x2Secure JTAGPLL / OSC16 KB D-cache16 KB I-cacheRTC and ResetFPUUART x8NVICMPUEnhanced DMA8 x 8 KeypadUp to 256 KB TCMIOMUXI2C x4GP Timer x6Quadrature ENC x2SPI x4External MemoryQuadTimer(4-Channel) x2FlexPWM(12-Channel) x2Watch Dog x4Internal Memory256 KB OCRAMshared with TCMFlexSPI (dual-Channel QuadSPINAND and NOR, Octal Flash, and RAM)GPIOI2S / SAI x3External Memory Controller8/16 bit SDRAMParallel NOR FlashNAND FlashPSRAM10 / 100 ENETwith IEEE 1588 x1HABPower ManagementFlexCAN x2USB2.0 OTG with PHYSecurity96 KB ROMS/PDIF Tx / RxDCDCADCCiphersRNGSecure RTCeFuseLDOTemp MonitorADC x2ACMP x4.Figure 2. i.MX RT1020 system block diagram1. Some modules shown in this block diagram are not offered on all derivatives. See Table 2 for details.i.MX RT1020 Crossover Processors for Consumer Products, Rev. 3.1, 03/2022NXP Semiconductors9

Modules list3Modules listThe i.MX RT1020 processors contain a variety of digital and analog modules. Table 3 describes thesemodules in alphabetical order.Table 3. i.MX RT1020 modules listBlock mnemonicBlock nameSubsystemBrief descriptionACMP1ACMP2ACMP3ACMP4Analog ComparatorAnalogThe comparator (CMP) provides a circuit for comparingtwo analog input voltages. The comparator circuit isdesigned to operate across the full range of the supplyvoltage (rail-to-rail operation).ADC1ADC2Analog to DigitalConverterAnalogThe ADC is a 12-bit general purpose analog to digitalconverter.AOIAnd-Or-InverterCross TriggerThe AOI provides a universal boolean functiongenerator using a four team sum of products expressionwith each product term containing true or complementvalues of the four selected inputs (A, B, C, D).ArmArm PlatformArmThe Arm Core Platform includes 1x Cortex-M7 core. Italso includes associated sub-blocks, such as NestedVectored Interrupt Controller (NVIC), Floating-PointUnit (FPU), Memory Protection Unit (MPU), andCoreSight debug modules.BEEBus Encryption EngineSecurityOn-The-Fly FlexSPI Flash DecryptionCCMGPCSRCClocks, Resets, and These modules are responsible for clock and resetClock Control Module,Power Controldistribution in the system, and also for the systemGeneral Powerpower management.Controller, System ResetControllerCSUCentral Security UnitSecurityThe Central Security Unit (CSU) is responsible forsetting comprehensive security policy within the i.MXRT1020 platform.DAPDebug Access PortSystem ControlPeripheralsThe DAP provides real-time access for the debuggerwithout halting the core to: System memory and peripheral registers All debug configuration registersThe DAP also provides debugger access to JTAG scanchains. The DAP module is internal to the Cortex-M7Core Platform.DCDCDCDC ConverterAnalogThe DCDC module is used for generating power supplyfor core logic. Main features are: Adjustable high efficiency regulator Supports 3.3 V input voltage Supports nominal run and low power standby modes Supports at 0.9 1.3 V output in run mode Supports at 0.9 1.0 V output in standby mode Over current and over voltage detectioni.MX RT1020 Crossover Processors for Consumer Products, Rev. 3.1, 03/202210NXP Semiconductors

Modules listTable 3. i.MX RT1020 modules list (continued)Block mnemonicBlock nameSubsystemBrief descriptioneDMAenhanced Direct Memory System ControlAccessPeripheralsThere is an enhanced DMA (eDMA) engine and twoDMA MUX. The eDMA is a 32 channel DMA engine, which iscapable of performing complex data transfers withminimal intervention from a host processor. The DMA MUX is capable of multiplexing up to 128DMA request sources to the 32 DMA channels ofeDMA.ENCQuadratureEncoder/DecoderTimer PeripheralsThe enhanced quadrature encoder/decoder moduleprovides interfacing capability to position/speedsensors. There are five input signals: PHASEA,PHASEB, INDEX, TRIGGER, and HOME. This moduleis used to decode shaft position, revolution count, andspeed.ENETEthernet ControllerConnectivityPeripheralsThe Ethernet Media Access Controller (MAC) isdesigned to support 10/100 Mbit/s Ethernet/IEEE 802.3networks. An external transceiver interface andtransceiver function are required to complete theinterface to the media. The module has dedicatedhardware to support the IEEE 1588 standard. See theENET chapter of the reference manual for details.EWMExternal WatchdogMonitorTimer PeripheralsThe EWM modules is designed to monitor externalcircuits, as well as the software flow. This provides aback-up mechanism to the internal WDOG that canreset the system. The EWM differs from the internalWDOG in that it does not reset the system. The EWM,if allowed to time-out, provides an independent triggerpin that when asserted resets or places an externalcircuit into a safe mode.FLEXCAN1FLEXCAN2Flexible Controller AreaNetworkConnectivityPeripheralsThe CAN protocol was primarily, but not only, designedto be used as a vehicle serial data bus, meeting thespecific requirements of this field: real-time processing,reliable operation in the Electromagnetic interference(EMI) environment of a vehicle, cost-effectiveness andrequired bandwidth. The FlexCAN module is a fullimplementation of the CAN protocol specification,Version 2.0 B, which supports both standard andextended message frames.FlexIO1Flexible Input/outputConnectivity andCommunicationsThe FlexIO is capable of supporting a wide range ofprotocols including, but not limited to: UART, I2C, SPI,I2S, camera interface, display interface, PWMwaveform generation, etc. The module can remainfunctional when the chip is in a low power modeprovided the clock it is using remain active.i.MX RT1020 Crossover Processors for Consumer Products, Rev. 3.1, 03/2022NXP Semiconductors11

Modules listTable 3. i.MX RT1020 modules list (continued)Block mnemonicBlock nameSubsystemBrief descriptionFlexPWM1FlexPWM2Pulse Width ModulationTimer PeripheralsThe pulse-width modulator (PWM) contains four PWMsub-modules, each of which is set up to control a singlehalf-bridge power stage. Fault channel support isprovided. The PWM module can generate variousswitching patterns, including highly sophisticatedwaveforms.FlexRAMRAMMemoriesThe i.MX RT1020 has 256 KB of on-chip RAM whichcould be flexible allocated to I-TCM, D-TCM, andon-chip RAM (OCRAM) in a 32 KB granularity. TheFlexRAM is the manager of the 256 KB on-chip RAMarray. Major functions of this blocks are: interfacing toI-TCM and D-TCM of Arm core and OCRAM controller;dynamic RAM arrays allocation for I-TCM, D-TCM, andOCRAM.FlexSPIQuad Serial PeripheralInterfaceConnectivity andCommunicationsFlexSPI acts as an interface to one or two externalserial flash devices, each with up to four bidirectionaldata lines.GPIO1GPIO2GPIO3GPIO5General Purpose I/OModulesSystem ControlPeripheralsUsed for general purpose input/output to external ICs.Each GPIO module supports up to 32 bits of I/O.GPT1GPT2General Purpose TimerTimer PeripheralsEach GPT is a 32-bit “free-running” or “set and forget”mode timer with programmable prescaler and compareand capture register. A timer counter value can becaptured using an external event and can be configuredto trigger a capture event on either the leading or trailingedges of an input pulse. When the timer is configured tooperate in “set and forget” mode, it is capable ofproviding precise interrupts at regular intervals withminimal processor intervention. The counter has outputcompare logic to provide the status and interrupt atcomparison. This timer can be configured to run eitheron an external clock or on an internal clock.KPPKeypad PortHuman MachineInterfacesThe KPP is a 16-bit peripheral that can be used as akeypad matrix interface or as general purposeinput/output (I/O). It supports 8 x 8 external key padmatrix. Main features are: Multiple-key detection Long key-press detection Standby key-press detection Supports a 2-point and 3-point contact key matrixLPI2C1LPI2C2LPI2C3LPI2C4Low PowerInter-integrated CircuitConnectivity andCommunicationsThe LPI2C is a low power Inter-Integrated Circuit (I2C)module that supports an efficient interface to an I2C busas a master.The I2C provides a method of communication betweena number of external devices. More detailedinformation, see Section 4.8.2, LPI2C module timingparameters.i.MX RT1020 Crossover Processors for Consumer Products, Rev. 3.1, 03/202212NXP Semiconductors

Modules listTable 3. i.MX RT1020 modules list (continued)Block mnemonicBlock nameSubsystemBrief descriptionLPSPI1LPSPI2LPSPI3LPSPI4Low Power SerialPeripheral InterfaceConnectivity andCommunicationsThe LPSPI is a low power Serial Peripheral Interface(SPI) module that support an efficient interface to anSPI bus as a master and/or a slave. It can continue operating while the chip is in stopmodes, if an appropriate clock is available Designed for low CPU overhead, with DMA offloading of FIFO register UART7LPUART8UART InterfaceConnectivityPeripheralsEach of the UART modules support the following serialdata transmit/receive protocols and configurations: 7- or 8-bit data words, 1 or 2 stop bits, programmableparity (even, odd or none) Programmable baud rates up to 20 Mbps.MQSMedium Quality SoundMultimediaPeripheralsMQS is used to generate 2-channel medium qualityPWM-like audio via two standard digital GPIO pins.QuadTimer1QuadTimer2QuadTimerTimer PeripheralsThe quad-timer provides four time channels with avariety of controls affecting both individual andmulti-channel features.Specific features includeup/down count, cascading of counters, programmablemodule, count once/repeated, counter preload,compare registers with preload, shared use of inputsignals, prescaler controls, independentcapture/compare, fault input control, programmableinput filters, and multi-channel synchronization.ROMCPROM Controller withPatchMemories andThe ROMCP acts as an interface between the ArmMemory Controllers advanced high-performance bus and the ROM. Theon-chip ROM is only used by the Cortex-M7 core duringboot up. Size of the ROM is 96 KB.RTC OSCReal Time ClockOscillatorClock Sources andControlThe RTC OSC provides the clock source for theReal-Time Clock module. The RTC OSC module, inconjunction with an external crystal, generates a 32.768kHz reference clock for the RTC.RTWDOGWatch DogTimer PeripheralsThe RTWDG module is a high reliability independenttimer that is available for system to use. It provides asafety feature to ensure software is executing asplanned and the CPU is not stuck in an infinite loop orexecuting unintended code. If the WDOG module is notserviced (refreshed) within a certain period, it resets theMCU. Windowed refresh mode is supported as well.SAI1SAI2SAI3Synchronous AudioInterfaceMultimediaPeripheralsThe SAI module provides a synchronous audiointerface (SAI) that supports full duplex serial interfaceswith frame synchronization, such as I2S, AC97, TDM,and codec/DSP interfaces.SA-TRNGStandalone True Random SecurityNumber GeneratorThe SA-TRNG is hardware accelerator that generatesa 512-bit entropy as needed by an entropy consumingmodule or by other post processing functions.i.MX RT1020 Crossover Processors for Consumer Products, Rev. 3.1, 03/2022NXP Semiconductors13

Modules listTable 3. i.MX RT1020 modules list (continued)Block mnemonicBlock nameSubsystemBrief descriptionSEMCSmart External MemoryControllerMemory andMemory ControllerThe SEMC is a multi-standard memory controlleroptimized for both high-performance and low pin-count.It can support multiple external memories in the sameapplication with shared address and data pins. Theinterface supported includes SDRAM, NOR Flash,SRAM, and NAND Flash, as well as 8080 displayinterface.SJCSystem JTAG ControllerSystem ControlPeripheralsThe SJC provides JTAG interface, which complies withJTAG TAP standards, to internal logic. The i.MXRT1020 processors use JTAG port for production,testing, and system debugging. In addition, the SJCprovides BSR (Boundary Scan Register) standardsupport, which complies with IEEE1149.1 andIEEE1149.6 standards.The JTAG port is accessible during platform initiallaboratory bring-up, for manufacturing tests andtroubleshooting, as well as for software debugging byauthorized entities. The i.MX RT1020 SJC incorporatesthree security modes for protecting againstunauthorized accesses. Modes are selected througheFUSE configuration.SNVSSecure Non-VolatileStorageSecuritySecure Non-Volatile Storage, including Secure RealTime Clock, Security State Machine, and Master KeyControl.SPDIFSony Philips DigitalInterconnect FormatMultimediaPeripheralsA standard audio file transfer format, developed jointlyby the Sony and Phillips corporations. Has Transmitterand Receiver functionality.Temp MonitorTemperature MonitorAnalogThe temperature sensor implements a temperaturesensor/conversion function based on atemperature-dependent voltage to time conversion.USBO2Universal Serial Bus 2.0ConnectivityPeripheralsUSBO2 (USB OTG1) contains: One high-speed OTG 2.0 module with integrated HSUSB PHY Support eight Transmit (TX) and eight Receive (Rx)endpoints, including endpoint 0i.MX RT1020 Crossover Processors for Consumer Products, Rev. 3.1, 03/202214NXP Semiconductors

Modules listTable 3. i.MX RT1020 modules list (continued)Block mnemonicBlock nameSubsystemBrief descriptionuSDHC1uSDHC2ConnectivitySD/MMC and SDXCPeripheralsEnhanced Multi-MediaCard / Secure Digital HostControlleri.MX RT1020 specific SoC characteristics:All four MMC/SD/SDIO controller IPs are identical andare based on the uSDHC IP. They are: Fully compliant with MMC command/response setsand Physical Layer as defined in the MultimediaCard System Specification, v4.5/4.2/4.3/4.4/4.41/including high-capacity (size 2 GB) cards HCMMC. Fully compliant with SD command/response setsand Physical Layer as defined in the SD MemoryCard Specifications, v3.0 including high-capacitySDXC cards up to 2 TB. Fully compliant with SDIO command/response setsand interrupt/read-wait mode as defined in the SDIOCard Specification, Part E1, v3.0Two ports support: 1-bit or 4-bit transfer mode specifications for SD andSDIO cards up to UHS-I SDR104 mode (104 MB/smax) 1-bit, 4-bit, or 8-bit transfer mode specifications forMMC cards up to 52 MHz in both SDR and DDRmodes (104 MB/s max) 4-bit transfer mode specifications for eMMC chips upto 100 MHz in HS200 mode (100 MB/s max)WDOG1WDOG2Watch DogTimer PeripheralsThe Watch Dog Timer supports two comparison pointsduring each counting period. Each of the comparisonpoints is configurable to evoke an interrupt to the Armcore, and a second point evokes an external event onthe WDOG line.XBARCross BARCross TriggerEach crossbar switch is an array of muxes with sharedinputs. Each mux output provides one output of thecrossbar. The number of inputs and the number ofmuxes/outputs are user configurable and registers areprovided to select which of the shared inputs are routedto each output.i.MX RT1020 Crossover Processors for Consumer Products, Rev. 3.1, 03/2022NXP Semiconductors15

Modules list3.1Special signal considerationsTable 4 lists special signal considerations for the i.MX RT1020 processors. The signal names are listed inalphabetical order.The package contact assignments can be found in Section 6, Package information and contactassignments.” Signal descriptions are provided in the i.MX RT1020 Reference Manual(IMXRT1020RM).Table 4. Special signal considerationsSignal nameRemarksDCDC PSWITCHPAD is in DCDC IN domain and connected the ground to bypass DCDC.To enable DCDC function, assert to DCDC IN with at least 1ms delay for DCDC IN rising edge.RTC XTALI/RTC XTALOIf the user wishes to configure RTC XTALI and RTC XTALO as an RTC oscillator, a 32.768 kHzcrystal, ( 100 k ESR, 10 pF load) should be connected between RTC XTALI and RTC XTALO.Keep in mind the capacitors implemented on either side of the crystal are about twice the crystalload capacitor. To hit the exact oscillation frequency, the board capacitors need to be reduced toaccount for board and chip parasitics. The integrated oscillation amplifier is self biasing, butrelatively weak. Care must be taken to limit parasitic leakage from RTC XTALI and RTC XTALOto either power or ground ( 100 M ). This will debias the amplifier and cause a reduction ofstartup margin. Typically RTC XTALI and RTC XTALO should bias to approximately 0.5 V.If it is desired to feed an external low frequency clock into RTC XTALI the RTC XTALO pin mustremain unconnected or driven with a complimentary signal. The logic level of this forcing clockshould not exceed VDD SNVS CAP level and the frequency should be 100 kHz under typicalconditions.In case when high accuracy real time clock are not required system may use internal lowfrequency ring oscillator. It is recommended to connect RTC XTALI to GND and keepRTC XTALO unconnected.XTALI/XTALOA 24.0 MHz crystal should be connected between XTALI and XTALO. External load capacitancevalue depends on the typical load capacitance of crystal used and PCB design.The crystal must be rated for a maximum drive level of 250 W. An ESR (equivalent seriesresistance) of typical 80 is recommended. NXP SDK software requires 24 MHz onXTALI/XTALO.The crystal can be eliminated if an external 24 MHz oscillator is available in the system. In thiscase, XTALO must be directly driven by the external oscillator and XTALI mounted with 18 pFcapacitor. The logic level of this forcing clock cannot exceed NVCC PLL level.If this clock is used as a reference for USB, then there are strict frequency tolerance and jitterrequirements. See OSC24M chapter and relevant interface specifications chapters for details.GPANAIOThis signal is reserved for NXP manufacturing use only. This output must remain unconnected.JTAG nnnnThe JTAG interface is summarized in Table 5. Use of external resistors is unnecessary. However,if external resistors are used, the user must ensure that the on-chip pull-up/down configuration isfollowed. For example, do not use an external pull down on an input that has on-chip pull-up.JTAG TDO is configured with a keeper circuit such that the non-connected condition is eliminatedif an external

2018-2022 NXP B.V. 1 i.MX RT1020 introduction . - 4-channel generic 16-bit resolution timer each - Each support standard capture and compare operation - Quadrature decoder integrated . 4MB Flash SIP 4 Enhanced Feature 5 Far Field AFE A Facial Recognition F Local Voice Control (audio input models) L .