Transcription
Basic EmbeddedSystem DesignTutorialusing MICROBLAZE and ZYNQ-7000 AP SOC embeddedprocessors to design two frequencies PWM modulatorsystemJanuary 17, 2017
Contents1INTRODUCTION11.1Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11.2Purpose of this tutorial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11.3Objectives of this tutorial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11.4One possible solution for the modulator design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21.4.1Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31.4.2Design Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Embedded Design Process Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111.523CREATING THE HARDWARE PLATFORM132.1Create a New Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132.2Vivado Integrated Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172.3Create MicroBlaze-based hardware platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192.4Create ARM-based hardware platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .492.5Create a socius board based hardware platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60CREATING THE SOFTWARE PLATFORM USING SDK833.1Board Support Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .853.2Creating an application project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .873.3Creating a C/C source files for MicroBlaze-based processor system . . . . . . . . . . . . . . . . . . .903.4Creating a C/C source files for ARM-based processor system . . . . . . . . . . . . . . . . . . . . . . .993.5Creating a C/C source files for a socius board based hardware platform . . . . . . . . . . . . . . . . . 1053.6Viewing and configuring Linker Script file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1113.7Building application and generating ELF file3.8Running Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1153.94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133.8.1Downloading MicroBlaze-based bitstream file . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1163.8.2Downloading ARM-based bitstream fileApplication Debugging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213.9.1Debug Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223.9.2Debug Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1233.9.3Debug Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126DEBUGGING SYSTEM USING VIVADO LOGIC ANALYZER4.1135Illustration of using Vivado Logic Analyzer tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
CONTENTS4.25Illustration of using Vivado Logic Analyzer together with SDK Debugger . . . . . . . . . . . . . . . . . . . 149USING CUSTOM IPS IN EMBEDDED SYSTEM DESIGN1575.1Using custom IP in MicroBlaze-based processor system . . . . . . . . . . . . . . . . . . . . . . . . . . . 1585.2Using custom IP in ARM-based processor system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1715.3Developing a device driver for the custom IP core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1755.3.1Device driver for PWM Modulator IP core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1755.3.2Creating Xilinx driver file and folder structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1806CONCLUSION1877EXERCISES191Indexii192
List of Figures1.1Example of the PWM signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21.2Sine wave with 256 samples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21.3Structure of microprocessor-based embedded system that will be used in tutorial . . . . . . . . . . . . . .41.4MicroBlaze core block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51.5Zynq-7000 AP SoC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61.6UART block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71.7AXI Timer core block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81.8AXI INTC core block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91.9AXI GPIO block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101.10 Design steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111.11 Typical embedded design process flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122.1The Vivado Getting Started page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132.2Create a New Vivado Project dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142.3Project Name dialog box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142.4Project Type dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152.5Default Part dialog box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162.6New Project Summary dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162.7Vivado IDE Viewing Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172.8Vivado IDE Default Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182.9Project Summary View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192.10 Create Block Design option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202.11 Create Block Design dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202.12 Vivado IDE with a blank design canvas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212.13 Add IP option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212.14 Add IP link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212.15 Add IP button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222.16 MicroBlaze core in the IP Catalog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222.17 Automatically instantiated MicroBlaze core in the IP Integrator design canvas . . . . . . . . . . . . . . . .232.18 IP Integrator design canvas with instantiated IPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232.19 Run Block Automation dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242.20 A basic system design created by the Block Automation feature . . . . . . . . . . . . . . . . . . . . . . .252.21 Run Connection Automation dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
LIST OF FIGURESiv2.22 Re-customize IP - AXI GPIO (2.0) dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272.23 Re-customize IP - Clocking Wizard (5.1) dialog box. . . . . . . . . . . . . . . . . . . . . . . . . . . . .282.24 Run Connection Automation dialog box for axi gpio 0 - GPIO interface . . . . . . . . . . . . . . . . . .292.25 Re-customize IP - Constant (1.1) dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302.26 Re-customize IP - Processor System Reset (5.0) dialog box . . . . . . . . . . . . . . . . . . . . . . . . .312.27 Final Block Diagram of our design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312.28 Validate Design option from the main menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322.29 Validate Design button from the main toolbar menu. . . . . . . . . . . . . . . . . . . . . . . . . . . . .322.30 Validate Design dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322.31 Project Settings dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332.32 Create HDL Wrapper option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332.33 Create HDL Wrapper dialog box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332.34 Sources window with generated HDL wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342.35 modulator mb wrapper.vhd source file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342.36 Block diagram of the modulator wrapper.vhd file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352.37 Add Sources command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362.38 Add Sources dialog box - add or create design sources option . . . . . . . . . . . . . . . . . . . . . . . .362.39 Add or Create Design Sources dialog box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .372.40 Add Source Files dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .372.41 Add or Create Design Sources dialog box - with added files . . . . . . . . . . . . . . . . . . . . . . . . .382.42 Sources view with new wrapper file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382.43 IO Planning layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392.44 I/O Planning View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392.45 I/O Ports tab with assigned pin locations and I/O standards . . . . . . . . . . . . . . . . . . . . . . . . .402.46 Properties window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402.47 Created modulator wrapper constraints file in the Sources window . . . . . . . . . . . . . . . . . . . . .412.48 modulator wrapper.xdc file with physical constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . .412.49 Timing Constraints option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422.50 Timing Constraints window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .432.51 Create Clock dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .442.52 Specify Clock Source Objects dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .452.53 Create Clock dialog box after specifying the period for the clk p . . . . . . . . . . . . . . . . . . . . . . .462.54 Timing Constraints window with the create clock constraint . . . . . . . . . . . . . . . . . . . . . . . . .472.55 modulator wrapper.xdc file with physical and timing constraints . . . . . . . . . . . . . . . . . . . . . . .482.56 Run Synthesis, Run Implementation and Generate Bitstream commands from the Vivado Flow Navigator .492.57 Create Block Design dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .502.58 Zynq7 Processor core in the IP Catalog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .502.59 Automatically instantiated Zynq7 Processor core in the IP Integrator design canvas . . . . . . . . . . . . .502.60 IP Integrator design canvas with all three instantiated IPs . . . . . . . . . . . . . . . . . . . . . . . . . .512.61 Zynq-7 Run Block Automation dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .522.62 Zynq-7000 AP SoC Processing System after Running Block Automation . . . . . . . . . . . . . . . . . .52
LIST OF FIGURES2.63 Re-customize IP - AXI GPIO (2.0) dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .532.64 Zynq-7000 AP SoC Processing System after Running Connection Automation . . . . . . . . . . . . . . .542.65 Re-customize IP - ZYNQ7 Processing System (5.5) dialog box. . . . . . . . . . . . . . . . . . . . . . .552.66 Re-customize IP - Constant (1.1) dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .562.67 Re-Customize IP - Processor System Reset (5.0) dialog box . . . . . . . . . . . . . . . . . . . . . . . . .572.68 Final Block Diagram of our design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .572.69 Sources window with generated HDL wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .582.70 I/O Planning layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .582.71 I/O Planning view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .592.72 Run Implementation and Generate Bitstream commands from the Vivado Flow Navigator. . . . . . . . .59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .612.75 Vivado IDE Viewing Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .612.76 Sources view with added new files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .662.77 Sources view with added constraints file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .682.78 Tcl Console window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .822.79 Block diagram of Zynq PS configured to run on socius board. . . . . . . . . . . . . . . . . . . . . . . .823.1SDK application development flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .833.2Export Hardware dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .843.3Launch SDK dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .843.4SDK main window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .853.5Board Support Package option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .863.6New Board Support Package Project dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .863.7Board Support Package Settings dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .873.8Application Project dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .883.9Templates dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .893.10 SDK main window after C project creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .903.11 New Source File dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .912.73 Project Name dialog box2.74 Default Part dialog box3.12 Adding math library to Libraries list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013.13 Added math library to Libraries list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013.14 Linking and Locating process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1113.15 Linker and Locator Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1123.16 Generate linker script dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1123.17 SDK Software Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133.18 Console window with code size information for the modulator no intc build configuration for MicroBlazebased system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1143.19 Console window with code size information for the modulator no intc build configuration for ARM-basedsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1143.20 Run Workflow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1163.21 Program FPGA option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173.22 Program FPGA dialog box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117v
LIST OF FIGURES3.23 Program FPGA flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1183.24 Program FPGA diloag box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193.25 SDK Terminal window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193.26 Connect to serial port dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1203.27 Terminal notification about successful connection to serial port. . . . . . . . . . . . . . . . . . . . . . . 1203.28 Terminal window with messages sent by software application . . . . . . . . . . . . . . . . . . . . . . . . 1203.29 Terminal window with messages sent by software application after changing the switch position on thedevelopment board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213.30 GDB overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213.31 Debug Workflow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223.32 Debug Configurations option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1233.33 Creating a new configuration of the selected type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1243.34 Automatically generated “modulator no intc Debug by the SDK” configuration . . . . . . . . . . . . . . . 1243.35 Application tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1253.36 Open Perspective button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1253.37 Open Perspective dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263.38 SDK Debug Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273.39 Result of the execution of the Step Into command on the XGpio Initialize function. . . . . . . . . . . . . 1273.40 Result of Step Return command execution within XGpio Initialize function . . . . . . . . . . . . . . . . . 1283.41 Result of the execution of the Step Over command on the XGpio SetDataDirection function . . . . . . . . 1283.42 Add Breakpoint option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1293.43 Properties for C/C Line Breakpoint dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1293.44 Breakpoint added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1303.45 Breakpoint reached . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1303.46 Starting address of the sine ampl array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1303.47 Monitor Memory dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1313.48 Content of the sine ampl array in Memory window before array initialization . . . . . . . . . . . . . . . . . 1313.49 Change of i variable value indication in the Variables tab . . . . . . . . . . . . . . . . . . . . . . . . . . . 1313.50 Indication of the change of the sine ampl value in Memory window . . . . . . . . . . . . . . . . . . . . . 1323.51 Properties for C/C Line Breakpoint dialog box - condition breakpoint setup i 5 . . . . . . . . . . . . . 1323.52 Conditional breakpoint added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1333.53 Conditional breakpoint reached, i 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133vi4.1Finial Block Diagram of our design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1364.2Mark Debug option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1364.3Set Up Debug button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1374.4Tools - Set Up Debug option4.5Set Up Debug dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1384.6Nets to Debug dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1384.7Find Nets dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1394.8Remove Nets option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1394.9ILA Core Options dialog box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
LIST OF FIGURES4.10 Set Up Debug Summary dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1404.11 Netlist window with generated ILA core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1414.12 Run Implementation and Generate Bitstream options4.13 Program FPGA dialog box. . . . . . . . . . . . . . . . . . . . . . . . . . . . 141. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1424.14 Open Hardware Manager command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1424.15 Open Hardware Target dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1434.16 Hardware Server Settings dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1434.17 Select Hardware Target dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1444.18 Open Hardware Target Summary dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1444.19 Hardware view after opening a connection to the hardware target . . . . . . . . . . . . . . . . . . . . . . 1454.20 ILA Dashboard window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1454.21 Create new trigger state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1464.22 Trigger FSM code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1474.23 Insert Probe window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1474.24 Trigger FSM State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1484.25 Captured waveform after trigger condition is reached . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1484.26 Breakpoint tab - Remove option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1494.27 Added Breakpoint at line 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1494.28 Properties for C/C Line Breakpoint dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1504.29 Debug Probes option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1504.30 Add Probes to Basic Trigger Setup option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1514.31 Added probes to the ILA Basic Trigger Setup window. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1514.32 Value dialog box for the microblaze 0 dlmb 1 ABUS[0:31] ILA debug probe . . . . . . . . . . . . . . . . 1524.33 Value dialog box for the microblaze 0 dlmb 1 WRITESTROBE ILA debug probe . . . . . . . . . . . . . . 1524.34 ILA Properties window after arming trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1534.35 Add Probes to Waveform option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1544.36 Waveform window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1544.37 Memory tab with data value on the memory address 0xA690. . . . . . . . . . . . . . . . . . . . . . . . 1555.1Structure of microprocessor-based embedded system, using a custom IP to generate pwm signal . . . . . 1575.2Repository Manager window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1595.3Add Repository dialog box5.4Repository Manager with selected ip repository . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1605.5IP Catalog with added modulator axi ip v1.0 IP core . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1605.6IP Integrator design canvas with instantiated IPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1615.7Re-customize IP - modulator axi ip v1.0 (1.0) dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . 1615.8A basic MicroBlaze-based system design created by the Block Automation feature . . . . . . . . . . . . . 1625.9Re-customize IP - AXI GPIO (2.0) dialog box - Board tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159. . . . . . . . . . . . . . . . . . . . . . . . . . 1635.10 Re-customize IP - AXI GPIO (2.0) dialog box - IP Configuration tab . . . . . . . . . . . . . . . . . . . . . 1645.11 Re-customize IP - Clocking Wizard (5.1) dialog box - Clocking Options tab . . . . . . . . . . . . . . . . . 1655.12 Re-customize IP - Clocking Wizard (5.1) dialog box - Output Clocks tab . . . . . . . . . . . . . . . . . . . 1665.13 A basic MicroBlaze-based system design after running Connection Automation feature . . . . . . . . . . . 166vii
LIST OF FIGURES5.14 Re-customize IP - Constant (1.1) dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1675.15 Re-Customize IP - Processor System Reset (5.0) dialog box . . . . . . . . . . . . . . . . . . . . . . . . . 1675.16 Final Block Diagram of the modulator axi mb block design . . . . . . . . . . . . . . . . . . . . . . . . . 1685.17 Re-customize IP - Processor System Design (5.0) dialog box - values of the External and Auxillary resetafter design validation process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1695.18 Sources window with created modulator axi mb wrapper.xdc constraints file . . . . . . . . . . . . . . . . 1705.19 IP Integrator design canvas with instantiated IPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1725.20 Zynq-7000 AP SoC Processing System after Running Block Automation . . . . . . . . . . . . . . . . . . 1735.21 Zynq-7000 AP SoC Processing System after Running Connection Automation . . . . . . . . . . . . . . . 1745.22 Final Block Diagram of the modulator axi arm block design . . . . . . . . . . . . . . . . . . . . . . . . . 1745.23 Required folder structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1805.24 Preferences dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1835.25 Browse For Folder dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1835.26 Board Support Package Settings dialog box with selected modulator axi ip custom driver . . . . . . . . . 184viii
List of Tables
Chapter 1INTRODUCTION1.1MotivationBasic Embedded System Design Tutorial is a document made for beginners who are entering the embedded system designusing FPGAs. This tutorial explains, step by step, the procedure of designing a simple digital system using C language andXilinx Vivado Design Suite.1.2Purpose of this tutorialThis tutorial is made to introduce you how to create and test an project and run it on your development board.After completing this tutorial, you will be able to: Launch and navigate the Vivado Integrated Design Environment (IDE) Create a MicroBlaze and Zynq-7000 AP SoC processor system project using Vivado IP Integrator tool Synthesize and implement the design in the Vivado IDE Export a hardware description XML file for later software development Create and debug your software application using SDK tool Generate the hardware implementation bitstream file and download it to the target Xilinx development board Debug a design in hardware using Vivado Logic AnalyzerThe following project is designed for: Designing Surface: VIVADO 2016.4 Programming Language: C Device: Xilinx ZedBoard Zynq Evaluation and Development Platform1.3Objectives of this tutorialIn this tutorial a PWM signal modulated using the sine wave with two different frequencies (1 Hz and 3.5 Hz) will becreated. Frequency that will be chosen depends on the position of the two-state on-board switch (sw0).PWM SignalPulse-width modulation (PWM) uses a re
Basic Embedded System Design Tutorial using MICROBLAZE and ZYNQ-7000 AP SOC embedded processors to design two frequenci
