WIXLIB

SystemVerilog Industry's first unified HDVL (Hw Description and Verificationlanguage (IEEE 1800)Major extension of Verilog language (IEEE 1364)Targeted primarily at the chip implementation and verificationflowImprove productivity in the design of large gate-count, IPbased, bus-intensive chips

Sources and references1. Accellera IEEE SystemVerilog pagehttp://www.systemverilog.com/home.html2. “Using SystemVerilog for FPGA design. A tutorial based on a simple bussystem”, A/3. “SystemVerilog for Design groups”, Slides from Doulos training course4. Various tutorials on SystemVerilog on Doulos website5. “SystemVerilog for VHDL Users”, Tom Fitzpatrick, Synopsys PrincipalTechnical Specialist, 04 systemverilog.pdf6. “SystemVerilog, a design and synthesis perspective”, K. Pieper, SynopsysR&D Manager, HDL Compilers7. Wikipedia

Extensions to Verilog Improvements for advanced design requirements––– Properties and assertions built in the language– Assertion Based Verification, Design for VerificationNew features for verification––– Data typesHigher abstraction (user defined types, struct, unions)InterfacesModels and testbenches using object-oriented techniques (class)Constrained random test generationTransaction level modelingDirect Programming Interface with C/C /SystemC–Link to system level simulations

Data types: logic Nets and Variables Net type, Data typeVariables Data typemodule counter (input logic clk,reset,enable,output logic q);logic [7:0] count;assign q count[7]; New logic 4-state datatype (synonym for reg)Ports can be variablesVariables can be assignedin continuous statementsalways @(posedge clk or posedgereset)beginif (reset 1'b1)count 0;else if (enable 1'b1)count count 1'b1;end Built-in: byte, shortint,int, longintendmodule: counter

Packed and unpacked arrays Multidimensional packedarrays unify and extendnotion of registers andmemorieslogic [3:0][7:0] qBytes [0:15][1:3];unpackedpacked.Qbytes[0][1][3][7] 1'b1;unpackedpacked

Array querying functionslogic [7:0] qBytes [0:15][1:3];31 dimensions(qBytes)23 unpacked dimensions(qBytes) left(qBytes)2 left(qBytes,2)0 right(qBytes,2) right(qBytes,3)3 low(qBytes,2)0 high(qBytes,2)1 size(qBytes,3)1 size(qBytes,2)8 increment(qBytes,1) increment(qBytes,3)33-11 bits(qBytes)512

User defined typeslogic [3:0][7:0] qBytes [0:15][1:3]; User defined types withtypedef Higher levelabstraction Design intenttypedef logic [7:0] octet t;typedef octet t [3:0] quadOctet t;typedef qBytes t quadOctet t [0:15][1:3];qBytes t qBytes ;.Qbytes[0][1] 32'hFFFFFFF;Qbytes[0][1][2] 8'hAA;Qbytes[0][2][3][7] 1'b1;

Enum

SystemVerilog Structtcp t mypkt; mypkt.source port 16'hAAAA;mypkt.dest port 16'hBBBB;63310

Design hierarchymodule counter(input logicclk,reset,enable,output logic q);// Creating a hierarchy inSystemVerilog is simpler( less typing) than inVerilog Use variables, no need of wires Implicit port connectionsCODE HERE!endmodule: countermodule top(input logic clk, reset, enable,output logic RE,output logic WE,output types::addr t addr,output types::rdata t rdata,output types::wdata t wdata);logic en data gen, en data gen b, q;Counter INST C0(.clk, .reset, .enable,.q(en data gen));Counter INST C1(.*); // NOT RECOMMENDED!endmodule: top

Packagespackage types;typedef logic [7:0] wdata t;typedef struct packed {logic [3:0] data h;logic [3:0] data l; }wdata struct t;endpackage: typesAllows sharing of: nets, variables, types, tasks, functions classes, extern constraints, externmethods parameters, localparams, spec params properties, sequencesUnambiguous references to shareddeclarations Built-in functions and types included in stdpackage Groups of files can be compiled separately

Enabling efficient coding: exampleChannel INST LEFTcontrol INST CTRLChannel INST RIGHT

Enabling efficient coding: exampleChannel INST LEFTcontrol INST CTRLChannel INST RIGHT

Adding a signal can require editing through the fullhierarchymodule top(input logic clk,reset);logic [1:0] cfga, cfgb, cfgc, cfgd;control INST ,.cfgd(cfgd));channel INST (cfgc[0]),.cfgd(cfgd[0]));channel INST c(cfgc[1]),.cfgd(cfgd[1]));endmodule : top

SystemVerilog ports support struct typespackage types;typedef struct {logic cfga;logic cfgb;logic cfgc;logic cfgd;} configGroup t;endpackage: typesmodule top(input logic clk);import types::*;configGroup t cfg [1:0];control INST CTRL(.clk,.cfg);module control(input logic clk,output types::configGroup t cfg [1:0]);// endmodule: controlmodule channel(input logic clk,input types::configGroup t cfg);// endmodule: channelchannel INST LEFT(.clk,.cfg(cfg[0]));channel INST RIGHT(.clk,.cfg(cfg[1]));endmodule : topGrouping signals and port with struc types enable avoiding editingthrough the full hierarchy

Catch design intent:always {comb,latch,ff}always ff @(posedge clk or posedgereset)beginif (reset 1'b1)count 0;elseif (enable 1'b1) count count 1'b1;end

Example basic design

Interfaces are much more than sets ofgrouped variables (signals) SystemVerilog interface can have ports and contain variablesand processes (like a module)It can connect to a module port (unlike a module)An interface that represents all of the wires within an on-chipbus only requires a single port connection to each master andslave on the busmodports within the interface allow master ports and slaveports to have different characteristics

Conclusions on design extensions SystemVerilog raises abstraction level––– Currently using Verilog for design?–– clear advantages in updating to SystemVerilogbackwards compatible with all existing VerilogCurrently using VHDL?– Productivity improves3x to 5x code size reductionBetter and faster verification with synthesiseffort switching to SystemVerilog justified? If your designscontain on-chip multiplexed busses with multiple masters andslaves, it probably isJust starting out?–it makes sense to choose SystemVerilog as first designlanguage to learn

Extensions to Verilog Improvements for advanced design requirements––– Properties and assertions built in the language (SVA)– Assertion Based Verification, Design for VerificationNew features for verification––– Data typesHigher abstraction (user defined types, struct, unions)InterfacesModels and testbenches using object-oriented techniques (class)Transaction level modelingConstrained random test generationDirect Programming Interface with C/C /SystemC–Link to system level simulations

Assertions0123456readwritereqackassert property (read and write cannot be asserted simultaneouslyread or write cannot be asserted when req is notasserted@(posedge clk)!(read && write) );assert property ( @(posedge clk)!((read write) && !req) );ack must be active 1, 2 or 3 clock cycles after reqack must change to active 1, 2 or 3 clock cycles afterreq changes to activeassert property ( @(posedge clk)req ##[1:3] ack );assert property ( @(posedge clk) rose(req) ##[1:3] rose(ack));

Sequences, properties, assertionsproperty not read and write;@(posedge clk) not (read && write);endpropertyassert property (not read and write);sequence requestreq;endsequencesequence acknowledge##[1:3] Ack;endsequenceproperty handshake;@(posedge clk) request acknowledge;endproperty// property built from sequences and// implication operators , assert property (handshake);// instruct simulator to react on verificationcover property (handshake);// instruct simulator to count verification

Binding to existing modulesmodule MyDevice (.);// The design is modelled hereendmodule program MyDevice assertions(.);// sequences, properties, assertions for M go hereendprogram bind MyDevice MyDevice assertions INST MYDEVICE ASSERTIONS (.);Equivalent to:module MyDevice (.);// The design is modelled hereprogram MyDevice assertions(.);// sequences, properties, assertions for M go hereEndprogramMyDevice assertions INST MYDEVICE ASSERTIONS (.);endmodule

Classes Classes are the foundation of the testbenchautomation languageClasses are used to model data Data values can be created as part ofthe constrained random methodologyrand keyword for data members that can berandomizedSystemVerilog has dynamic arraysTasks to manipulate structured data are classmembersclass CAN Message;rand struct packed {bit [10:0] ID;bitRTR;bit [1:0] rsvd;bit [3:0] DLC;bytedata[];bit [14:0] CRC;} message;////////////11 bit identifierreply required?"reserved for expansion" bits4 bit Data Length Codedata payload15 bit checksumtask set RTR (bit new value);// Set the RTR bit as requestedmessage.RTR new value;if (message.RTR) begin// Messages with the RTR bit set should have no data.message.DLC 0;clear data(); // make the data list emptyendendtasktask clear data; . endtask constraint keyword to describe propertiesof data fieldsconstraint c1 { message.DLC inside {[0:8]}; }constraint c2 { message.data.size() DLC; }endclass

Testbench with classesmodule CAN Message tb;CAN message test message[10]; //unpacked array of 10 CAN message objectslogic SerialIn;MyModule INST DUT (.clk, .SerialIn); initialbegin// initialize the 10 messages with random data:for (int i 0; i 10; i )test message[i].randomize();// randomize first and second message again with additional constrainttest message[0].randomize with { message.DCL 4; };test message[1].randomize with { message.DCL 8; };for (int msgCount message.size() 1; msgCount 0; msgCount )for (int i test message[0].message.size() 1; i 0; i )begin@(posedge clk) SerialIn test message[msgCount].message[i];endendendmodule

Functional coverageenum {Red, Green, Blue} Colour; logic [3:0] x, y;covergroup cg Colour @(posedge clock);Instruct simulator to buildhistograms of valuestaken by variablescoverpoint Colour;Endgroup covergroup cg xy @(posedge clock);Histogram pair (triples.)of valuesX : coverpoint x;Y : coverpoint y;XY : cross X, Y;endgroup Control binningHistograms of transitions– State machines

Standard CERN PC, large screen and SLC5 HP Compaq DC 7900 (2009 model)–– Note: Only VGA video output is supported, theDisplayPort connector is not functional on SLC5 as ofMarch 2009 (even with DisplayPort to DVI adapter):Therefore dual-screen setups cannot be used.Update: As of December 2009 the DisplayPort adapterworks on some configurations providing fully updatedSLC 5.4 version is used.Bought ATI video card on CERN store–––Installed proprietary driver downloaded from ATI siteConfigured via command line toolUsing dual screen (24” HP CERN store 19” EIZO) 24” driven by HDMI cable, 19” by DVI cableFull native resolution, 60 Hz

SystemVerilog Industry's first unified HDVL (Hw Description and Verification language (IEEE 1800) Major extension of Verilog language (IEEE 1364) Targeted primarily at the chip implementation and verification flow Improve productivity in the d