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SystemVerilog 3.1aLanguage Reference ManualAccellera’s Extensions to Verilog Abstract: a set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language to aidin the creation and verification of abstract architectural level models

SystemVerilog 3.1a (5/13/04)SystemVerilog 3.1aLanguage Reference ManualAccellera’s Extensions to Verilog Abstract: a set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language to aidin the creation and verification of abstract architectural level modelsCopyright 2002, 2003, 2004 by Accellera Organization, Inc.1370 Trancas Street #163Napa, CA 94558Phone: (707) 251-9977Fax: (707) 251-9877All rights reserved. No part of this document may be reproduced or distributed in any medium whatsoever to any third parties without prior written consent of Accellera Organization, Inc.

AccelleraExtensions to Verilog-2001SystemVerilog 3.1aVerilog is a registered trademark of Cadence Design Systems, San Jose, CAiiCopyright 2004 Accellera. All rights reserved.

AccelleraExtensions to Verilog-2001SystemVerilog 3.1aSTATEMENT OF USEOF ACCELLERA STANDARDSAccellera Standards documents are developed within Accellera and the Technical Committees of AccelleraOrganization, Inc. Accellera develops its standards through a consensus development process, approved by itsmembers and board of directors, which brings together volunteers representing varied viewpoints and intereststo achieve the final product. Volunteers are not necessarily members of Accellera and serve without compensation. While Accellera administers the process and establishes rules to promote fairness in the consensus development process, Accellera does not independently evaluate, test, or verify the accuracy of any of theinformation contained in its standards.Use of an Accellera Standard is wholly voluntary. Accellera disclaims liability for any personal injury, property or other damage, of any nature whatsoever, whether special, indirect, consequential, or compensatory,directly or indirectly resulting from the publication, use of, or reliance upon this, or any other Accellera Standard document.Accellera does not warrant or represent the accuracy or content of the material contained herein, and expresslydisclaims any express or implied warranty, including any implied warranty of merchantability or suitability fora specific purpose, or that the use of the material contained herein is free from patent infringement. AccelleraStandards documents are supplied “AS IS”.The existence of an Accellera Standard does not imply that there are no other ways to produce, test, measure,purchase, market, or provide other goods and services related to the scope of an Accellera Standard. Furthermore, the viewpoint expressed at the time a standard is approved and issued is subject to change due to developments in the state of the art and comments received from users of the standard. Every Accellera Standard issubjected to review periodically for revision and update. Users are cautioned to check to determine that theyhave the latest edition of any Accellera Standard.In publishing and making this document available, Accellera is not suggesting or rendering professional orother services for, or on behalf of, any person or entity. Nor is Accellera undertaking to perform any duty owedby any other person or entity to another. Any person utilizing this, and any other Accellera Standards document, should rely upon the advice of a competent professional in determining the exercise of reasonable care inany given circumstances.Interpretations: Occasionally questions may arise regarding the meaning of portions of standards as they relateto specific applications. When the need for interpretations is brought to the attention of Accellera, Accellerawill initiate action to prepare appropriate responses. Since Accellera Standards represent a consensus of concerned interests, it is important to ensure that any interpretation has also received the concurrence of a balanceof interests. For this reason, Accellera and the members of its Technical Committees are not able to provide aninstant response to interpretation requests except in those cases where the matter has previously received formal consideration.Comments for revision of Accellera Standards are welcome from any interested party, regardless of membership affiliation with Accellera. Suggestions for changes in documents should be in the form of a proposedchange of text, together with appropriate supporting comments. Comments on standards and requests for interpretations should be addressed to:Accellera Organization1370 Trancas Street #163Napa, CA 94558USACopyright 2004 Accellera. All rights reserved.iii

SystemVerilog 3.1aAccelleraExtensions to Verilog-2001Note: Attention is called to the possibility that implementation of this standard may require use of subjectmatter covered by patent rights. By publication of this standard, no position is taken with respect to theexistence or validity of any patent rights in connection therewith. Accellera shall not be responsible foridentifying patents for which a license may be required by an Accellera standard or for conducting inquiries into the legal validity or scope of those patents that are brought to its attention.Accellera is the sole entity that may authorize the use of Accellera-owned certification marks and/or trademarks to indicate compliance with the materials set forth herein.Authorization to photocopy portions of any individual standard for internal or personal use must be granted byAccellera Organization, Inc., provided that permission is obtained from and any required fee is paid to Accellera. To arrange for authorization please contact Lynn Horobin, Accellera, 1370 Trancas Street #163, Napa,CA 94558, phone (707) 251-9977, e-mail lynn@accellera.org. Permission to photocopy portions of any individual standard for educational classroom use can also be obtained from Accellera.ivCopyright 2004 Accellera. All rights reserved.

AccelleraExtensions to Verilog-2001SystemVerilog 3.1aAcknowledgementsThis SystemVerilog Language Reference Manual was developed by experts from many different fields, including design and verification engineers, Electronic Design Automation (EDA) companies, EDA vendors, andmembers of the IEEE 1364 Verilog standard working group.The SystemVerilog Language Reference Manual (LRM) was specified by the Accellera SystemVerilog committee. Four subcommittees worked on various aspects of the SystemVerilog 3.1 specification:— The Basic/Design Committee (SV-BC) worked on errata and extensions to the design features of SystemVerilog 3.1.— The Enhancement Committee (SV-EC) worked on errata and extensions to the testbench features of SystemVerilog 3.1.— The Assertions Committee (SV-AC) worked on errata and extensions to the assertion features of SystemVerilog 3.1.— The C Application Programming Interface (API) Committee (SV-CC) worked on errata and extensions tothe Direct Programming Interface (DPI), the assertions and coverage APIs and the VPI features of SystemVerilog 3.1.The committee chairs were:Vassilios Gerousis, SystemVerilog 3.1 and 3.1a Committee General ChairBasic/Design CommitteeJohny Srouji, SystemVerilog 3.1 and 3.1a ChairKaren Pieper, SystemVerilog 3.1 and 3.1a Co-ChairEnhancement CommitteeDavid Smith, SystemVerilog 3.1 and 3.1a ChairStefen Boyd, SystemVerilog 3.1 Co-ChairNeil Korpusik, SystemVerilog 3.1a Co-ChairAssertions CommitteeFaisal Haque, SystemVerilog 3.1 and 3.1a ChairSteve Meier, SystemVerilog 3.1 Co-ChairArif Samad, SystemVerilog 3.1a Co-ChairC API CommitteeSwapnajit Mittra, SystemVerilog 3.1 and 3.1a ChairGhassan Khoory, SystemVerilog 3.1 and 3.1a Co-ChairStuart Sutherland, SystemVerilog 3.1 and 3.1a Language Reference Manual EditorStefen Boyd, SystemVerilog 3.1 BNF Annex. EditorBrad Pierce, SystemVerilog 3.1a BNF Annex EditorCopyright 2004 Accellera. All rights reserved.v

AccelleraExtensions to Verilog-2001SystemVerilog 3.1aCommittee members included (listed alphabetically by last name)SystemVerilog 3.1/3.1aBasic/Design CommitteeKevin Cameron Cliff Cummings* Dan Jacobi Jay Lawrence Mark Hartoog Peter Flake Matt Maidment Francoise Martinolle* Rishiyur Nikhil Karen Pieper* Brad Pierce David Rich Steven Sharp* Johny Srouji Gord Vreugdenhil* Doug Warmke SystemVerilog 3.1/3.1aEnhancement CommitteeStefen Boyd* Dennis Brophy Michael Burns Kevin Cameron Cliff Cummings* Peter Flake Jeff Freedman Neil Korpusik Jay Lawrence Francoise Martinolle* Don Mills Mehdi Mohtashemi Phil Moorby Karen Pieper* Brad Pierce Dave Rich Ray Ryan Arturo Salz David Smith Stuart Sutherland* SystemVerilog 3.1/3.1aAssertions CommitteeRoy Armoni Surrendra Dudani Cindy Eisner Harry Foster Faisal Haque John Havlicek Richard Ho Adam Krolnik* David Lacey Joseph Lu Erich Marschner Steve Meier Hillel Miller Prakash Narain Koushik Roy Arif Samad Andrew Seawright Bassam Tabbara SystemVerilog 3.1/3.1aC API CommitteeJohn Amouroux Kevin Cameron Ralph Duncan Charles Dawson João Geada Ghassan Khoory Andrzej Litwiniuk Avinash Mani Francoise Martinole* Swapnajit Mittra Michael Rohleder John Stickley Stuart Swan Bassam Tabbara Kurt Takara Doug Warmke * indicates this person was also an active member of the IEEE 1364 Verilog Standard Working Group indicates this person was actively involved in SystemVerilog 3.1 indicates this person was actively involved in SystemVerilog 3.1a indicates this person was actively involved in SystemVerilog 3.1 and 3.1aviCopyright 2004 Accellera. All rights reserved.

AccelleraExtensions to Verilog-2001SystemVerilog 3.1aTable of ContentsSection 1 Introduction to SystemVerilog . 1Section 22.12.22.32.42.52.62.72.8Literal Values. 4Introduction (informative) .4Literal value syntax.4Integer and logic literals .4Real literals .5Time literals .5String literals.5Array literals .6Structure literals .6Section 153.16Data Types. 8Introduction (informative) .8Data type syntax.9Integer data types .10Real and shortreal data types .11Void data type .11chandle data type .11String data type .12Event data type.16User-defined types .16Enumerations .17Structures and unions.22Class.26Singular and aggregate types .27Casting .27 cast dynamic casting .28Bit-stream casting .29Section 15Arrays . 32Introduction (informative) .

SystemVerilog 3.1a Language Reference Manual Accellera’s Extensions to Verilog Abstract: a set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language to aid in the creation and verification of abstract architectural level models