WIXLIB

“output” — 2019/6/7 — 17:38 — page 1 — #1Case study on Universal VerificationMethodology(UVM) SystemC testbench for RTLverificationKevin Skaria Chackoke4067fn-s@student.lu.seDepartment of Electrical and Information TechnologyLund UniversitySupervisor: Liang LiuExaminer: Erik LarssonJune 7, 2019

“output” — 2019/6/7 — 17:38 — page 2 — #2c 2019Printed in SwedenTryckeriet i E-huset, Lund

“output” — 2019/6/7 — 17:38 — page i — #3AbstractThis Master’s thesis aims to conduct a case study on using Universal VerificationMethodology (UVM) in SystemC for Register-Transfer Level (RTL) verification.Verification of ASICs is very important nowadays especially in terms of productioncosts, time to market and the sustainability of products. As Moore’s Law is inmotion, verification gets large, complex, and time-consuming. Re-usability andsimulation performance of testbenches are key areas for improvement. AccelleraSystems Initiative, a standard organization that supports user and vendor standards in the field of EDA and ICs has released UVM in SystemC as a Beta version.Since SystemVerilog UVM testbenches have been around in industries for severalyears in different performance optimized versions, one of these versions is implemented in UVM SystemC to study if the same optimizations are possible. This willalso enable to have a common language platform for SystemC Register-TransferLevel (RTL) and RTL testbench development. In order to simulate two differenthardware modeling languages in an EDA simulator, 3 different methods of interfacing UVM SystemC with SystemVerilog RTL have been explored: UVM-MultiLanguage (ML), Beta over Legacy (βoL), and Standard Co-Emulation Interface(SCE-MI). Based on simplicity and simulation time the βoL interface has beencharacterized for a better option. Moreover, knowing the relationship of SystemCsimulation time with timing accuracy, a performance comparison with SystemVerilog UVM has helped to understand the bottleneck of SystemC testbench withcycle-accurate interfaces as compared to SystemVerilog interfaces where the simulator tool perform optimizations in context switching. From the results of theperformance comparison, this study proposes a direction in using a hybrid testbench model where the stimulus and response data parts of the testbench arestill in SystemC TLM whereas the cycle accurate interfaces with the RTL are inSystemVerilog.i

“output” — 2019/6/7 — 17:38 — page ii — #4ii

“output” — 2019/6/7 — 17:38 — page iii — #5AcknowledgmentsTo begin with, I would like to thank my supervisor, Professor Liang Liu andmy examiner, Professor Erik Larsson for their guidance in this project. They havehelped me to bring up the scientific aspect of this thesis all along the way. Similarly,I am thankful to my supervisor at Ericsson, Ole Kristoffersen for sharing his vastexperience in ASIC verification and always encouraging me to think outside thebox. I would like to show my gratitude to the Application engineers at Cadence,David Spieker and Hans Martin for providing constant support throughout thethesis. I am also thankful to my Manager at Ericsson, Torsten C Larsson, frominspiring me from the beginning being a guest lecturer at LTH to giving me anopportunity to do this thesis in his team.To my colleagues in Ericsson: Grzegorz Swiecanski, Deepak Yadav, Arun Jeevaraj and Dimitar Dikov, I am always grateful for assisting me from the basictechnical problems in the starting days to the end of this thesis work.To my family, who have given me the motivation in pursuing my passion andinterest and been the foundation of my success. I can never thank you enough.To my friends in Lund: Aishwarya, Michail, Ghanashyam for bearing my thesistalks during lunch and after work, trying to understand and providing unconditional support in achieving my goals. Thank you for helping me in your besteffort.To my friends from National Institute of Technology India, who have helpedme realize my potential to complete this thesis. This thesis has your imprints allover it. To my high school teacher, Ms. Seena, without you I would not haveremembered my OOP concepts needed for this work.To every person that I forgot to mention here, those who have played even thesmallest part in my life. I thank you from the bottom of my heart.iii

“output” — 2019/6/7 — 17:38 — page iv — #6iv

“output” — 2019/6/7 — 17:38 — page v — #7Popular Science SummaryYou need to give up something to achieve somethingAs the digital electronics and semiconductor industries tries to follow theMoores Law: "The number of transistors and resistors on a chip doubles every24 months", the verification process of these chips gets large and more complex.The need for verification engineers in an ASIC/IC development project has surpassed the design engineers since a few years for the same reason.Nowadays electronic industries compete with each other to reach the marketfirst and give the most innovative and efficient products. It can be seen with thenew standards released every decade in mobile communications: GSM, 3G, 4Gand now 5G. To make sure these industries meet the consumers demands for highspeed communication, they need to find faster and efficient ways of designing andverifying their products. This would be the context of this thesis work: to finda direction on how to reduce the verification time of large and complex digitalhardware designs.Digital Circuits are designed with Hardware Description Language (HDL)which is like a programming language to implement a Register-Transfer Level(RTL) abstraction model of data flow and timing of a circuit. These HDL’s can besimulated to check their correctness with testbenches. The traditional testbenchesare usually written with HDL languages in different standards or methodologies tointerface better with the Design Under Test (DUT). Therefore if an HDL testbenchcan be adapted to a more abstract language such as SystemC based on C , itwill be able to compile and sequentially run them much faster and efficiently.HDL Testbench languages typically vary based on their size and complexityin verifying hardware designs, smaller designs use VHDL/Verilog with no specificstandard or methodology whereas bigger designs uses SystemVerilog in UniversalVerification Methodology (UVM) framework. These languages are tools of a tradelike carpentry and the methodologies explains how efficiently the trade can buildsomething big like a house.This thesis work will verify a RTL hardware design of Ericsson with a testbenchon SystemC Universal Verification Methodology(UVM) framework and compareits simulation time to already existing SystemVerilog UVM framework. The studyof comparing simulation performances will help to understand the bottleneck ofusing UVM SystemC and provide a direction on how to improve the current bestperformance.v

“output” — 2019/6/7 — 17:38 — page vi — #8vi

“output” — 2019/6/7 — 17:38 — page vii — #9AcronymsAPIASICApplication Programming InterfaceApplication Specific Integrated CircuitBFMBus Functional BlockCMAFIRCPUCTSRCascadable Multiplexed Asymmetric FIRCentral Processing UnitClock to Sample RatioDUTDesign Under TestEDAElectronic Design AutomationFE AFIRFFFIRFPGAFilter Engine Asymmetric FIR filterFlip-flopFinite Impulse ResponseField-Programmable Gate ArrayGDBGSMGNU DebuggerGlobal System for Mobile CommunicationHDLHiLHLSHardware Description LanguageHardware in the LoopHigh Level SynthesisICIEEEIFSIPIntegrated CircuitInstitute of Electrical and Electronics EngineersIntegrated Functional Verification Script EnvironmentIntellectual ProprietyMLMulti LanguageOAOpen Architecturevii

“output” — 2019/6/7 — 17:38 — page viii — #10OOPObject-oriented programmingRCPRTLRapid Control PrototypingRegister-Transfer LevelSCE-MISoCStandard Co-Emulation InterfaceSystem on ChipTLMTransaction Level ModellingUVCUVMUniversal Verification ComponentUniversal Verification MethodologyVHDLVHSIC Hardware Description Languageviii

“output” — 2019/6/7 — 17:38 — page ix — #11Table of Contents1Background1.1 Importance of Verification . . . . . . . . . . . . . . . . . . . . . . .1.2 Design Under Test . . . . . . . . . . . . . . . . . . . . . . . . . . .1.31.4231131.2.1Hardware Architecture31.2.2Functional Specification31.2.3Design Parameters41.2.4Signal Interface41.2.5HW/SW Interface5SystemVerilog UVM . . . . . . . . . . . . . . . . . . . . . . . . . .51.3.1Traditional Testbench51.3.2System Verilog Testbench61.3.3Universal Verification MethodologyPrevious Work on SystemC7. . . . . . . . . . . . . . . . . . . . . .8Objectives, Challenges and Methodology2.1 Main Objectives of this Work . . . . . . . . . . . . . . . . . . . . .11112.1.1UVM SystemC Testbench112.1.2Testbench - RTL Interface132.1.3Evaluation of the Simulation Performance14Implementation and Results3.1 Key Differences in UVM SystemC from UVM System Verilog . . . .3.23.33.419193.1.1Forward Declaration193.1.2Dynamic Array Size Allocation193.1.3Segmentation Fault Debugger203.1.4SystemC Bit Reduction and Range Selection203.1.5Forked Process Implementation21Testbench to RTL Interface . . . . . . . . . . . . . . . . . . . . . .223.2.1UVM Multi-Language(ML)223.2.2βeta over Legacy(βoL)233.2.3Standard Co- Emulation Modelling Interface (SCE-MI)24Simulation Time Comparison between SCE-MI and βoL Interfaces . .Performance Evaluation between Multiple Testbench - RTL Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ix2627

“output” — 2019/6/7 — 17:38 — page x — #123.543.4.1Configurations3.4.2Performance Analysis2728Scope of results . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303.5.13.5.23030High Level Synthesis VerificationHardware Prototyping Platforms (Validation)Conclusion and Future Work4.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31313233Referencesx

“output” — 2019/6/7 — 17:38 — page xi — #13List of Figures1.11.21.31.41.5A basic verification plan . . . . . . . . . . .A representation of the FE AFIR . . . . . .Traditional testbench Architecture . . . . . .System Verilog Testbench Architecture . . .UVM System Verilog Testbench Architecture.246672.12.22.32.4Different implementation of the forked process . . . . . . . . . . . .SystemC UVM testbench architecture . . . . . . . . . . . . . . . . .Multi-Language Interface . . . . . . . . . . . . . . . . . . . . . . . .Relative hardware modelling simulation performance with timing Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Multi Language TLM ports . . . . . . . . . . . . . . . . . . . . . .Architecture of the Hybrid solution . . . . . . . . . . . . . . . . . .121314Separator modules at Input, Output and signal channels . . . . . . .UVM ML interface using the Cadence Legacy UVM hierarchical components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .βoL interface implemented with a switch . . . . . . . . . . . . . . .SCE-MI interface between simulator and emulator . . . . . . . . . .Performance comparison between SCE-MI and βoL interface . . . . .Multiple Testbench RTL configuration . . . . . . . . . . . . . . . . .Analysis of multiple Testbench RTL configurations . . . . . . . . . 9

“output” — 2019/6/7 — 17:38 — page xii — #14xii

“output” — 2019/6/7 — 17:38 — page xiii — #15List of Tables1.1List of DUT interfaces . . . . . . . . . . . . . . . . . . . . . . . . .xiii5

“output” — 2019/6/7 — 17:38 — page xiv — #16xiv