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Quartus II Version 7.2 HandbookVolume 4: SOPC BuilderPreliminary Information101 Innovation DriveSan Jose, CA 95134www.altera.comQII5V4-7.2
Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks andservice marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrantsperformance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to makechanges to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by AlteraCorporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.iiAltera Corporation
ContentsChapter Revision Dates . xiAbout this Handbook. xiiiHow to Contact Altera . xiiiTypographic Conventions . xiiiSection I. SOPC Builder FeaturesChapter 1. Introduction to SOPC BuilderOverview .Architecture of SOPC Builder Systems .SOPC Builder Components .Example System .Custom Components .System Interconnect Fabric .Functions of SOPC Builder .Defining and Generating the System Hardware .Creating a Memory Map for Software Development .Creating a Simulation Model and Test Bench .Getting Started .Referenced Documents .Document Revision History 61–71–71–8Chapter 2. System Interconnect Fabric for Memory-Mapped InterfacesIntroduction . 2–1High-Level Description . 2–1Fundamentals of Implementation . 2–4Functions of System Interconnect Fabric . 2–4Address Decoding . 2–5Datapath Multiplexing . 2–6Wait-State Insertion . 2–7Pipeline Read Transfers . 2–8Native Address Alignment and Dynamic Bus Sizing . 2–9Dynamic Bus Sizing . 2–9Wider Master . 2–10Narrower Master . 2–10Native Address Alignment . 2–11Arbitration for Multimaster Systems . 2–12Altera CorporationiiiQuartus II Handbook, Volume 4
Quartus II Handbook, Volume 4Traditional Shared Bus Architectures . 2–12Slave-Side Arbitration . 2–13Arbiter Details . 2–14Arbitration Rules . 2–15Setting Arbitration Parameters in SOPC Builder . 2–15Fairness-Based Shares . 2–16Round-Robin Scheduling . 2–17Burst Transfers . 2–17Minimum Share Value . 2–17Burst Management . 2–18Clock Domain Crossing . 2–19Description of Clock Domain-Crossing Logic . 2–19Location of Clock Domain Crossing Logic . 2–21Duration of Transfers Crossing Clock Domains . 2–22Implementing Multiple Clock Domains in SOPC Builder . 2–22Component Overview . 2–23Functional Description . 2–23Interfaces . 2–24Clock Domain Crossing Logic and FIFOs . 2–24Burst Support . 2–25Example System with Avalon-MM Clock-Crossing Bridges . 2–26Instantiating the Avalon-MM Clock-Crossing Bridge in SOPC Builder . 2–28Interrupts . 2–29Software Priority . 2–29Hardware Priority . 2–30Assigning IRQs in SOPC Builder . 2–30Reset Distribution . 2–31Referenced Documents . 2–31Document Revision History . 2–32Chapter 3. System Interconnect Fabric for Streaming InterfacesIntroduction . 3–1High-Level Description . 3–1Avalon Streaming and Avalon Memory-Mapped Interfaces . 3–2Adapters . 3–3Data Format Adapter . 3–4Timing Adapter . 3–4Channel Adapter . 3–5Multiplexer Examples . 3–5Example to Double Clock Frequency . 3–5Example to Double Data Width and Maintain Frequency . 3–6Example to Boost the Frequency . 3–6Referenced Documents . 3–7Document Revision History . 3–7Chapter 4. SOPC Builder ComponentsIntroduction . 4–1ivQuartus II Handbook, Volume 4Altera Corporation
ContentsNew Component Structure in v7.1 of the Quartus II Software . 4–1Component Providers . 4–2Component Hardware Structure . 4–2Components That Include Logic Inside the System Module . 4–3Components That Interface to Logic Outside the System Module . 4–4List of Available Components in SOPC Builder . 4–4Tcl Components . 4–5Component Description File ( hw.tcl) . 4–5Component File Organization . 4–5Referenced Document . 4–6Document Revision History . 4–6Chapter 5. Component EditorIntroduction .Component Hardware Structure .Starting the Component Editor .HDL Files Tab .Signals Tab .Naming Signals for Automatic Type and Interface Recognition .Templates for Interfaces to External Logic .Interfaces Tab .Component Wizard Tab .Identifying Information .Parameters .Saving a Component .Editing a Component .Referenced Documents .Document Revision History 65–75–75–85–85–9Chapter 6. Building a Component Interface with Tcl Scripting CommandsOrganization of a Component Tcl File . 6–2Set and Add Commands . 6–3Module Properties . 6–4Clock Interface . 6–4Avalon-MM Master Interface . 6–5Avalon-MM Slave Interface . 6–5Avalon-ST Source Interface . 6–6Avalon-ST Sink Interface . 6–7Avalon-MM Tristate Interface . 6–7Nios II Custom Instruction Interface . 6–8Interrupt Interface . 6–9Conduit Interface . 6–10Document Revision History . 6–10Chapter 7. Archiving SOPC Builder ProjectsIntroduction . 7–1Scope . 7–1Altera CorporationvQuartus II Handbook, Volume 4
Quartus II Handbook, Volume 4Required Files .SOPC Builder Design Files .Nios II Application Software Project Files .Nios II System Library Project .File Write Permissions .Referenced Documents .Document Revision History .7–27–37–37–47–47–47–5Section II. Building Systems with SOPC BuilderChapter 8. Building Memory Subsystems Using SOPC BuilderIntroduction . 8–1Example Design . 8–2Example Design Structure . 8–2Example Design Starting Point . 8–4Hardware and Software Requirements . 8–5Design Flow . 8–5Component-Level Design in SOPC Builder .
Preliminary Information 101 Innovation Drive San Jose, CA 95134 www.altera.com Quartus II Version 7.2
