WIXLIB

PIC16F8X3.0ARCHITECTURAL OVERVIEWThe high performance of the PIC16CXX family can beattributed to a number of architectural featurescommonly found in RISC microprocessors. To beginwith, the PIC16CXX uses a Harvard architecture. Thisarchitecture has the program and data accessed fromseparate memories. So the device has a programmemory bus and a data memory bus. This improvesbandwidth over traditional von Neumann architecturewhere program and data are fetched from the samememory (accesses over the same bus). Separatingprogram and data memory further allows instructions tobe sized differently than the 8-bit wide data word.PIC16CXX opcodes are 14-bits wide, enabling singleword instructions. The full 14-bit wide program memorybus fetches a 14-bit instruction in a single cycle. A twostage pipeline overlaps fetch and execution of instructions (Example 3-1). Consequently, all instructions execute in a single cycle except for program branches.The PIC16F83 and PIC16CR83 address 512 x 14 ofprogram memory, and the PIC16F84 and PIC16CR84address 1K x 14 program memory. All program memory is internal.The PIC16CXX can directly or indirectly address itsregister files or data memory. All special functionregisters including the program counter are mapped inthe data memory. An orthogonal (symmetrical)instruction set makes it possible to carry out any operation on any register using any addressing mode. Thissymmetrical nature and lack of ‘special optimalsituations’ make programming with the PIC16CXXsimple yet efficient. In addition, the learning curve isreduced significantly. 1998 Microchip Technology Inc.DS30430C-page 7

PIC16F8XPIC16CXX devices contain an 8-bit ALU and workingregister. The ALU is a general purpose arithmetic unit.It performs arithmetic and Boolean functions betweendata in the working register and any register file.The W register is an 8-bit working register used for ALUoperations. It is not an addressable register.Depending on the instruction executed, the ALU mayaffect the values of the Carry (C), Digit Carry (DC), andZero (Z) bits in the STATUS register. The C and DC bitsoperate as a borrow and digit borrow out bit,respectively, in subtraction. See the SUBLW and SUBWFinstructions for examples.The ALU is 8-bits wide and capable of addition,subtraction, shift and logical operations. Unlessotherwise mentioned, arithmetic operations are two’scomplement in nature. In two-operand instructions,typically one operand is the working register(W register), and the other operand is a file register oran immediate constant. In single operand instructions,the operand is either the W register or a file register.FIGURE 3-1:PIC16F8X BLOCK DIAGRAMData Bus138Program CounterFlash/ROMProgramMemoryPIC16F83/CR83512 x 14PIC16F84/CR841K x 14ProgramBusA simplified block diagram for the PIC16F8X is shownin Figure 3-1, its corresponding pin description isshown in Table 3-1.8 Level Stack(13-bit)14EEPROM Data MemoryRAMFile RegistersPIC16F83/CR8336 x 8PIC16F84/CR8468 x 87EEDATARAM AddrEEPROMData Memory64 x 8EEADRAddr MuxInstruction reg7Direct Addr5TMR0IndirectAddrFSR regRA4/T0CKISTATUS reg8MUXPower-upTimerInstructionDecode &ControlTimingGenerationOscillatorStart-up Timer8ALUPower-onResetWatchdogTimerI/O PortsRA3:RA0W e 8MCLRVDD, VSS 1998 Microchip Technology Inc.

PIC16F8XTABLE 3-1PIC16F8X PINOUT C2/CLKOUT1515O—Oscillator crystal output. Connects to crystal or resonator in crystaloscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has1/4 the frequency of OSC1, and denotes the instruction cycle rate.MCLR44I/PSTMaster clear (reset) input/programming voltage input. This pin is anactive low reset to the device.Pin NameBufferTypeDescriptionST/CMOS (3) Oscillator crystal input/external clock source input.PORTA is a bi-directional I/O TTLRA4/T0CKI33I/OSTCan also be selected to be the clock input to the TMR0 timer/counter. Output is open drain type.PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.RB0/INT66I/OTTL/ST (1)RB177I/OTTLRB288I/OTTLRB0/INT can also be selected as an external interrupt pin.RB399I/OTTLRB41010I/OTTLInterrupt on change pin.RB51111I/OTTLInterrupt on change pin.RB61212I/OTTL/ST (2)(2)TTL/STInterrupt on change pin. Serial programming clock.Interrupt on change pin. Serial programming data.RB71313I/OVSS55P—Ground reference for logic and I/O pins.VDD1414P—Positive supply for logic and I/O pins.Legend: I inputO outputI/O Input/OutputP power— Not usedTTL TTL inputST Schmitt Trigger inputNote 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.2: This buffer is a Schmitt Trigger input when used in serial programming mode.3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 1998 Microchip Technology Inc.DS30430C-page 9

PIC16F8X3.1Clocking Scheme/Instruction Cycle3.2The clock input (from OSC1) is internally divided byfour to generate four non-overlapping quadratureclocks namely Q1, Q2, Q3 and Q4. Internally, theprogram counter (PC) is incremented every Q1, theinstruction is fetched from the program memory andlatched into the instruction register in Q4. Theinstruction is decoded and executed during thefollowing Q1 through Q4. The clocks and instructionexecution flow is shown in Figure 3-2.Instruction Flow/PipeliningAn “Instruction Cycle” consists of four Q cycles (Q1,Q2, Q3 and Q4). The instruction fetch and execute arepipelined such that fetch takes one instruction cyclewhile decode and execute takes another instructioncycle. However, due to the pipelining, each instructioneffectively executes in one cycle. If an instructioncauses the program counter to change (e.g., GOTO)then two cycles are required to complete the instruction(Example 3-1).A fetch cycle begins with the Program Counter (PC)incrementing in Q1.In the execution cycle, the fetched instruction is latchedinto the “Instruction Register” in cycle Q1. Thisinstruction is then decoded and executed during theQ2, Q3, and Q4 cycles. Data memory is read during Q2(operand read) and written during Q4 (destinationwrite).FIGURE 3-2:CLOCK/INSTRUCTION clockQ3Q4PCPCOSC2/CLKOUT(RC mode)EXAMPLE 3-1:Fetch INST (PC)Execute INST (PC-1)PC 2Fetch INST (PC 1)Execute INST (PC)Fetch INST (PC 2)Execute INST (PC 1)INSTRUCTION PIPELINE FLOW1. MOVLW 55h2. MOVWF PORTB3. CALL SUB 14. BSFPC 1PORTA, BIT3Fetch 1Execute 1Fetch 2Execute 2Fetch 3Execute 3Fetch 4FlushFetch SUB 1 Execute SUB 1All instructions are single cycle, except for any program branches. These take two cycles since the fetchinstruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.DS30430C-page 10 1998 Microchip Technology Inc.

PIC16F8XMEMORY ORGANIZATIONThere are two memory blocks in the PIC16F8X. Theseare the program memory and the data memory. Eachblock has its own bus, so that access to each block canoccur during the same oscillator cycle.The data memory can further be broken down into thegeneral purpose RAM and the Special FunctionRegisters (SFRs). The operation of the SFRs thatcontrol the “core” are described here. The SFRs usedto control the peripheral modules are described in thesection discussing each individual peripheral module.The data memory area also contains the dataEEPROM memory. This memory is not directly mappedinto the data memory, but is indirectly mapped. That is,an indirect address pointer specifies the address of thedata EEPROM memory to read/write. The 64 bytes ofdata EEPROM memory have the address range0h-3Fh. More details on the EEPROM memory can befound in Section 7.0.4.1FIGURE 4-1:PROGRAM MEMORY MAPAND STACK - PIC16F83/CR83PC 12:0 13CALL, RETURNRETFIE, RETLWStack Level 1 Stack Level 8User MemorySpace4.0Reset Vector0000hPeripheral Interrupt Vector0004h1FFhProgram Memory OrganizationThe PIC16FXX has a 13-bit program counter capableof addressing an 8K x 14 program memory space. Forthe PIC16F83 and PIC16CR83, the first 512 x 14(0000h-01FFh)arephysicallyimplemented(Figure 4-1). For the PIC16F84 and PIC16CR84, thefirst 1K x 14 (0000h-03FFh) are physically implemented (Figure 4-2). Accessing a location above thephysically implemented address will cause a wraparound. For example, for the PIC16F84 locations 20h,420h, 820h, C20h, 1020h, 1420h, 1820h, and 1C20hwill be the same instruction.1FFFhFIGURE 4-2:PROGRAM MEMORY MAPAND STACK - PIC16F84/CR84PC 12:0 13CALL, RETURNRETFIE, RETLWStack Level 1 Stack Level 8Reset Vector0000hPeripheral Interrupt Vector0004hUser MemorySpaceThe reset vector is at 0000h and the interrupt vector isat 0004h.3FFh1FFFh 1998 Microchip Technology Inc.DS30430C-page 11

PIC16F8X4.2Data Memory Organization4.2.1GENERAL PURPOSE REGISTER FILEThe data memory is partitioned into two areas. The firstis the Special Function Registers (SFR) area, while thesecond is the General Purpose Registers (GPR) area.The SFRs control the operation of the device.All devices have some amount of General PurposeRegister (GPR) area. Each GPR is 8 bits wide and isaccessed either directly or indirectly through the FSR(Section 4.5).Portions of data memory are banked. This is for boththe SFR area and the GPR area. The GPR area isbanked to allow greater than 116 bytes of generalpurpose RAM. The banked areas of the SFR are for theregisters that control the peripheral functions. Bankingrequires the use of control bits for bank selection.These control bits are located in the STATUS Register.Figure 4-1 and Figure 4-2 show the data memory maporganization.The GPR addresses in bank 1 are mapped toaddresses in bank 0. As an example, addressing location 0Ch or 8Ch will access the same GPR.Instructions MOVWF and MOVF can move values fromthe W register to any location in the register file (“F”),and vice-versa.The special function registers can be classified into twosets, core and peripheral. Those associated with thecore functions are described in this section. Thoserelated to the operation of the peripheral features aredescribed in the section for that specific feature.The entire data memory can be accessed eitherdirectly using the absolute address of each register fileor indirectly through the File Select Register (FSR)(Section 4.5). Indirect addressing uses the presentvalue of the RP1:RP0 bits for access into the bankedareas of data memory.4.2.2SPECIAL FUNCTION REGISTERSThe Special Function Registers (Figure 4-1, Figure 4-2and Table 4-1) are used by the CPU and Peripheralfunctions to control the device operation. Theseregisters are static RAM.Data memory is partitioned into two banks whichcontain the general purpose registers and the specialfunction registers. Bank 0 is selected by clearing theRP0 bit (STATUS 5 ). Setting the RP0 bit selects Bank1. Each Bank extends up to 7Fh (128 bytes). The firsttwelve locations of each Bank are reserved for theSpecial Function Registers. The remainder are General Purpose Registers implemented as static RAM.DS30430C-page 12 1998 Microchip Technology Inc.

PIC16F8XFIGURE 4-1:REGISTER FILE MAP PIC16F83/CR83File AddressFIGURE 4-2:REGISTER FILE MAP PIC16F84/CR84File AddressFile Address80h00hIndirect ON8Bh0BhINTCONINTCON8Bh8Ch0Ch00hIndirect addr.(1)01hTMR002hPCL03h04hIndirect d(accesses)in Bank 02Fh30hFile Address8ChMapped(accesses)in Bank 04Fh50h7FhFFhBank 0Bank 1Unimplemented data memory location; read as ’0’.Note 1: Not a physical register. 1998 Microchip Technology irect addr.(1)CFhD0h7FhFFhBank 0Bank 1Unimplemented data memory location; read as ’0’.Note 1: Not a physical register.DS30430C-page 13

PIC16F8XTABLE 4-1AddressREGISTER FILE SUMMARYNameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Value onPower-onResetValue on allother resets(Note3)Bank 000hINDFUses contents of FSR to address data memory (not a physical register)---- -------- ----01hTMR08-bit real-time clock/counterxxxx xxxxuuuu uuuu02hPCLLow order 8 bits of the Program Counter (PC)0000 00000000 B107hC0001 1xxx000q quuuxxxx xxxxuuuu uuuuRA0---x xxxx---u uuuuRB0/INTxxxx xxxxuuuu uuuuUnimplemented location, read as '0'---- -------- ----Indirect data memory address pointer 008hEEDATAEEPROM data registerxxxx xxxxuuuu uuuu09hEEADREEPROM address registerxxxx xxxxuuuu uuuu0AhPCLATH———---0 0000---0 00000BhINTCONGIEEEIET0IE0000 000x0000 000u---- -------- ----1111 11111111 11110000 00000000 0000Write buffer for upper 5 bits of the PC (1)INTERBIET0IFINTFRBIFBank 180hINDF81hOPTIONREG82hPCL83hSTATUS (2)84hFSR85hTRISA86hTRISB87h88hEECON1Uses contents of FSR to address data memory (not a physical register)RBPUINTEDGT0CST0SEPSAPS2PS1PS0Low order 8 bits of Program Counter (PC)IRPRP1RP0TOPDZDCCIndirect data memory address pointer 0———PORTA data direction register0001 1xxx000q quuuxxxx xxxxuuuu uuuu---1 1111---1 1111PORTB data direction register1111 11111111 1111Unimplemented location, read as '0'---- -------- -------0 x000---0 IEEEIET0IEEEIFWRERRWRENWRRDEEPROM control register 2 (not a physical register)Write buffer for upper 5 bits of the PC (1)INTERBIET0IFINTFRBIF---- -------- -------0 0000---0 00000000 000x0000 000uLegend: x unknown, u unchanged. - unimplemented read as ’0’, q value depends on condition.Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a slave register for PC 12:8 . The contentsof PCLATH can be transferred to the upper byte of the program counter, but the contents of PC 12:8 is never transferredto PCLATH.2: The TO and PD status bits in the STATUS register are not affected by a MCLR reset.3: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.DS30430C-page 14 1998 Microchip Technology Inc.

PIC16F8X4.2.2.1STATUS REGISTERThe STATUS register contains the arithmetic status ofthe ALU, the RESET status and the bank select bit fordata memory.As with any register, the STATUS register can be thedestination for any instruction. If the STATUS register isthe destination for an instruction that affects the Z, DCor C bits, then the write to these three bits is disabled.These bits are set or cleared according to device logic.Furthermore, the TO and PD bits are not writable.Therefore, the result of an instruction with the STATUSregister as destination may be different than intended.For example, CLRF STATUS will clear the upper-threebits and set the Z bit. This leaves the STATUS registeras 000u u1uu (where u unchanged).FIGURE 4-1:R/W-0IRPOnly the BCF, BSF, SWAPF and MOVWF instructionsshould be used to alter the STATUS register (Table 9-2)because these instructions do not affect any status bit.Note 1: The IRP and RP1 bits (STATUS 7:6 ) ar

All PICmicro microcontrollers employ an advanced RISC architecture. PIC16F8X devices have enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with a separate 8-bit wide data bus.