System Modeling And SystemC - University Of Texas At Austin

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Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David BlackSystem Modeling and SystemCDavid C Blackwww.xtreme-eda.cominfo@xtreme-eda.comVersion 1.72009-Aug-20Restricted materialXtremeEDA USA - SystemC Specialists Founded 2003 under the name Eklectically Inc. (later DBA ESLX Inc.)– Broad Background (Hardware/Software/Methodology/Systems)– Active in SystemC Standardization working groups– Authors of book SystemC: From the Ground Up– Became XtremeEDA USA, a subsidiary of XtremeEDA in 2008 Services– SystemC Adoption Planning– Methodology & Flow Definition & Development General Modeling & Software Development Platforms Architectural and Functional Verification Behavioral Synthesis– Staffing Mentoring Peak staffing needs– Training & Quick Ramp Mentoring Clients include small “startups” to Fortune 500Let our expertshelp your companybe successfulwith SystemC 2009 XtremeEDA USA Corporation - Version 090820.10Copyright (C) 2009 by XtremeEDA Corporation.All rights reserved.Page 1 of 481

Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David BlackObjectives - System Modeling and SystemC Provide a quick overview of the topics– Several fast paced hours of lecture– What is system modeling– How does SystemC fit– Brief introduction to SystemC syntax NOT a complete tutorial– See books or call us for in-depth training– Use this as a guideline on what to learn 2009 XtremeEDA USA Corporation - Version 090820.10Restricted materialTopics System Design Context– General Methodology– Refinement– Benefits SystemC Overview Anatomy of an SC MODULE SystemC Simulation Kernel An Example Some Homework 2009 XtremeEDA USA Corporation - Version 090820.10Copyright (C) 2009 by XtremeEDA Corporation.All rights reserved.Page 2 of 482

Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David BlackLanguages UsageRequirementsMatlab &C/C Algorithm and ArchitecturalFunctional and Software DevelopmentBehavioralSoC VerificationSystemVerilogIP VerificationVerilogRTLSystemCVeraePSLVHDLGates* Modified from DVCon- Gabe Moretti EDNTransistors 2009 XtremeEDA USA Corporation - Version 090820.10Restricted materialModeling Characteristics and Models– UnTimed Functional (UTF)– Timed Functional (TF)– Bus Cycle Accurate (BCA)– Pin Cycle Accurate (PCA)– Register Transfer (RT) accurate Model typesModel Functionality Terms used to characterize modelsUTTFRT– System Architectural Model (SAM)– System Performance Model (SPM)– Transaction Level Model (TLM)– Functional Level Model (FLM)– System Level Model (SLM)– Behavioral Level Model (BLM)– Register Transfer Level (RTL) modelUTTFBCAModel InterfacePCA 2009 XtremeEDA USA Corporation - Version 090820.10Copyright (C) 2009 by XtremeEDA Corporation.All rights reserved.Page 3 of 483

Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David BlackModel RefinementAbstractDetailedModel TDetailedTFBCAPCAModel InterfaceSystemC allows model refinement to proceed independentlyfor functionality and interface 2009 XtremeEDA USA Corporation - Version 090820.10Restricted materialTLM Based ESL entSystem ArchitectureModel DevelopmentSAMTransaction Level lopmentRTLRTL to GDSII Flow 2009 XtremeEDA USA Corporation - Version 090820.10Copyright (C) 2009 by XtremeEDA Corporation.All rights reserved.Page 4 of 484

Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David BlackESL Impacts on Schedule - beforeDisparate ation 2009 XtremeEDA USA Corporation - Version 090820.109Restricted materialESL Impacts on Schedule - afterDisparate Teams:Algorithm Architecture Model Verification wareDevelopmentSystemIntegration 2009 XtremeEDA USA Corporation - Version 090820.10Copyright (C) 2009 by XtremeEDA Corporation.All rights reserved.10Page 5 of 485

Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David Black“Architectural Verification” vs.“Implementation Verification” Architectural Verification– “Have we defined ‘the right’ architecture?”– “Will it enable our customers to succeed?”– “Have we addressed specific use case requirements?” Block-Level Implementation Verification– “Have we implemented a given piece of the architecturecorrectly?”– “Does the implementation match the specification?” System-Level Implementation Verification– “Have we implemented the complete architecture (system)correctly?”– “Does the implementation match the specification?” 2009 XtremeEDA USA Corporation - Version 090820.10Restricted materialBehavioral SynthesisConsidered by many to be the missing Link for ESL Flows Several Vendors now offering solutions– Forte Design Systems– Mentor– Cadence– Agility– AutoESL– Synfora Takes “behavioral code” and “synthesizes” to RTL code Results comparable to human generated RTL– Less code faster design cycle– More microarchitectures considered 2009 XtremeEDA USA Corporation - Version 090820.10Copyright (C) 2009 by XtremeEDA Corporation.All rights reserved.Page 6 of 486

Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David BlackModeling Abstraction LevelsAbstractMajor eventsProgrammer’s view (PV)Loosely Timed (LT)TLM – minimal busInstruction seq.VHDL,VerilogCycle Approximate (CA)TLM – arch. busCycle-accurate I/FRT level (RT)Signal/BitCycle-accurateBetter accuracyApproximately Timed (AT) TLM – generic busPerformance Anal.Faster speedSDL,SystemC, Maxsim,Matlab Coware, PanamaSoftsimVirtioAlgorithmic level (AL) 2009 XtremeEDA USA Corporation - Version 090820.10Restricted materialTLM – Motivations Speed– Quick turn-around for architectural exploration– Appropriate for software development– Regression-style verification Independently refinable– Independently refine functionality and communication– Affords traceability from Architectural Specification to HardwareSpecification and implementation Use of Existing Techniques– TLM is already widely used for verification (not just SystemC)– TLM Interface Spec v1.0 April 2005– TLM Specification v2.0 approved June 2008 2009 XtremeEDA USA Corporation - Version 090820.10Copyright (C) 2009 by XtremeEDA Corporation.All rights reserved.Page 7 of 487

Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David BlackTLM – Model Mix and MatchLT ElementAT ChannelAT ElementLT ElementAdaptor CC ElementAdaptor RT Element 2009 XtremeEDA USA Corporation - Version 090820.10Restricted materialRelative PerformanceAlgorithm (non-functional)ALPerformance modeling(variable degree of timing)LT10MRTL1MAT100K10K1KCALoosely Timed(instruction- andregister-accurate); littleor no timing100Cycle-Approximate(interface timing)Gate-levelRTGates1010%25 %50 %75 %100 %Timing Accuracy 2009 XtremeEDA USA Corporation - Version 090820.10Copyright (C) 2009 by XtremeEDA Corporation.All rights reserved.Page 8 of 488

Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David BlackTopics System Design Context– General Methodology– Refinement– Benefits SystemC Overview Anatomy of an SC MODULE SystemC Simulation Kernel An Example Some Homework 2009 XtremeEDA USA Corporation - Version 090820.10Restricted materialSystemC Organizations IEEE Standards Group 1666 OSCI - systemc.org– LWG (Language Working Group)– VWG (Verification Working Group)– SWG (Synthesis Working Group)– TWG (Transaction Level Modeling Working Group) GreenSOCs.org– Boost.org equivalent Users Groups– European SystemC User’s Group– North American SystemC User’s Group– Latin America SystemC User's Group– India SystemC User's Group 2009 XtremeEDA USA Corporation - Version 090820.10Copyright (C) 2009 by XtremeEDA Corporation.All rights reserved.Page 9 of 489

Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David BlackWebsites IEEE Standards Associationstandards.ieee.org/announcements/pr p1666.html OSCI www.systemc.org NASCUG www.nascug.org ESCUGwww-ti.informatik.uni-tuebingen.de/ systemc/systemc.html GreenSOCs www.greensocs.org Boost www.boost.org 2009 XtremeEDA USA Corporation - Version 090820.10Restricted materialsystemc.org 2009 XtremeEDA USA Corporation - Version 090820.10Copyright (C) 2009 by XtremeEDA Corporation.All rights reserved.Page 10 of 4810

Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David Blackstandards.ieee.org 2009 XtremeEDA USA Corporation - Version 090820.10Restricted materialSystemC Books 2009 XtremeEDA USA Corporation - Version 090820.10Copyright (C) 2009 by XtremeEDA Corporation.All rights reserved.Page 11 of 4811

Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David BlackComing in December 2009 XtremeEDA USA Corporation - Version 090820.10Restricted materialSystemC Books: Details Advanced Verification Techniques: A Systemc Based Approach for SuccessfulTapeout by Leena Singh, Leonard Drucker and Neyaz Khan 2004 ESL Design and Verification by Brian Bailey, Grant Martin and Andrew Piziali 2007 Microelectrofluidic Systems: Modeling and Simulation by Tianhao Zhang,Krishnendu Chakrabarty, Richard B Fair, Zhang Zhang 2002 SystemC: From the Ground Up by David Black and Jack Donovan 2004(now in paperback!) System Design with SystemC by Thorsten Groetker, Stan Liao, Grant Martinand Stuart Swan 2002 SystemC: Methodologies and Applications by Wolfgang Muller, WolfgangRosenstiel and Jurgen Ruf SystemC Primer by Jayram Bhasker 2004 Transaction-Level Modeling with SystemC - TLM Concepts and Applicationsfor Embedded Systems by Frank Ghenassia 2005 2009 XtremeEDA USA Corporation - Version 090820.10Copyright (C) 2009 by XtremeEDA Corporation.All rights reserved.Page 12 of 4812

Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David BlackCan C be used as is?No - C/C lacks Notion of simulated timeTime sequenced operations ConcurrencyHardware and systems are inherently concurrent,i.e. they operate in parallel Hardware data typesBit type, bit-vector type, multi-valued logic type, signed andunsigned specific width integer types and fixed-point types 2009 XtremeEDA USA Corporation - Version 090820.10Restricted materialSystemC C ClassesEnable C without extending the language (syntax)- use classes and templatesCommunicationChannels, eventsNotion of TimeClocks, sc timeConcurrencyHardware Data TypesProcessesbit vectors, arbitraryprecision signed andunsigned integers,fixed-point numbers 2009 XtremeEDA USA Corporation - Version 090820.10Copyright (C) 2009 by XtremeEDA Corporation.All rights reserved.Page 13 of 4813

Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David BlackSystemC Simulation & Testing FunctionalityContains functionality for modular design, easy integration,testing and simulation managementModulesHierarchyTLM StandardInteroperabilityVerification libraryTest BenchSchedulerRunning 2009 XtremeEDA USA Corporation - Version 090820.10Restricted materialUsing SystemC With OSCI PoC SimulatorStandardC faceIP-CoreASICdebugger.class libraryandsimulation kernelDSP.header filessource files for systemand testbenches"make"elbta n"ecucatioxe" cifia.outspeexecutable simulator 2009 XtremeEDA USA Corporation - Version 090820.10Copyright (C) 2009 by XtremeEDA Corporation.All rights reserved.Page 14 of 4814

Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David BlackTopics System Design Context– General Methodology– Refinement– Benefits SystemC Overview Anatomy of an SC MODULE SystemC Simulation Kernel An Example Some Homework 2009 XtremeEDA USA Corporation - Version 090820.10Restricted materialSystemC Language ArchitectureLayered LibrariesVerification Library, etc.Primitive ChannelsSignal, Mutex, Semaphore, FIFO, etc.Core nts & TimeEvent-driven simulationData Types4-valued Logic type4-valued Logic VectorsBits and Bit VectorsArbitrary Precision IntegersFixed-point typesC user-defined typesC Language Standard 2009 XtremeEDA USA Corporation - Version 090820.10Copyright (C) 2009 by XtremeEDA Corporation.All rights reserved.Page 15 of 4815

Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David BlackA Simple Module – conceptual (not pegmodule image(ccd p,out);// capture pictureendmodulemodule jpeg(raw,jpg);// compress imageendmodulemodule fifo(in,out);// buffer odule camera(ccd p,img p);image M1( );fifo CH1( );image M2( );endmodule camera; 2009 XtremeEDA USA Corporation - Version 090820.10Restricted materialSC MODULE Anatomy - moduleSC MODULE(module name){// port declarations// channel declarations// variable declarations// event declarations// process declarations// helper method declarations// module instantiationsSC CTOR(module name): // initialization list{// connectivity// process registration}}; 2009 XtremeEDA USA Corporation - Version 090820.10Copyright (C) 2009 by XtremeEDA Corporation.All rights reserved.Page 16 of 4816

Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David BlackModule declaration//Filename: Camera.h#include systemc // Sub-module declarationsstruct Camera: public sc module{// Ports// Local channels & instances// Local events// Processes// ConstructorCamera(sc module name nm);private:// Helper member functions// Local data};Class declarationcameraimagefifojpeg 2009 XtremeEDA USA Corporation - Version 090820.10Restricted materialSC MODULE Anatomy - portsSC MODULE(module name) {//port declarations//channel declarations//variable declarations//event declarations//process declarations//helper method declarations//module instantiationsSC CTOR(module name): //.init list {//connectivity//process registration}}; 2009 XtremeEDA USA Corporation - Version 090820.10Copyright (C) 2009 by XtremeEDA Corporation.All rights reserved.Page 17 of 4817

Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David BlackSC MODULE Graphical ViewModuleconnections outerM1 mi1p1p6pAif1pBpG pCif6M2 mi2Ch1 )if5ev1p2InterfaceCh3 ci3ev2pr1p3ifF(dash )if2Ch2 ci2ifYifXp5ifZif4pr3pr2Ch channel If interface M module P port/pointer Pr processp4Channel(hex) 2009 XtremeEDA USA Corporation - Version 090820.10Restricted materialSC PORTInterface(aka API)sc fifo int c;“points tothe channel viathe interface”write() read() modA mAmodB mBsc port sc fifo out if int pAA threadpA- write(v);sc port sc fifo in if int pBB threadv pB- read();Pointer Access 2009 XtremeEDA USA Corporation - Version 090820.10Copyright (C) 2009 by XtremeEDA Corporation.All rights reserved.Page 18 of 4818

Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David BlackPort Declarationssc port interface type port name;SC MODULE(fir arch) {//Port Declarationssc port sc fifo in if double sc port sc fifo out if double }; //end fir archdata i;data o;templated interfacej data i- read();data i- read(j);data o- write(k); 2009 XtremeEDA USA Corporation - Version 090820.10Restricted materialPorts added//Filename: Camera.h#include systemc // Sub-module declarationsstruct Camera : public sc module {// Portssc port ccd p if ccd p;sc port firewire if img p;// Local channels & instances// Local events// Processes// ConstructorCamera(sc module name nm);private:// Helper member functions// Local data};Ports boundto interfacescameraccd pimagefifojpegimg p 2009 XtremeEDA USA Corporation - Version 090820.10Copyright (C) 2009 by XtremeEDA Corporation.All rights reserved.Page 19 of 4819

Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David BlackSC EXPORTmodA mAsc export sc fifo in if int pAsc fifo int c;write() read() “exports theinterface ofthe channel”Direction ofsubroutine callreversed.modB mBA threadc.write(v);sc port sc fifo in if int pBB threadv pB- read();Pointer Access 2009 XtremeEDA USA Corporation - Version 090820.10Restricted materialSC MODULE Anatomy - channelsSC MODULE(module name) {//port declarations//channel declarations//variable declarations//event declarations//process declarations//helper method declarations//module instantiationsSC CTOR(module name): //.init list {//connectivity//process registration}}; 2009 XtremeEDA USA Corporation - Version 090820.10Copyright (C) 2009 by XtremeEDA Corporation.All rights reserved.Page 20 of 4820

Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David BlackChannel Declarationschannel typechannel name;SC MODULE(fir arch) {//Channel Declarationssc fifo double orig in fifo; //stimulus to resultssc fifo double data in fifo; //stimulus to filtersc fifo double data out fifo;//filtered data }; //end fir archtemplated channel typej orig in fifo.read();data in.read(j);data out fifo.write(k);// Example using channels 2009 XtremeEDA USA Corporation - Version 090820.10Restricted materialChannels added//Filename: Camera.h#include systemc struct Camera : public sc module {// Portssc port ccd p if ccd p;sc port firewire if img p;// Local channels & instancessc fifo image t CH1;// Local events// Processes// ConstructorCamera(sc module name nm);private:// Helper member functions// Local data};cameraccd pimagefifojpegimg p 2009 XtremeEDA USA Corporation - Version 090820.10Copyright (C) 2009 by XtremeEDA Corporation.All rights reserved.Page 21 of 4821

Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David BlackSC MODULE Anatomy - variablesSC MODULE(module name) {//port declarations//channel declarations//variable declarations//event declarations//process declarations//helper method declarations//module instantiationsSC CTOR(module name): //.init list {//connectivity//process registration}}; 2009 XtremeEDA USA Corporation - Version 090820.10Restricted materialVariable Declarations Simply member data – Local to all methods in module– C data types– User Defined data types– SystemC data typesSC MODULE(fir arch) { sc uint 16 m taps;unsignedm tap;unsignedm results cnt;char*m cfg filename;};//end fir arch 2009 XtremeEDA USA Corporation - Version 090820.10Copyright (C) 2009 by XtremeEDA Corporation.All rights reserved.Page 22 of 4822

Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David BlackSC MODULE Anatomy - eventsSC MODULE(module name) {//port declarations//channel declarations//variable declarations//event declarations//process declarations//helper method declarations//module instantiationsSC CTOR(module name): //.init list {//connectivity//process registration}}; 2009 XtremeEDA USA Corporation - Version 090820.10Restricted materialEvent Declarationssc event event name, event name,. ; Event object– Event is a basic synchronization object– Event is used to synchronize between processes– Channels use events to implement blocking– Event has no data type, only control– Declared inside of a module Used for synchronization between the processes inside a module Declare as many as wantedSC MODULE(fir sys) { //Event Declarationssc event fir done evt; }; //end fir sys 2009 XtremeEDA USA Corporation - Version 090820.10Copyright (C) 2009 by XtremeEDA Corporation.All rights reserved.Page 23 of 4823

Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David BlackEvent NotifyThe sc event class has the following methods:void notify( )void notify( const sc time& )void notify( double, sc time unit )//within a simulation processsc time time out(10,SC MS); event1.notify();event2.notify(time out);event3.notify(1, SC NS); Will discuss making simulation processes “sensitive” to events later 2009 XtremeEDA USA Corporation - Version 090820.10Restricted materialnotify() Behaviors Three notify() behaviors– Immediate notification Causes processes which are sensitive to the event to be madeimmediately ready to run– Run in the current evaluate phase– Useful for modeling software systems and operating systems,which lack the concept of delta cycles– Delayed Causes process which are sensitive to the event to be made ready torun in the next evaluate phase– Timed notification Causes processes which are sensitive to the event to be made readyto run at a specified time in the future 2009 XtremeEDA USA Corporation - Version 090820.10Copyright (C) 2009 by XtremeEDA Corporation.All rights reserved.Page 24 of 4824

Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David BlackSC MODULE Anatomy - processesSC MODULE(module name) {//port declarations//channel declarations//variable declarations//event declarations//process declarations//helper method declarations//module instantiationsSC CTOR(module name): //.init list {//connectivity//process registration}}; 2009 XtremeEDA USA Corporation - Version 090820.10Restricted materialSimulation Processes Functionality is described in simulation processes C Methods “registered” with the simulation kernel– Simulation kernel is the ONLY legal caller– Called based on the sensitivity (discussed later)– SC METHOD processes execute when called and returncontrol to the calling mechanism behave like ordinary C method Verilog always block or VHDL process– SC THREAD and SC CTHREAD processes are called once,and then can suspend themselves and resume executionlater behave like threads Verilog initial block 2009 XtremeEDA USA Corporation - Version 090820.10Copyright (C) 2009 by XtremeEDA Corporation.All rights reserved.Page 25 of 4825

Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David BlackProcess Types Three different process types:– Methods (SC METHOD)– Threads (SC THREAD)– Clocked Threads (SC CTHREAD) – will be deprecated May have many processes inside the same moduleProcess Usage: System architectural models tend to use Threads System Performance models tend to use primarily Threads Transaction Level Models tend to use primarily Threads Behavioral synthesis uses clocked Threads only RTL models use Methods Test benches may use all process types 2009 XtremeEDA USA Corporation - Version 090820.10Restricted materialSC THREAD Runs only when invokedby the SystemC scheduler(part of SystemC kernel) Invoked based upon:– Start of simulation– Sensitivity To event(s) in channelsconnected to ports To event(s) in localchannels Local declared events(sc event) To time delays When SC THREADprocess is invoked:– Statements are executeduntil a wait statement isencountered– At the next wait()statement, the processexecution is suspended– At the next reactivation,process execution startsfrom the statementfollowing the wait 2009 XtremeEDA USA Corporation - Version 090820.10Copyright (C) 2009 by XtremeEDA Corporation.All rights reserved.Page 26 of 4826

Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David BlackSC THREAD Implemented as a method– Takes no arguments– Supplies no return value– Uses wait() to suspend Typically implemented with aninfinite loop– Ensures that the process canbe repeatedly reactivated– Allows for suspension andreactivation at different points– If no infinite loop then processis executed only oncevoid main thread(void){for(;;) {// Behaviorwait(args );}//endforever//Completely finishedreturn;} May be desired - like in a testbench for example 2009 XtremeEDA USA Corporation - Version 090820.10Restricted materialSC METHOD Runs only when invokedby the SystemC scheduler(part of SystemC kernel) Invoked based upon:– Start of simulation– Sensitivity To event(s) in channelsconnected to ports To event(s) in localchannels Local declared events(sc event) To time delays When SC THREADprocess is invoked:– Once invoked Entire body of the processis executed Must return– Upon completion returnsexecution control back tothe simulation kernel 2009 XtremeEDA USA Corporation - Version 090820.10Copyright (C) 2009 by XtremeEDA Corporation.All rights reserved.Page 27 of 4827

Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David BlackSC METHOD Implemented as a method– Takes no arguments– Supplies no return value– Re-invoked as needed– May use next trigger() May not use infinite loop– Execution would neverterminate - hang– May not have wait()– Uses next trigger()void my method(void){//Behaviorint local i;next trigger(args );return;//until re-invoked} Local variables redefined eachtime invoked.– Need to save the state of theprocess in member variables 2009 XtremeEDA USA Corporation - Version 090820.10Restricted materialSC MODULE Anatomy - subroutinesSC MODULE(module name){// port declarations// channel declarations// variable declarations// event declarations// process declarations// helper method declarations// module instantiationsSC CTOR(module name): // initialization list{// connectivity// process registration}}; 2009 XtremeEDA USA Corporation - Version 090820.10Copyright (C) 2009 by XtremeEDA Corporation.All rights reserved.Page 28 of 4828

Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David BlackSubroutines - Helper Processes/Subroutines C Methods (Member functions)– Same C rules Called from Simulation Processes (or the Constructor) Adds readability and reusability NOTE: Can use ordinary C-functions too; however,– Cannot access module data directly– Pass explicit arguments 2009 XtremeEDA USA Corporation - Version 090820.10Restricted materialSimulation Process - Declaration A processes are C functions (usually within module) Declared functions that take and return void Need to “register” with the simulation kernelSC MODULE(fir sys){ // Simulation Processesvoid stimulus thread(void);void fir thread(void);void results method(void);// Helper Processesvoid read cfg(void);. . .}; //end fir sys 2009 XtremeEDA USA Corporation - Version 090820.10Copyright (C) 2009 by XtremeEDA Corporation.All rights reserved.Page 29 of 4829

Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David BlackSimulation Process - ImplementationRecommended Style - define implementation in a separatefile (module name.cpp)void fir sys::stimulus thread(void) { for (int t 0; t ! STIM PTS; t) {double data 0.0;if (t IMP PT) data 1.0; //impulseorig in fifo.write(data);data in fifo.write(data);}//endfor}//end fir sys::stimulus thread()Implied wait ()within sc fifo 2009 XtremeEDA USA Corporation - Version 090820.10Restricted materialSimulation Process Implementationvoid fir sys::results method(void) {while(data out fifo.num available() 0) {m results cnt ;cout "DATA: " "[" setw(2) m results cnt "]" " " setw(9) fixed setprecision(5) orig in fifo.read() " " setw(9) fixed setprecision(5) data out fifo.read() endl;}//endwhileassumes staticnext trigger();sensitivity - TBD}//end fir sys::results method() 2009 XtremeEDA USA Corporation - Version 090820.10Copyright (C) 2009 by XtremeEDA Corporation.All rights reserved.Page 30 of 4830

Restricted for use by registeredUniversity of Texas students only.System Modeling and SystemCA Rapid Introduction by David BlackSub-module instances added//Filename: Camera.h#include systemc // Sub-module declarationsstruct Camera : public sc module {// Portssc port ccd p if ccd p;sc port firewire if img p;// Local channels & instancessc fifo image t CH1;image M1;jpeg M2;// Processes// ConstructorCamera(sc module name nm);private:// Helper member functions// Local dataccd p};cameraimagejpegfifoimg p 2009 XtremeEDA USA Corporation - Version 090820.10Restricted materialSC MODULE Anatomy - ConstructorSC MODULE(module name) {//port declarations//channel declarations//variable declarations//event declarations//process declarations//helper method declarations//module instantiationsSC CTOR(module name): //.init list {//connectivity//pr

SystemC Primer by Jayram Bhasker 2004 Transaction-Level Modeling with SystemC - TLM Concepts and Applications for Embedded Systems by Frank Ghenassia 2005 SystemC Books: Details Restricted for use by registered University of Texas students only. System Modeling and SystemC A Rapid Introduction by David Black