WIXLIB

Module ConstructorConstructor: can use a macro SC CTOR() where eachmodule has a constructor using the method or thread macros.SC METHOD (funct) ; // Identifies the function or process ‘funct’Methods or Threads are called similar to C as:SC CTOR(cpu) {cout "cpu::constructor()" endl;//confirming constructor// register the method/thread that will be called when sc start() is calledSC METHOD(funct);}; SC METHOD process is triggered by events and executes all thestatements in it before returning control to the SystemC kernel. A Method needs to be made sensitive to some internal or externalsignals. e.g. sensitive pos clock or sensitive neg clock Process and threads get executed automatically in the constructor,even if an event in sensitivity list does not occur. To prevent thisun-intentional execution, dont initialize() function is used. G. KhanCOE838: Systems on Chip Design,SystemC & SoC Modelling and Co-designPage: 25

SystemC ModuleSC MODULE(module name) {// Ports declaration// Signals declaration// Module constructor : SC CTOR// Process constructors and sensibility list//SC METHOD // or (SC THREAD)// Sub-Modules creation and port mappings// Signals initialization}moduleprocessmodule G. KhanCOE838: Systems on Chip Design,processmoduleSystemC & SoC Modelling and Co-designPage: 26

Signals and PortsPorts of a module are the external interfaces that pass information toand from a module.sc inout data type port name; Create an input-output port of ‘data type’ with name‘port name’. sc in and sc out create input and output ports respectively.Signals are used to connect module ports allowing modules tocommunicate.sc signal data type sig name ; Create a signal of type ‘data type’ and name it ‘sig name’. hardware module has its own input and output ports to whichthese signals are mapped or bound.For example:in tmp in.read( );out.write(out temp); G. KhanCOE838: Systems on Chip Design,//reads the port in to in tmp//writes out temp to the out portSystemC & SoC Modelling and Co-designPage: 27

2-to-1 Mux ModulesModule constructor – SC CTOR is Similar to an“architecture“ in VHDLSC MODULE( Mux21 ) {sc in sc uint 8 in1;sc in sc uint 8 in2;sc in bool selection;sc out sc uint 8 out;void MuxImplement( void );SC CTOR( Mux21 ) {SC METHOD( MuxImplement );sensitive selection;sensitive in1;sensitive in2;}} G. KhanCOE838: Systems on Chip Design,SystemC & SoC Modelling and Co-designPage: 28

sc main()The top level is a special function called sc main. It is in a file named main.cpp or main.c sc main() is called by SystemC and is the entry point foryour code. The execution of sc main() until the sc start()function is called.int sc main (int argc, char *argv []) {// body of functionsc start(arg) ;return 0 ;} sc start(arg) has an optional argument:It specifies the number of time units to simulate.If it is a null argument the simulation will run forever. G. KhanCOE838: Systems on Chip Design,SystemC & SoC Modelling and Co-designPage: 29

Lab1: Flip-Flop Module#include systemc.h SC MODULE(flipflop) {sc in bool clk;sc in bool enable;sc in sc uint 3 din;sc out sc uint 3 dout;void ff method();SC CTOR(flipflop) {SC METHOD(ff method);dont initialize();sensitive clk.pos(); // ve edge sensitive}}; G. KhanCOE838: Systems on Chip Design,SystemC & SoC Modelling and Co-designPage: 30

Lab1: Flip-Flopsc int 3 data;void flipflop :: ff method() {//after every rising edge, check if enabledcout "Enable " enable.read() ", output ";if(enable.read() 1){data din.read();dout.write(din.read()); }cout data.to string(SC BIN) endl;}From the sc main() shown earlier, we can identify 3 phases:Elaboration Phase: everything before the call of sc start() function.This phase is used to declare modules, clocks, make connections etc.Simulation Phase: Execution of the sc start() functionPost-processing Phase: The code after sc start(). Handle the results ofsimulation (determine if a test passed or not), close any stimuli files, etc. G. KhanCOE838: Systems on Chip Design,SystemC & SoC Modelling and Co-designPage: 31

Lab1: Flip-Flop Testing#include systemc.h int sc main(int argc, char* argv[]){sc trace file *tf;// Create VCD file for tracingsc signal sc uint 3 data in, data out; //Declare signalssc signal bool en;sc clock clk("clk",10,SC NS,0.5); //Create a clock signal flipflopDUT("flipflop"); //Create Device Under Test (DUT)DUT.din(data in); // Connect/map the ports to testbench signalsDUT.dout(data out); DUT.clk(clk);DUT.enable(en);// Create wave file and trace the signals executingtf sc create vcd trace file("trace file");tf- set time unit(1, SC NS);sc trace(tf, clk, "clk"); sc trace(tf, en, "enable");sc trace(tf, data in, "data in"); sc trace(tf, data out, "data out");cout "\nExecuting flip flop example. check .vcd produced" endl;//start the testbench G. KhanCOE838: Systems on Chip Design,SystemC & SoC Modelling and Co-designPage: 32

Lab1: Flip-Flop Testing --cont.//start the testbenchen.write(0); //initializedata in.write(0); sc start(9, SC NS);en.write(1); //enable and inputdata in.write(7); sc start(10, SC NS);data in.write(6); sc start(10, SC NS);data in.write(5); sc start(10, SC NS);en.write(0); //not enabled and input scenariodata in.write(6); sc start(10, SC NS);en.write(1); //enableddata in.write(1); sc start(10, SC NS);data in.write(0); sc start(10, SC NS);sc close vcd trace file(tf);return 0;} G. KhanCOE838: Systems on Chip Design,SystemC & SoC Modelling and Co-designPage: 33

Connecting SystemC sub-modulesSignalssc signal type q, s, c; Positional Connection Named Connection G. KhanCOE838: Systems on Chip Design,SystemC & SoC Modelling and Co-designPage: 34

Named and Positional ConnectionsSC MODULE(filter) {// Sub-modules: “components”sample *s1;coeff *c1;mult*m1;sc signal sc uint 32 q,s,c;// Constructor :“architecture”SC CTOR(filter) {//Sub-modules instantiation/mappings1 new sample (“s1”);s1- din(q);// named mappings1- dout(s);c1 new coeff(“c1”);c1- out(c);// named mappingm1 new mult (“m1”);(*m1)(s, c, q)//positional mapping}} G. KhanCOE838: Systems on Chip Design,SystemC & SoC Modelling and Co-designPage: 35

SystemC Counter Module#include "systemc.h"#define COUNTERstruct counter : sc module {// the counter modulesc inout int in;// the input/output port of int typesc in bool clk;// Boolean input port for clockvoid counter fn();// counter module functionSC CTOR( counter ) {// counter constructorSC METHOD( counter fn ); // declare the counter fn as methoddont initialize();// don’t run it at first executionsensitive pos clk; // make it sensitive to ve clock edge}};void counter :: counter fn() {in.write(in.read() 1);printf("in %d\n", in.read());} G. KhanCOE838: Systems on Chip Design,SystemC & SoC Modelling and Co-designPage: 36

SystemC Counter Modulestruct counter : sc module { // the counter modulesc inout int in; // the input/output port of int typesc in bool clk; // Boolean input port for clockvoid counter fn(); // counter module functionSC CTOR( counter ) {SC METHOD( counter fn ); // declare the counter fn as a methoddont initialize(); // don’t run it at first executionsensitive pos clk; // make it sensitive to ve clock edge}}// software block that check/reset the counter value, part of sc mainvoid check for 10(int *counted) {if (*counted 10) {printf(“Max count (10) reached . Reset count to Zero\n");*counted 0;}} G. KhanCOE838: Systems on Chip Design,SystemC & SoC Modelling and Co-designPage: 37

BCD Counter Example Main Codevoid check for 10 (int *counted);int sc main(int argc, char *argv[ ]) {sc signal int counting; // the signal for the counting variablesc clock clock("clock",20, 0.5); // clock period 20 duty cycle 50%int counted; // internal variable, to store the value in counting signalcounting.write(0); // reset the counting signal to zero at startcounter COUNT("counter"); // call counter moduleCOUNT.in(counting); // map the ports by nameCOUNT.clk(clock); // map the ports by namefor (unsigned char i 0; i 21; i ) {counted counting.read(); // copy the signal onto the variablecheck for 10(&counted); // call the software block & check for 10counting.write(counted); // copy the variable onto the signalsc start(20);// run the clock for one period} return 0;} G. KhanCOE838: Systems on Chip Design,SystemC & SoC Modelling and Co-designPage: 38

Counter Main Code with Tracingint sc main(int argc, char *argv[ ]) {sc signal int counting; // the signal for the counting variablesc clock clock("clock", 20, 0.5); // clock; time period 20 duty cycle 50%int counted; // internal variable, to stores the value in counting signal// create the trace- file by the name of "counter tracefile.vcd“sc trace file *tf sc create vcd trace file("counter tracefile");// trace the clock and the counting signalssc trace(tf, clock.signal(), "clock");sc trace(tf, counting, "counting");counting.write(0); // reset the counting signal to zero at startcounter COUNT("counter"); // call counter module. COUNT is just a temp varCOUNT.in(counting); // map the ports by nameCOUNT.clk(clock); // map the ports by namefor (unsigned char i 0; i 21; i ) { .}sc close vcd trace file(tf); // close the tracefilereturn 0;} G. KhanCOE838: Systems on Chip Design,SystemC & SoC Modelling and Co-designPage: 39

Communication andSynchronization SystemC 2.0 and higher has general-purpose Channel A mechanism for communication and synchronization They implement one or more interfaces Interface Specify a set of access methods to the channelBut it does not implement those methods Event Flexible, low-level synchronization primitive Used to construct other forms of synchronization G. KhanCOE838: Systems on Chip Design,SystemC & SoC Modelling and Co-designPage: 40

Communication ventsPorts to Interfaces G. KhanCOE838: Systems on Chip Design,SystemC & SoC Modelling and Co-designPage: 41

Interfaces Interface is purely functional and does not provide theimplementation of the methods. Interface only provides the method's signature. Interfaces are bound to ports. They define what can be done through a particular port. The implementation is doneinside a channel. G. KhanCOE838: Systems on Chip Design,SystemC & SoC Modelling and Co-designPage: 42

Channels Channel implements an interfaceIt must implement all of its defined methods. Channel are used for communication between processes insideof modules and between modules. Inside of a module a process may directly access a channel. If a channel is connected to a port of a module, the processaccesses the channel through the port. G. KhanCOE838: Systems on Chip Design,SystemC & SoC Modelling and Co-designPage: 43

Channels G. KhanCOE838: Systems on Chip Design,SystemC & SoC Modelling and Co-designPage: 44

ChannelsTwo types of Channels: Primitive and Hierarchical Primitive Channels: They have no visible structure and no processes Theye cannot directly access other primitive channels.oooooosc signalsc signal rvsc fifosc mutexsc semaphoresc buffer Hierarchical Channels: These are modules themselves, may contain processes, other modules etc. may directly access other hierarchical channels. G. KhanCOE838: Systems on Chip Design,SystemC & SoC Modelling and Co-designPage: 45

Channel UsageUse Primitive Channels: when you need to use the request-update semantics. when channels are atomic and cannot reasonably bechopped into smaller pieces. when speed is absolutely crucial. Using primitive channels can often reduce the number of deltacycles. when it doesn't make any sense i.e. trying to build achannel out of processes and other channels such as asemaphore or a mutex.Use Hierarchical Channels: when you would want to be able to explore the underlyingstructure, when channels contain processes or ports, when channels contain other channels. G. KhanCOE838: Systems on Chip Design,SystemC & SoC Modelling and Co-designPage: 46

Processes: method, thread or cthreadProcesses are functions identified to the SystemC kerneland called if a signal of the sensitivity list changes. Processes implement the funcionality of modules. Similar to C functions or methodsThree types of Processes: Methods, Threads and Cthreads Methods : When activated, executes and returnsSC METHOD(process name) Threads: can be suspended and reactivated- wait( ) - suspends- one sensitivity list event - activatesSC THREAD(process name) Cthreads: are activated by the clock pulseSC CTHREAD(process name, clock value); G. KhanCOE838: Systems on Chip Design,SystemC & SoC Modelling and Co-designPage: 47

ProcessesTypeSC METHODSC THREADSC CTHREADActivates Exec.Event in sensit.listEvent in sensit.ListClock pulseSuspendsExec.NOYESYESInfinite LoopNOYESYESsuspended/reactivated byN/AHas embeddedwait()wait()wait()wait until()ConstructorandSensibilitydefinition G. KhanSC METHODSC THREAD(call back);(call back);sensitive (signals);sensitive(signals);sensitive pos(signals); sensitive pos(signals);sensitive neg(signals); sensitive neg(signals);COE838: Systems on Chip Design,SystemC & SoC Modelling and Co-designSC CTHREAD(call back,clock.pos() );SC CTHREAD(call back,clock.neg());Page: 48

Sensitivity List of a Process sensitive with the ( ) operatorTakes a single port or signal as argumentsensitive(s1);sensitive(s2);sensitive(s3) sensitive with the stream notationTakes an arbitrary number of argumentssensitive s1 s2 s3; sensitive pos with either ( ) or operatorDefines sensitivity to positive edge of Boolean signal or clocksensitive pos clk; sensitive neg with either ( ) or operatorDefines sensitivity to negative edge of Boolean signal or clocksensitive neg clk; G. KhanCOE838: Systems on Chip Design,SystemC & SoC Modelling and Co-designPage: 49

Multiple Process ExampleSC MODULE(ram) {sc in int addr;sc in int datain;sc in bool rwb;sc out int dout;int memdata[64];// local memory storageint i;void ramread(); // process-1void ramwrite();// process-2SC CTOR(ram){SC METHOD(ramread);sensitive addr rwb;SC METHOD(ramwrite);sensitive addr datain rwb;for (i 0; i ; i 64) {memdata[i] 0;} }}; G. KhanCOE838: Systems on Chip Design,SystemC & SoC Modelling and Co-designPage: 50

Thread Process and wait() function wait( ) may be used in both SC THREAD and SC CTHREADprocesses but not in SC METHOD process block wait( ) suspends execution of the process until the process isinvoked again wait( pos int ) may be used to wait for a certain number ofcycles (SC CTHREAD only)In Synchronous process (SC CTHREAD) Statements before the wait( ) are executed in one cycle Statements after the wait( ) executed in the next cycleIn Asynchronous process (SC THREAD) Statements before the wait( ) are executed in the last event Statements after the wait( ) are executed in the next event G. KhanCOE838: Systems on Chip Design,SystemC & SoC Modelling and Co-designPage: 51

Thread Process and wait() functionvoid do count() {while(1) {if(reset) {value 0;}else if (count) {value ;q.write(value);}wait(); // wait till next event !}} G. KhanCOE838: Systems on Chip Design,SystemC & SoC Modelling and Co-designPage: 52

Example Codevoid wait example:: my thread process(void){wait(10, SC NS);cout "Now at " sc time stamp() endl;sc time t DELAY(2, SC MS);t DELAY * 2;cout "Delaying " t DELAY endl;wait(t DELAY);cout "Now at " sc time stamp() endl;}OUTPUT G. KhanCOE838: Systems on Chip Design,SystemC & SoC Modelling and Co-designPage: 53

Thread ExampleSC MODULE(my module) {sc in bool id;sc in bool clock;sc in sc uint 3 in a;sc in sc uint 3 in b;sc out sc uint 3 out c;void my thread();Thread Implementation//my module.cppvoid my module::SC CTOR(my module){my thread(){SC THREAD(my thread);while(true){sensitive clock.pos(); if (id.read())}out c.write(in a.read());};elseout c.write(in b.read());wait();}}; G. KhanCOE838: Systems on Chip Design,SystemC & SoC Modelling and Co-designPage: 54

CThread Almost identical to SC THREAD, but implements“clocked threads” Sensitive only to one edge of one and only oneclock It is not triggered if inputs other than the clockchange Models the behavior of unregistered inputs andregistered outputs Useful for high level simulations, where the clock isused as the only synchronization device Adds wait until( ) and watching( ) semantics for easydeployment. G. KhanCOE838: Systems on Chip Design,SystemC & SoC Modelling and Co-designPage: 55

Opposite ExampleSC MODULE(countsub){sc in double in1;sc in double in2;sc out double sum;sc out double diff;sc in bool clk;void addsub();// Constructor:SC CTOR(countsub){// declare addsub as SC METHODSC METHOD(addsub);// make it sensitive to// positive clocksensitive pos clk;}}; G. KhanCOE838: Systems on Chip Design,in1in2sumaddersubtractordiffclk// addsub methodvoid countsub::addsub(){double a;double b;a in1.read();b in2.read();sum.write(a b);diff.write(a-b);};SystemC & SoC Modelling and Co-designPage: 56

Clocks Special object How to create ?sc clock clock name ( “clock label”, period,duty ratio, offset, initial value ); Clock connectionf1.clk( clk signal ); //where f1 is a module Clock example:sc clock clock1 ("clock1", 20, 0.5, 2, true);2 G. Khan12COE838: Systems on Chip Design,223242SystemC & SoC Modelling and Co-designPage: 57

sc timesc time data type to measure time. Time is expressed in two parts:a numeric magnitude and a time unit e.g. SC MS, SC NS,SC PS, SC SEC, etc.sc time t(20, SC NS);// var t of type sc time with value of 20nsMore Examples:sc timet PERIOD(5, SC NS) ;sc timet TIMEOUT (100, SC MS) ;sc timet MEASURE, t CURRENT, t LAST CLOCK;t MEASURE (t CURRENT-t LAST CLOCK) ;if (t MEASURE t HOLD) { error ("Setup violated") } G. KhanCOE838: Systems on Chip Design,SystemC & SoC Modelling and Co-designPage: 58

Hardware-Software Codesign Co-design of Embedded Systems consists of the following parts: Co-Specification Developing system specification that describes hardware, software modules and relationship between the hardware and software Co-Synthesis Automatic and semi-automatic design of hardware and software modules to meet the specification