Transcription
ASSOCIATION CONNECTINGELECTRONICS INDUSTRIESIPC-SM-780Component Packagingand Interconnectingwith Emphasis onSurface MountingANSI/IPC-SM-780July 1988A guideline developed by IPC2215 Sanders Road, Northbrook, IL 60062-6135Tel. 847.509.9700 Fax 847.509.9798www.ipc.org
IPC-SM-780July 1988Table of Contents1.0INTRODUCTION . 11.11.2Scope. 1Purpose . 11.31.41.4.11.4.21.4.31.4.4Classification.Terms and Definitions .Castellations.Chip Carrier .Coefficient of Thermal Expansion Mismatch .Component.1.4.51.4.6Component Mounting Site . 2Constraining Core. 21.4.71.4.8Double-Sided Assembly . 2Dual In-Line Package. 21.4.9Flat Pack . 21.4.10Footprint . 21.4.11Grid . 21.4.12Integrated Circuit (IC). 21.4.13Land Pattern . 21.4.14Leaded Chip Carrier. 21.4.15Leadless Chip Carrier. 21.4.16Mixed Mounting Technology. 21111121.4.17Packaging and Interconnecting Structure . 21.4.18Primary Side . 21.4.19Secondary Side . 21.4.20Single In-Line Package . 21.4.21Single-Sided Assembly. 21.4.22Supporting Plane . 21.4.23Surface Mounting . 21.4.241.4.25Thermal Expansion Mismatch . 2Via Hole. 22.0REFERENCE DOCUMENTS . 32.1Institute for Interconnecting and PackagingElectronic Circuits (IPC). 32.2Electronic Industries Association (EIA) . 32.3Military . 32.3.1Standards . 32.3.2Specifications . 42.4Federal . 42.5American National Standards Institute(ANSI) . 43.0COMPONENT PACKAGING ANDINTERCONNECTION (CPI) IMPLEMENTATIONCONCEPT . 4iv3.1System Design Sequence . .13.3.2System Requirements . 5Circuit Requirements. 5Performance Considerations. 6Reliability Considerations . 6System Integration. 7Technology Trends . 9Package Technology . 10Interconnect Technology . 10Size Considerations . 11Packaging/Interconnection AssemblyImplementation Techniques. 11Comparisons . 12Size . 123.3.3Through-Hole Mounting Technology . 133.3.4Surface Mount Technology . 143.3.5Intermixed Technology. 163.3.6Other Considerations . 174.0ELECTRONIC COMPONENT TYPES ANDINTERCONNECTION DEVICES . 174.1General Considerations . 174.1.1Lead/Termination Finishes . 174.1.2Component Handling . 184.1.3Precleaning Techniques . 204.2Discrete Component Types . 204.2.1Axial Leaded . 204.2.2Radial Leaded Components . 204.2.3Chip Components (Leaded and Leadless). 204.2.4Direct Deposition . 224.2.5Switches . 234.2.6Other Devices . 234.3Semiconductor Package Types. 234.3.1Multileaded Radial Type Components. 244.3.2Small Outline Packages . 244.3.3In-Line Packages Configurations . 264.3.4Ribbon Multileaded Component Types(Flat Packs and Quad Packs) . 284.3.5Chip Carriers (Leaded and Leadless) . 294.3.6Grid Arrays . 364.4Sockets and Connectors . 384.4.1Materials . 384.4.2Lead Configuration and Spacing . 384.4.3Socket Types. 39
July 19884.4.45.0IPC-SM-780Connectors . 41PACKAGING AND INTERCONNECTINGSTRUCTURE (P&IS) TYPE . 426.2.3Electrical Configuration . 546.2.46.2.56.2.66.2.76.2.86.2.9Component Considerations .Cost Consideration .Design Checklist.Reliability .Thermal Management.Vibration and 2.156.2.166.2.17Simplified Cyclic Strain Considerations.Power Consumption .Power Cycling .Warpage and Rigidity.Testing.High Speed .High Frequency .EMI/RFI.5656565657575757Parasitic Elements .ESD.EOS.Commonality .Pin Count .Storage and Handling.Safety and Handling.595959595960605.15.1.1General Considerations . 44Categories . 465.1.25.1.35.1.45.1.55.25.2.1Design .Performance .Thermal Expansion Mismatch .Chip-on-Board/TAB .Organic-Base Material P&IS .Epoxy-Fiberglass Materials.5.2.25.2.3Polyimide-Fiberglass Materials. 47Epoxy Aramid Fiber Materials . 475.2.45.2.55.2.65.2.75.2.8Polyimide Aramid Fiber Materials .Polyimide Quartz Materials .Fiberglass/Aramid Fiber Materials .Teflon Fiberglass Materials .Flexible-Dielectric Structures.5.2.95.3Thermoplastic Resin P&I Structures . 48Non-Organic Base Materials. 485.3.1Hybrid Circuits . 485.3.2Ceramic Printed Boards . porting-Plane P&I Structures. 486.3Packaging Considerations . 605.4.1Printed Board Bonded to Support Plane(Metal or Non-Metal). 485.4.2Sequentially-Processed Structures withMetal Support Plane. 49Density .Gross Estimate.Detail Estimate .Final Design Review .5.4.3Discrete-Wire Structures with MetalSupport Plane . 496.3.16.3.26.3.36.3.46.3.55.4.4Flexible Printed Board with MetalSupport Plane . 496.4Performance, Reliability and Producibility . 626.5CAD/CAM Relationships. 62464647474747474748484860606061End Product Considerations. 615.5Constraining Core P&I Structures . 506.6Testing Considerations . 645.5.1Porcelainized-Metal (Metal Core)Structures . 506.6.1Design to Test. 646.6.2Fan Out . 645.5.2Printed Board With Constraining (notelectrically functioning) Core . 516.7P&IS Design Issues. 645.5.3Printed Boards with Electrically-FunctionalConstraining Cores . 516.7.1Through-the-Board . 646.7.2Land Pattern Considerations . 66Printed Board With Constraining Core. 516.7.3Mixed Mounting. 73Compliant-Layer Structures . 526.7.4Chip-on-Board Considerations. 735.5.45.5.56.0DESIGN PARAMETERS . 527.0P&I STRUCTURE (P&IS) FABRICATION . 746.1General Considerations . 527.1Organic Printed Boards . 746.1.1Specifications . 527.2Constraining Core P&IS . 746.1.2Design Responsibilities . 547.2.1Types. 746.2System Requirements . 547.2.2Spray Coating Process . 746.2.1Partitioning . 547.2.3Electrophoretic Deposition Process . 74Mechanical Configurations. 547.2.4Fluidized Bed Process . 756.2.2v
IPC-SM-780July 19887.2.57.37.3.17.3.2Molding Process .Material Considerations .Incoming Tests.Safety .757575758.5.28.68.6.18.6.2Solder Preforms .Component Placement.Through Hole Placement .Manual .38.7Intermixed Technology. 106Surface Mounting . 1088.7.18.7.28.88.8.18.8.2Manual Assembly . 108Automated Assembly . 108Chip-on-Board Placement . 108Low-Volume Equipment . 109Fully-Integrated Systems. 1107.5.37.67.6.17.6.27.6.3Material Storage .Process Flow and Control .Process Flow Charts .Process Control Environmental Conditions.Fabricating Techniques .Parallel Processing for Multilayer PrintedBoards (Blind and Buried Vias) .Processing for Single-and DoubleSided Boards.Non-Organic Printed Board .Quality Conformance Coupons.Quantity and Location.Identification .Tolerances .8.98.9.1Component Attachment . 111Soldering, General . 1117.6.47.6.5Lands and Holes. 81Conductors . 828.9.28.9.38.9.48.9.58.10Wave Soldering. 111Reflow Soldering . 113Adhesive Bonding . 115Wire Bonding . 115Cleaning . 1177.6.67.6.77.6.87.6.9Etched Letters.Number of Layers .Coupon Length .Test Coupon Examples .8.10.18.10.28.11Post-soldering Cleaning. 117Surface Mount Considerations . 1178.11.1Masking. 1198.11.2Application . 1208.11.3Bake . 1208.11.4Handling . 1208.11.5Results. 1207.5.28.07780808181818182828282ASSEMBLY PROCESSES . 868.18.1.18.1.28.1.3General Considerations .P&IS Assembly Techniques .Epoxy Attachment 8787101101102103Conformal Coating . 1199.0QUALITY ASSURANCE AND TESTING . 1209.1Quality Assurance and Testing. 120Conformal Coating . 87Process Flow . 88Introduction. 889.1.1Preassembly Assurance . 1219.2Solderability. 1219.2.1Acceptable Solderability Criteria . 121Materials . 88Flux . 88Solders . 909.2.2Surface Solderability Tests. 1229.3Quality Assurance Provisions . 1239.3.1Materials Inspection . 123Adhesives. 929.3.2Quality Conformance Inspection . 1238.3.4Conformal Coating . 939.4Post Assembly Assurance. 1278.4Component Preparation . 949.4.1Visual Joint Inspection . 1278.4.1Through Hole Mounting . 949.4.2Verification Inspection. 1288.4.2Straight Through Leads. 949.4.3Workmanship . 1288.4.3Performed Leads. 959.5Mechanical and Electrical Testing . 1348.4.4Surface Mounting Leaded Components . 979.6Solder Joint Mechanism of Failure. 1358.4.5Surface Mounted Leadless Device . 989.7Handling Electronic Assemblies . 1368.4.6Connectors/Sockets. 999.7.1Metal Fatigue Failure . 1378.5Solder Placement . 1009.7.2Brittle Failure . 138Solder Paste Placement . 1009.7.3Overstress Conditions. 1388.5.1vi
July 1988IPC-SM-7809.7.4Handling and Shipping Damage . 13810.0MODIFICATION AND REPAIR. 13810.110.2Basic Rules . 138Handling Electronic Assemblies . 13910.2.110.2.210.2.3General Guidelines . 139Handling After Cleaning . 139Electrostatic Discharge (ESD) DamagePrevention . 13910.2.410.2.510.2.6Electrical Overstress (EOS) DamagePrevention . 139Warning Labels. 140EOS/ESD Sensitivity Markings . 14010.2.710.2.8Protective Methods . 140EOS/ESD Safe Work Station . 14110.310.3.110.3.210.3.310.3.410.4General Modification/Repair Procedures.Cleaning .Identification of Coatings.Coating Removal .Legends and Markings .P&I Structure Modification/Repair .10.5P&I Assembly Modification/RepairMethods .Removal and Replacement ofComponents .Heat Factors.Through-Hole Mounted Components 42142142Pin and hole locating feature. 19Figure 4-6Axial leaded component . 20Figure 4-7Radial lead (dipped) capacitor. 20Figure 4-8Radial lead transistor can. 20Figure 4-9Flat rectangular chip resistor . 21Figure 4-10Chip resistor constructions . 21Figure 4-11Multiple layer ceramic chip capacitor . 22Figure 4-12Chip capacitor package . 22Figure 4-13MELF body outlines. 22Figure 4-14A chip inductor . 22Figure 4-15Typical surface mount inductor. 23Figure 4-16Surface mount cermet trimmer. 23Figure 4-17‘‘TO’’ can outline drawing. 24Figure 4-18SOT-23 package. 25Figure 4-19SOT-89 package. 25Figure 4-20SOT-23 comparisons . 25Figure 4-21SOT-143 dimensions . 25Figure 4-2216-pin SO and SOL outline . 26Figure 4-23Proposed JEDEC outline for SOJ packages. 27Figure 4-24Typical DIP outline . 27Figure 4-25Typical SIP outline . 27Figure 4-26Typical QUIP outline . 28Figure 4-27Typical QUIL outline. 28Figure 4-28Flatpack outline. 28143143144Figure 4-29Quad pack configuration. 29Figure 4-30Typical ribbon leaded transistor. 29Figure 4-31The 50-mil center JEDEC packages . 30Surface Mounted Devices . 145Through-Hole and Surface MountedComponent Removal . 147Replacement of Surface MountedDevices . 148Figure 4-32Mounting compatibility of JEDEC packages . 31Figure 4-33Features common to the 50-mil centerpackages. 31Figure 4-34Type E package variations . 32FiguresFigure 3-1Figure 4-5Ideal connective length needed versusnumber of pins and package type (alldimensions in inches) . 6Figure 4-35A Chip carrier land pattern design . 32Figure 4-35B Leadless ceramic chip carrier attachedto a CTE-tailored P&I structure with soldercolumns. 33Figure 4-36Square plastic chip carrier. 34Figure 4-37Rectangular plastic chip carrier . 35Figure 4-38Double row plastic chip carrier . 36Figure 3-2Cooling option combinations . 8Figure 4-39Open-via chip carrier (OVCC) . 37Figure 3-3Packaging and assembling integratedcircuits (all dimensions in inches). 10Figure 4-40149-pin array package. 37Figure 4-41I/O density versus lead count. 37Figure 4-42Surface mount connector land patterncriteria . 39Figure 4-43Surface mount connector hold downfeatures . 39Figure 3-4Semiconductor technology development . 11Figure 3-5Gate density comparison (all dimensionsin inches) . 12Figure 3-6Packaging technology comparisons (alldimensions in inches) . 12Figure 3-7Joint geometries . 15Figure 4-1Interrelated package design factors . 18Figure 4-2Matrix tray . 19Figure 4-3Tube or magazine packaging . 19Figure 4-4Bulk packaging . 19Figure 4-44Surface mounting socket . 40Figure 4-45Section through socket solder contact . 40Figure 4-46Screw down cover . 41Figure 4-47Section through pressure-mounted socket. 42Figure 4-48Section through through-hole mountingsocket contact. 42vii
IPC-SM-780July 1988Figure 4-49Surface-mount DIP socket. 42Figure 4-50Pin grid array sockets. 43Figure 4-51Leadless grid array socket . 43Figure 4-52D-subminiature surface mount connector . 43Figure 4-53Surface mount receptacle. 44Figure 6–24 1.27 mm [0.050 in.] pitch chip carrier sitewith ‘‘II’’ fan out . 71Figure 4-54Box-contact surface mount receptacle . 44Figure 6–25 Modified fan out patterns. 71Figure 4-55Surface mount header . 44Figure 6–26 Peripheral fan out . 72Figure 4-56Surface mount card edge connector . 44Figure 6–27 Solid fan out. 72Figure 5-1Printed board bonded to supporting plane . 49Figure 6–28 High package density fan out. 72Figure 5-2Sequentially-processed structure withsupporting plane . 49Figure 6–29 Multilayer fabrication (standard parallelprocess with buried via layers) . 72Figure 5-3Discrete-wire structure with low-expansionmetal support plane . 50Figure 6–30 Buried via on internal layer between2.54 mm [0.100 in] centers through-vias. 72Figure 5-4Flexible printed board with metal supportplane . 50Figure 7-1Double-sided rigid printed board processflow chart . 76Figure 5-5Printed board with supporting plane (notelectrically-functional constraining core). 51Figure 7-2Multilayer board process flow chart. 77Figure 7-3Figure 5–6Multilayer P&I structure with copper-cladInvar power and ground planes(electrically-functional constraining cores). 51Multilayer flexible printed board processflow chart . 77Figure 7-4Rigid-flex multilayer process flow chart . 78Non-organic printed board process flowchart . 78Gang soldermask window . 80Figure 6–22 Land patterns for standard leadlesschip carriers (LCC) . 70Figure 6–23 1.27 mm [0.050 in] pitch chip carrier sitewith ‘‘IL’’ fan-out for leadless type C. 71Figure 5–7Balanced structure with constraining corenot at neutral axis . 52Figure 7-5Figure 5–8Balanced structure with constraining coreon neutral axis . 52Figure 7-6Figure 7-7Individual soldermask windows . 81Figure 5–9Compliant-layer P&I structure. 52Figure 7-8A B coupon (types 2 and 3) . 83Figure 6–1Design flow chart . 53Figure 7-9C coupon details. 83Figure 6–2Productivity plan . 54Figure 7-10D coupons details . 83Figure 6–3Manufacturing cost vs. complexity of circuit. 55Figure 7-11E coupon details . 84Figure 6–4P&I structure signal loop . 58Figure 7-12F coupon details (type 3). 84Figure 6–5Power ground interconnections . 58Figure 7-13G coupon details. 84Figure 6–6Decoupling capacitor placement . 59Figure 7-14H coupon details. 85Figure 6–7High I/O component decoupling capacitordesign . 59Figure 7-15J coupon details. 85Figure 8-1Minimum inside bend radius. 95Figure 8-2Single in-line component . 95Figure 8-3Staggered hole pattern mounting. ‘‘MO’’ flatpack outline drawing (only inches shown). . 96Figure 8-4Through hole mounting. ‘‘MO’’ flat packoutline drawing. 96Figure 6–12 Typical one-conductor routing . 66Figure 8-5Loop bends . 96Figure 6–13 Typical two-conductor routing . 66Figure 8-6Axial-lead stress relief . 96Figure 6–14 Typical three-conductor routing . 66Figure 8-7Stress relief leads . 96Figure 6–15 Staggered grid—3 lines/channel . 66Figure 8-8Simple-offset preformed leads. 96Figure 6–16 Chip resistor. 67Figure 8-9Dimple preformed leads . 97Figure 8-10Compound preformed leads . 97Figure 8-11Combination preformed leads . 97Figure 8-12Lead bend for surface mounting . 97Figure 8-13Lead bending requirements for surfacemounting . 97Figure 8-14SO-16 package drawings typicaldimensions. 98Figure 8-15Typical SOT packages. 99Figure 8-16Modifying DIP for surface mounting . 99Figure 6–8Crosstalk situation . 60Figure 6–9Design N/C documentation options. 63Figure 6–10 Clipped-land conductor routing (dimensionsin inches) .
IPC-SM-780 Component Packaging and Interconnecting with Emphasis on Surface Mounting ASSOCIATION CONNECTING ELECTRONICS INDUSTRIES 2215 Sanders Road, Northbrook, IL 60062-6135 Tel. 847.509.9700 Fax 847.509.9798 www.ipc.org ANSI/IPC-SM-780 July 1988 A guideline developed by IPC
