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MicroprocessorPackagingThe Key Link in the ChainKoushik BanerjeeTechnical AdvisorAssembly Technology DevelopmentIntel Corporation1
Microprocessors197120012
Global Packaging laysiaPenangVirtualVirtual ATDATD3
Main R&D facility inChandler, AZ4
Computing needsdrivingcomplexityFirst to introduce organic inmainstream CPUsFirst to introduce flip chip inmainstream CPUsIntel 486TM Pentium Processor ProcessorPentium Pro Pentium IIProcessorProcessor25 MHzCeramicTo OrganicPentium IIIProcessorPentium 4ProcessorItanium Processor1.0 GHzWire-bondTo Flip Chip5
Looking ahead Complexity and Challengesto support Moore’s Law1. Silicon to package interconnect2. Within package interconnect3. Power management4. Adding more functionalityGoalGoal :: BringBring technologytechnology innovationinnovation intointoHighHigh volumevolume manufacturingmanufacturing atat aa LOWLOW COSTCOST6
Silicon ? PackageRelationshipAnatomy 101Silicon Processor:The “brain” of the computer(generates instructions)Packaging:The rest of the body(Communicates instructionsto the outside world, addsprotection)NoNo PackagePackage NoNo ProductProduct !!GreatGreat PackagingPackaging GreatGreat ProductsProducts !!!!7
The Key Link in the ChainTransistor-to-TransistorCkt Blk to Ckt BlkOpportunityOpportunityInnovative,Innovative, efficient,efficient,highhigh performance,performance, lowlowcostcost packagespackages areare aasignificantsignificant ckagePackageto-BoardBoard-to-System8
Example – EnablingCustom solutionsSiliconSilicon nt9
Breaking Barriers to1 BillionMoore’s LawTransistorsK1,000,000Pentium 4 Processor100,000Pentium II Processor10,000Pentium Processor1,000Pentium III ProcessorPentium Pro Processori486 Processori386 �95’00’05’10’15Source: IntelIntegratedIntegrated PackagingPackaging SiliconSilicon TechnologyTechnologydevelopmentdevelopment isis essentialessential10
Challenge # 1Silicon to packageinterconnect11
Number of flip chip bumpsApproaching 10K flipchip bumps on a dieFlip Chip TMPentium III FamilyFamilyFuturePentium 4 generationsFamilyDriverDriver –– increasedincreased siliconsiliconfunctionalityfunctionality12
Solution : Aggressive BumpPitch Scaling to keep downSolderdie sizeBumpsKey Challenges :HumanHairStrand Plating bumps Chip Attach Process Underfill Joint integrity HVM scalable process13
Which leads us to Challenge # 2Within packageInterconnect14
Solution : High DensityInterconnectVery highescaperoutingdensityfrom thediePackageTracesDriverDriver :: NeedNeed highhigh wiringwiringdensitydensityLines narrowerthan hairHuman Hair15
Dimensional Stack-UpLine in Silicon130 nm(100X magnification)Line in Package25 um(100X magnification)Line in Motherboard5 mils (0.005”)(100X magnification)16
# of micro-vias in packageApproaching 40K microvias inside a packageMicro-vias40KChip AttachPads0Pentium III FamilyPentium 4 FamilyItaniumTMFamilyPackage X -sectionFuturegenerationsDriverDriver –– HighHigh I/OI/O countcount && powerpowersupplysupply17
Solution : Advancedlithography (new term in packaging !)WireC/A padsKey Challenges : Developing HDI (highdensity interconnect) atLOW COST High VolumeManufacturing CapableViaBuild-UpdielectricCore18
Core frequency trend doubling every 2 years100,00010,0001,000Frequency(MHz)10048610 808510.1’70P6Pentium proc3868086 286808080084004’80’90’00’10Source : Intel Architecture LabsIn addition 19
Max Mega transfers / secondFSB frequency rampcontinues40066Pentium IIProcessor133Pentium III Pentium 4ProcessorProcessorFuture Generation ProcessorsMicroprocessor Generation20
Solution : High PerformanceInterconnect TechnologyBenefits of organic1. Copper – Low resistance2. Low dielectric constant3. CheaperKey Challenge :High Performance SiliconCopper Interconnects? Optimize the entire substratearchitecture (materialproperties, layer stack-up,via placement, powerbussing etc.)Organic Packaging21
Solution : Better designsA poor design canruin processorperformanceKey Challenges :?Signal TimingInnovative routing – layoutOptimizing power / ground distributionCo-design of the complete silicon ? package interconnect22
Switching gears frominterconnect to Challenge # 3Power Management23
Power Increasing, silicongetting smallerPower(Watts)Pentium processors1002868086808580801048638680081 40040.1’71’74’78’85’92’00’04Source : Intel Architecture Labs’08Two Challenges Getting power in & getting heat out24
Importance of a quiet PowerSupplyHighLowIdeal stateHighLowReality – noiseORHighLowORThis is what Voltage Scaling can do25
Need lots of charge, veryquickly Increasing distance from supplyHot WaterHeaterInefficientdesignStill Waiting !!CloseProximityto supply26
Solution : Optimize designfor power deliveryKey Challenge:lpkg (pH)Cpkg (uF)CpkgLpkg0.18 umGenerationprocessors130 X improvement incapacitance andinductance needed /generation?Need to optimize thecomplete silicon ?package integratedpower deliverysolution27
Solution : Reduce systemdesign burden – heat removalTemp – Silicon(Tj)Temp – PackageCase (T c)Temp – Ambient(Ta)Temperature GradientPackagingProvide Solutionsfor this interfaceof the budgetOEMProvide Solutionsfor this interfaceof the budgetIntegratedIntegrated ThermalThermal SolutionsSolutions inin thethepackagepackage reducereduce heatheat fluxflux –– easiereasier toto coolcool ininthethe systemsystem28
Example :Integrated HighConductivity HeatSpreader Pentium4High conductivityThermal InterfaceMaterial29
Example : ItaniumSchematic ofof howhow aa typicaltypical heatheat pipepipe worksworksSchematicWick StructureWater VaporHeater BlockIntegrated heat pipetechnology interfacingdirectly to thesiliconCooler SectionOf Heat PipeEvaporationVapor CondensesCooler SectionOf Heat PipeHeat SourceCondensed water flows backthrough the wick structure bycapillary action30
And finally Challenge # 4Adding morefunctionality31
Solution : High Densityinterconnect moreintegrationHigh DensityInterconnect enablesa large cachememory integrationin a small spaceLeveraging packaging insteadof adding onto silicon32
Solution : Massiveintegration more featuresOn CPU VoltageregulationRASM33
In Summary 34
We talked about futureComplexity and Challengesto support Moore’s Law1. Silicon to package interconnect2. Within package interconnect3. Power management4. Adding more functionalityIntel’s Packaging StrategyInnovative TechnologyMaking Technology AffordableSmart designsIntegrated silicon packaging solutions35
For more information, please visit tmhttp://developer.intel.com/technology/itj/Search for packaging articles36
Approaching 10K flip chip bumps on a die Package Silicon Flip Chip (C4) interconnect Number of flip chip bumps Underfill Pentium III Family Pentium 4 Family ItaniumTM Family Future generations 10K 0
