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DATA SHEETwww.onsemi.comBluetooth) 5.2System-in-Package (SiP)RSL10 SIPSIP51 8x6CASE 127EYIntroductionRSL10 System In Package (RSL10 SIP) is a complete solutionthat provides the easiest way to integrate the industry’s lowest powerBluetooth Low Energy technology into a wireless application.The RSL10 SIP features an on board antenna, RSL10 radio SoC,and all necessary passive components in one package to help minimizeoverall system size. Already fully qualified to FCC, CE, and otherregulatory standards; RSL10 SIP removes the need for additionalantenna design considerations or RF certifications.Key Features Fully Certified:Bluetooth 5.2QDID Declaration ID FCC, CE, IC, MIC, KCCIndustry’s Lowest Power: Peak Rx Current 5.6 mA (1.25 V VBAT) Peak Rx Current 3.0 mA (3 V VBAT) Peak Tx Current (0 dBm) 8.9 mA (1.25 V VBAT) Peak Tx Current (0 dBm) 4.6 mA (3 V VBAT)Deep Sleep Current Consumption (1.25 V VBAT): Deep Sleep, IO Wake up: 50 nA Deep Sleep, 8 kB RAM Retention: 300 nACurrent Consumption (3 V VBAT): Deep Sleep, IO Wake up: 25 nA Deep Sleep, 8 kB RAM Retention: 100 nAEEMBC ULPMark Core Profile (3 V): 1090EEMBC ULPMark Core Profile (2.1 V): 1360Advanced Wireless: Bluetooth 5.2 Certified with LE 2 Mbit PHY (High Speed),as well as Backwards Compatibility and Support for EarlierBluetooth Low Energy Specifications Supports FOTA (Firmware Over The Air) Updates Rx Sensitivity (Bluetooth Low Energy Mode, 1 Mbps): 93 dB Transmitting Power: 17 to 6 dBm Range up to 100 Meters XXXXXAWLYWW(SIP51)XXXXXXAWLYWWG or G Specific Device Code Assembly Location Wafer Lot Year Work Week Pb Free PackageORDERING INFORMATIONDevicePackageShipping†NCH RSL10 101S51 ACGSIP51(Pb Free)2500 /Tape & Reel†For information on tape and reel specifications,including part orientation and tape sizes, pleaserefer to our Tape and Reel Packaging SpecificationBrochure, BRD8011/D.Other Key Features Arm Cortex M3 Processor Clocked at up to 48 MHzSupply Voltage Range: 1.1 3.3 V384 kB of Flash Memory76 kB of Program Memory88 kB of Data Memory Semiconductor Components Industries, LLC, 2018January, 2022 Rev. 41Publication Order Number:RSL10SIP/D
RSL10 SIPFEATURES Arm Cortex M3 Processor: A 32 bit core for real time Highly Configurable Interfaces: I2C, UART, two SPI applications, specifically developed to enablehigh performance low cost platforms for a broad rangeof low power applications.LPDSP32: A 32 bit Dual Harvard DSP core thatefficiently supports intensive signal processingapplications. Various codecs are available to customersthrough libraries that are included in RSL10’sdevelopment tools.Radio Frequency Front End: Based on a 2.4 GHz RFtransceiver, the RFFE implements the physical layer ofthe Bluetooth Low Energy technology standard and otherproprietary or custom protocols.Protocol Baseband Hardware: Bluetooth 5.2 certifiedand includes support for a 2 Mbps RF link and customprotocol options. The RSL10 baseband stack issupplemented by support structures that enableimplementation of onsemi and customer designedcustom protocols.Highly Integrated SoC: The dual core architecture iscomplemented by high efficiency power managementunits, oscillators, flash and RAM memories, a DMAcontroller, along with a full complement of peripheralsand interfaces.Deep Sleep Mode: RSL10 can be put into a Deep SleepMode when no operations are required. Various DeepSleep Mode configurations are available, including: “IO wake up” configuration. The power consumptionin deep sleep mode is 50 nA (1.25 V VBAT). Embedded 32 kHz oscillator running with interruptsfrom timer or external pin. The total current drain is90 nA (1.25 V VBAT). As above with 8 kB RAM data retention. The totalcurrent drain is 300 nA (1.25 V VBAT). The DC DC converter can be used in buck mode orLDO mode during Sleep Mode, depending on VBATvoltage.Standby Mode: Can be used to reduce the average powerconsumption for off duty cycle operation, rangingtypically from a few ms to a few hundreds of ms. Thetypical chip power consumption is 30 mA in StandbyMode.Multi Protocol Support: Using the flexibility providedby LPDSP32, the Arm Cortex M3 processor, and the RFfront end; proprietary protocols and other customprotocols are supported.Flexible Supply Voltage: RSL10 integrates high efficiency power regulators and has a VBAT range of 1.1to 3.3 V. interfaces, PCM interface, multiple GPIOs. It alsosupports a digital microphone interface (DMIC) and anoutput driver (OD).Flexible Clocking Scheme: RSL10 must be clockedfrom the XTAL/PLL of the radio front end at 48 MHzwhen transmitting or receiving RF traffic. When RSL10is not transmitting/receiving RF traffic, it can run off the48 MHz XTAL, the internal RC oscillators, the 32 kHzoscillator, or an external clock. A low frequency RTCclock at 32 kHz can also be used in Deep Sleep Mode. Itcan be sourced from either the internal XTAL, the RCoscillator, or a digital input pad.Diverse Memory Architecture: 76 kB of SRAMprogram memory (4 kB of which is PROM containing thechip boot up program, and is thus unavailable to the user)and 88 kB of SRAM data memory are available. A totalof 384 kB of flash is available to store the Bluetooth stackand other applications.The Arm Cortex M3 processor can execute from SRAMand/or flash.Security: AES128 encryption hardware block for customsecure algorithms and code protection with authenticateddebug port access (JTAG ‘lock’)Ultra Low Power Consumption ApplicationExamples: Low Duty Cycle Advertising: IDD 1.1 mA foradvertising at all three channels at 5 second intervals@ VBAT 3 V, DCDC converter enabled.RoHS Compliant Devicewww.onsemi.com2
RSL10 SIPNoticeinside the SiP. If an external antenna is used instead of theantenna internal to the SiP, this external antenna needs to beconnected to PIN E1.Additionally, an external PCB connection is required forthe VDDO pad to ensure that it is not left floating. Forexample, it can be connected to VBAT so that the logic highlevel for the digital I/O (DIO) pads is equal to VBAT.Figures 1 and 2 show proposed layout patterns for theRSL10 SIP. The specific layout pattern used in theapplication may have to be adjusted to meet certain needs ofthe PCB manufacturer or assembly house. PCB design filesfor the RSL10 SIP are available at www.onsemi.com.All specifications for the RSL10 System in Package arebased on the RSL10 radio SoC. The RSL10 SIP data sheetonly contains key parameters. For a full list of RSL10parameters and specifications, refer to the RSL10 data sheet.Application Board ConnectionThe RSL10 SIP is designed to be reflowed onto low costprinted circuit boards. The RSL10 SIP connects to theapplication board via solder pads located on the bottom.To properly operate the RSL10 SIP an external PCBconnection between the RF and ANT pads is required. Thisconnection connects the RF pin on RSL10 to the antennaNotes:1. Align component edge to PCB edge if possible.2. Extend keepout area to PCB edge.3. Keepout area All layers.4. Keepout area Top layer only.5. Units mm.Figure 1. RSL10 SIP Keepout Area Requirementswww.onsemi.com3
RSL10 SIPNotes:1. When incorporating internal antenna, join landing pads using 0.40 x 1.10 shape.2. Establish 50 W impedance to underlying reference plane.3. Maintain minimum 300 mm distance from ground plane.4. Area for several vias.5. Refer to radiation efficiency data for applicable ground plane sizing.6. Units mm.Figure 2. Minimum Top Layer Ground Structurewww.onsemi.com4
RSL10 SIPRSL10 SiP SchematicThe schematic for the RSL10 SIP is shown in Figure 3.Figure 3. RSL10 SIP SchematicFigure 4. Pin Connection Diagramwww.onsemi.com5
RSL10 SIPPAD FUNCTION DESCRIPTIONFor detailed pad function information see the RSL10 data sheet.Table 1. PAD LISTPad IdentifierPad NameI/OA/DPullA1JTMSI/ODUA2DOI12I/ODU/DDigital input output 12A3JTCKI/ODUCM3 JTAG Test ClockA4DOI10I/ODU/DDigital input output 10A5DOI6I/ODU/DDigital input output 6A6DOI3I/OA/DU/DDigital input output 3 / ADC 3A7DOI2I/OA/DU/DDigital input output 2 / ADC 2A8DOI5I/ODU/DDigital input output 5B1DOI13I/ODU/DDigital input output/CM3 JTAG Test ResetB2DOI14I/ODU/DDigital input output/CM3 JTAG Test Data InB3DOI11I/ODU/DDigital input output 11B5DOI8I/ODU/DDigital input output 8B6DOI1I/OA/DU/DDigital input output 1 / ADC 1B7DOI7I/ODU/DDigital input output 7B8DOI4I/ODU/DDigital input output 4C1DOI15I/ODU/DDigital input output/CM3 JTAG Test Data OutC2DOI9I/ODU/DDigital input output 9C7DOI0I/OA/DU/DDigital input output 0 / ADC 0C8EXT tal O/I voltage supplyD8VBATIPBattery input voltageE1RFI/OARF signal og test 7RESIDF8WAKEUPIAWake up pin for power m6DescriptionCM3 JTAG Test Mode StateExternal clock inputReset pinRESERVED
RSL10 SIPTable 1. PAD LIST (continued)Pad IdentifierPad dTable 2. ABSOLUTE MAXIMUM RATINGSSymbolParameterMinMaxUnitVBATPower supply voltage3.63VVDDOI/O supply voltage (Note 1)3.63VVSSRFRF front end ground 0.3VVSSAAnalog ground 0.3VVSSDDigital core and I/O groundVinT storage 0.3Voltage at any input pinStorage temperature rangeVVSSD 0.3VDDO 0.3(Up to a maximum of 3.63 V)V 4085 CCaution: Class 2 ESD Sensitivity, JESD22 A114 B (2000 V)The QFN package meets 450 V CDM levelStresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionalityshould not be assumed, damage may occur and reliability may be affected.1. VDDO voltage must not be applied before VBAT voltage on cold start.Table 3. RECOMMENDED OPERATING CONDITIONSDescriptionSupply voltage operating rangeFunctional temperature rangeSymbolConditionsMinTypMaxUnitVBATInput supply voltage on VBAT pin (Note 2)1.181.253.3V 40 85 CT functionalFunctional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyondthe Recommended Operating Ranges limits may affect device reliability.2. In order to be able to use a VBAT Min of 1.1 V, the following reduced operating conditions should be observed: Maximum Tx power 0 dBm. SYSCLK 24 MHz. Functional temperature range limited to 0 50 deg CThe following trimming parameters should be used: VCC 1.10 V VDDC 0.92 V VDDM 1.05 V, will be limited by VCC at end of battery life VDDRF 1.05 V, will be limited by VCC at end of battery life. VDDPA should be disabledRSL10 should enter in end of battery life operating mode if VCC falls below 1.03 V. VCC will remain above 1.03 V if VBAT 1.10 V underthe restricted operating conditions described above.www.onsemi.com7
RSL10 SIPTable 4. ELECTRICAL PERFORMANCE SPECIFICATIONSUnless otherwise noted, the specifications mentioned in the table below are valid at 25 C for VBAT VDDO 1.25 V in LDO mode, orVBAT VDDO 3 V in DC DC (buck) LLCurrent consumption RX,VBAT 1.25 V, low latencyIVBAT1.8mACurrent consumption TX,VBAT 1.25 V, low latencyIVBAT1.8mACurrent consumption RX,VBAT 1.25 VIVBAT1.15mADeep sleep current,example 1, VBAT 1.25 VIds1Wake up from wake up pin or DIOwake up.50nADeep sleep current,example 2, VBAT 1.25 VIds2Embedded 32 kHz oscillator runningwith interrupts from timer or external pin.90nADeep sleep current,example 3, VBAT 1.25 VIds3As Ids2 but with 8 kB RAM dataretention.300nAStandby Mode current,VBAT 1.25 VIstbDigital blocks and memories are notclocked and are powered at a reducedvoltage.30mACurrent consumption RX,VBAT 3 VIVBAT0.9mACurrent consumption TX,VBAT 3 VIVBAT0.9mADeep sleep current,example 1, VBAT 3 VIds1Wake up from wake up pin or DIOwake up.25nADeep sleep current,example 2, VBAT 3 VIds2Embedded 32 kHz oscillator runningwith interrupts from timer or external pin.40nADeep sleep current,example 3, VBAT 3 VIds3As Ids2 but with 8 kB RAM dataretention.100nAStandby Mode current,VBAT 3 VIstbDigital blocks and memories are notclocked and are powered at a reducedvoltage.17mAULPMark CP 3.0 VArm Cortex M3 processor running fromRAM, VBAT 3.0 V, IAR C/C Compiler for ARM 8.20.1.141831090ULPMarkULPMark CP 2.1 VArm Cortex M3 processor running fromRAM, VBAT 2.1 V, IAR C/C Compiler for ARM 8.20.1.141831260ULPMarkEEMBC ULPMark BENCHMARK, CORE PROFILEEEMBC CoreMark BENCHMARK for the Arm Cortex M3 Processor and the LPDSP32 DSPArm Cortex M3 processorrunning from RAMAt 48 MHz SYSCLK. Using the IAR8.10.1 C compiler, certified159CoreMarkLPDSP32 running from RAMAt 48 MHz SYSCLKUsing the 2020.03 release ofthe Synopsys LPDSP32 C compiler174CoreMarkArm Cortex M3 processor andLPDSP32 running from RAM,VBAT 1.25 VAt 48 MHz SYSCLK123CoreMark/mAArm Cortex M3 processor andLPDSP32 running from RAM,VBAT 3 VAt 48 MHz SYSCLK293CoreMark/mAArm Cortex M3 processorrunning CoreMark from RAM,VBAT 1.25 VAt 48 MHz SYSCLK(processor consumption only)29.1mA/MHzwww.onsemi.com8
RSL10 SIPTable 4. ELECTRICAL PERFORMANCE SPECIFICATIONS (continued)Unless otherwise noted, the specifications mentioned in the table below are valid at 25 C for VBAT VDDO 1.25 V in LDO mode, orVBAT VDDO 3 V in DC DC (buck) mode.DescriptionSymbolConditionsMinTypMaxUnitEEMBC CoreMark BENCHMARK for the Arm Cortex M3 Processor and the LPDSP32 DSPArm Cortex M3 processorrunning CoreMark from RAM,VBAT 3 VAt 48 MHz SYSCLK(processor consumption only)12.3mA/MHzArm Cortex M3 processorrunning CoreMark from Flash,VBAT 1.25 VAt 48 MHz SYSCLK(processor consumption only)34.3mA/MHzArm Cortex M3 processorrunning CoreMark from Flash,VBAT 3 VAt 48 MHz SYSCLK(processor consumption only)14.6mA/MHzLPDSP32 running CoreMarkfrom RAM, VBAT 1.25 VAt 48 MHz SYSCLK(processor consumption only)19.5mA/MHzLPDSP32 running CoreMarkfrom RAM, VBAT 3 VAt 48 MHz SYSCLK(processor consumption only)8.2mA/MHzINTERNALLY GENERATED VDDC: Digital Block Supply VoltageSupply voltage: operating rangeVDDC0.92Supply voltage: trimming rangeVDDCRANGE0.75Supply voltage: trimming stepVDDCSTEP1.151.32(Note 3)V1.38V10mVINTERNALLY GENERATED VDDM: Memories Supply VoltageSupply voltage: operating rangeVDDM1.05Supply voltage: trimming rangeVDDMRANGE0.75Supply voltage: trimming stepVDDMSTEP1.151.32(Note 4)1.3810VVmVINTERNALLY GENERATED VDDRF: Radio Front end supply voltageSupply voltage: operating rangeVDDRF1.00Supply voltage: trimming rangeVDDRFRANGE0.75Supply voltage: trimming stepVDDRFSTEP1.101.32 (Notes5 and 6)V1.38V10mVVDDO PAD SUPPLY VOLTAGE: Digital Level High VoltageDigital I/O supplyVDDO1.11.253.3V1.43.3V1.13.3V1.32VINDUCTIVE BUCK DC DC CONVERTERVBAT range when the DC DCconverter is active (Note 7)IN RANGEVBAT range when the LDO isactiveIN RANGEOutput voltage: trimming rangeDCDCLDODCDC1.11.2OUT RANGESupply voltage: trimming stepDCDCSTEP10mVPOWER ON RESETPOR voltageVBATPOR0.40.81.0VRADIO FRONT END: General SpecificationsRF input impedanceData rate FSK / MSK / GFSKZinRFSKSingle ended50OQPSK as MSK62.5Data rate 4 FSKOn air data 2000kbps
RSL10 SIPTable 4. ELECTRICAL PERFORMANCE SPECIFICATIONS (continued)Unless otherwise noted, the specifications mentioned in the table below are valid at 25 C for VBAT VDDO 1.25 V in LDO mode, orVBAT VDDO 3 V in DC DC (buck) mode.DescriptionSymbolConditionsMinTypMaxUnitRADIO FRONT END: Crystal and Clock SpecificationsXtal frequencyFXTALFundamental48Settling time0.5MHz1.5msRADIO FRONT END: Synthesizer SpecificationsFrequency range2500MHzRX frequency stepFRFSupported carrier frequenciesRX Mode frequency synthesizerresolution2360100HzTX frequency stepTX Mode frequency synthesizerresolution600HzPLL Settling time, RXtPLL RXRX Mode1525msPLL Settling time, TXtPLL TXTX mode, BLE modulation510msRADIO FRONT END: Receive Mode SpecificationsCurrent consumption at 1 Mbps,VBAT 1.25 VIBATRFRXVDDRF 1.1 V, 100% duty cycle5.6mACurrent consumption at 2 Mbps,VBAT 1.25 VIBATRFRXVDDRF 1.1 V, 100% duty cycle6.2mACurrent consumption at 1 Mbps,VBAT 3 V, DC DCIBATRFRXVDDRF 1.1 V, 100% duty cycle3.0mACurrent consumption at 2 Mbps,VBAT 3 V, DC DCIBATRFRXVDDRF 1.1 V, 100% duty cycle3.4mARX Sensitivity, 0.25 Mbps0.1% BER (Notes 8, 9) 96dBmRX Sensitivity, 0.5 Mbps0.1% BER (Notes 8, 9) 95dBmRX Sensitivity, 1 Mbps, BLE0.1% BER (Notes 8, 9) Single endedmatch to 50 W 93dBmRX Sensitivity, 2 Mbps, BLE0.1% BER (Notes 8, 9) 91dBmRSSI effective rangeWithout AGC60dB2.4dB48dB6dB 10dBmTx power 0 dBm, VDDRF 1.07 V,VDDPA: off, LDO mode8.9mATx power 3 dBm, VDDRF 1.1 V,VDDPA: 1.26 V, LDO mode17.4mATx power 6 dBm, VDDRF 1.1 V,VDDPA: 1.60 V, LDO mode25mATx power 0 dBm, VDDRF 1.07 V,VDDPA: off, DC DC mode4.6mATx power 3 dBm, VDDRF 1.1 V,VDDPA 1.26 V, DC DC mode8.6mATx power 6 dBm, VDDRF 1.1 V,VDDPA 1.60 V, DC DC mode12mARSSI step sizeRX AGC rangeRX AGC step sizeProgrammableMax usable signal level0.1% BERRADIO FRONT END: Transmit Mode SpecificationsTx peak power consumption atVBAT 1.25 V (Note 10)Tx peak power consumption atVBAT 3 V (Note 10)IBATRFTXIBATRFTXTransmit power rangeBLETransmit power step sizeFull band 17 6(Note 12)1www.onsemi.com10dBmdB
RSL10 SIPTable 4. ELECTRICAL PERFORMANCE SPECIFICATIONS (continued)Unless otherwise noted, the specifications mentioned in the table below are valid at 25 C for VBAT VDDO 1.25 V in LDO mode, orVBAT VDDO 3 V in DC DC (buck) mode.DescriptionSymbolConditionsMinTx power 0 dBm. Full band. Relative tothe typical value. 1.5TypMaxUnit1.5dBRADIO FRONT END: Transmit Mode SpecificationsPower in 2nd harmonic0 dBm mode. 50 W for “Typ” value.(Note 11) 62dBmPower in 3rd harmonic0 dBm mode. 50 W for “Typ” value.(Note 11) 70dBmPower in 4th harmonic0 dBm mode. 50 W for “Typ” value.(Note 11) 82dBmADCResolutionInput voltage rangeINLDNLChannel sampling frequencyADCRES814bitsADCRANGE02VADCINL 2 2mVADCDNLADCCH SFFor the 8 channels sequentially,SLOWCLK 1 MHz12 1 1mV0.01956.25kHz50kHz32 kHz ON CHIP RC OSCILLATORUntrimmed FrequencyTrimming stepsFreqUNTR20Steps321.5%3 MHz ON CHIP RC OSCILLATORUntrimmed FrequencyFreqUNTR235MHzTrimming stepsSteps1.5%Hi Speed modeFhi10MHz32768Hz32 kHz ON CHIP CRYSTAL OSCILLATOROutput FrequencyFreq32kDepends on xtal parametersStartup time1Internal load trimming rangeSteps of 0.4 pFDuty Cycle040503s25.2pF60%DC INPUT CHARACTERISTICS OF THE DIGITAL PADS With VDDO 2.97 V – 3.3 V, nominal: 3.0 V LogicVoltage level for high inputVIH2VDDO 0.3VVoltage level for low inputVILVSSD 0.30.8VDC INPUT CHARACTERISTICS OF THE DIGITAL PADS With VDDO 1.1 V – 1.32 V, nominal: 1.2 V LogicVoltage level for high inputVIH0.65 *VDDOVDDO 0.3VVoltage level for low inputVILVSSD 0.30.35 *VDDOVDC OUTPUT CHARACTERISTICS OF THE DIGITAL PADSVoltage level for high outputVOHIOH 2 mA to 12 mAVDDO 0.4Voltage level for low outputVOLIOH 2 mA to 12 mA4V0.4V12mADIO DRIVE STRENGTHDIO drive strengthIDIO2www.onsemi.com1112
RSL10 SIPTable 4. ELECTRICAL PERFORMANCE SPECIFICATIONS (continued)Unless otherwise noted, the specifications mentioned in the table below are valid at 25 C for VBAT VDDO 1.25 V in LDO mode, orVBAT VDDO 3 V in DC DC (buck) mode.DescriptionSymbolConditionsMinTypMaxUnitFLASH SPECIFICATIONSEndurance of the 384 kB of flash10000write/erasecyclesEndurance for sections NVR1,NVR2, and NVR3 (6 kB in total)1000write/erasecycles25yearsRetentionProduct parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Productperformance may not be indicated by the Electrical Characteristics if operated under different conditions.3. The maximum VDDC voltage cannot exceed the VBAT input voltage or the VCC output from the buck converter.4. The maximum VDDM voltage cannot exceed the VBAT input voltage or the VCC output from the buck converter.5. The maximum VDDRF voltage cannot exceed the VBAT input voltage or the VCC output from the buck converter.6. The VDDRF calibrated target is 1.07 V (TX power 0 dBm).7. The LDO can be used to regulate down from VBAT and generate VCC. For VBAT values higher than 1.5 V, the LDO is less efficient and itis possible to save power by activating the DC DC converter to generate VCC.8. Signal generated by RF tester.9. Single ended match to 50 ohms, measured at pin E1 including loss of integrated Tx harmonic filter.10. All values are based on evaluation board performance, including the harmonic filter loss.11. The values shown here are including integrated RF filter.12. For optimal performance, charge pump frequency of 125 kHz should be avoided when VDDPA supply is enabled.Table 5. VDDM TARGET TRIMMING VOLTAGE IN FUNCTION OF VDDO VOLTAGENOTE:VDDM Voltage (V)DIO PAD CFG DRIVEMaximum VDDO Voltage (V)1.0512.71.0503.21.1003.3These are trimming targets at room/ATE temperature 25X30 C.Table 6. VDDC TARGET TRIMMING VOLTAGE IN FUNCTION OF SYSCLK FREQUENCYNOTE:VDDC Voltage (V)Maximum SYSCLK Frequency (MHz)Restriction0.92 24The ADC will be functional in low frequencymode and between 0 and 85 C only.1.00 24Fully functional1.0548Fully functionalThese are trimming targets at room/ATE temperature 25X30 C.www.onsemi.com12
RSL10 SIPANTENNA SPECIFICATIONSThe antenna performance of the RSL10 SIP depends on the size of the ground plane on which it is mounted. Figure 5 showsan overview of different ground plane sizes with expected antenna return losses shown in Figure 6.123450 x 60mm40 x 60mm30 x 60mm25 x 60mm5Figure 5. PCB ground planes. 1) 50x60, 2) 40x60, 3) 30x60, 4) 25x60, 5) 12.5x60. All sizes in .000.0012345Figure 6. Antenna Efficiency vs. PCB Sizewww.onsemi.com13625 x 25mm 12.4 x 60mm6
RSL10 SIPFigure 7. Radiation Pattern for 50 x 60 mm PCB Ground PlaneFigure 8. Radiation Pattern for 40 x 60 mm PCB Ground PlaneFigure 9. Radiation Pattern for 30 x 60 mm PCB Ground Planewww.onsemi.com14
RSL10 SIPFigure 10. Radiation Pattern for 25 x 60 mm PCB Ground PlaneFigure 11. Radiation Pattern for 25 x 25 mm PCB Ground PlaneFigure 12. Radiation Pattern for 12.5 x 60 mm PCB Ground PlaneENVIRONMENTAL SPECIFICATIONSElectrostatic Discharge (ESD) Sensitive DeviceCAUTION: ESD sensitive device. Permanent damage may occur on devices subjected to high energy electrostaticdischarges.Proper ESD precautions in handling, packaging and testing are recommended to avoid performance degradation or loss offunctionality.Solder InformationThe RSL10 SIP is constructed with all RoHS compliant material and should be reflowed accordingly. This device is MoistureSensitive Class MSL3 and must be stored and handled accordingly. Re flow according to IPC/JEDEC standard J STD 020C,Joint Industry Standard: Re flow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. Handsoldering is not recommended for this part.For more information, see SOLDERRM/D available from www.onsemi.com.www.onsemi.com15
RSL10 SIPREGULATORY INFORMATIONFCC Regulatory and User InformationFCC ID: 2APD9 RSL10SIPThis device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:(1) this device may not cause harmful interference, and (2) this device must accept any interference received, includinginterference that may cause undesired operation.Any changes or modifications not expressly approved by onsemi could void the user’s authority to operate the equipment.Module Usage ConditionsManufacturers of products incorporating the RSL10SIP Bluetooth 5.2 Module are authorized to use the FCC Grant of theRSL10SIP module for their own products according to the conditions referenced in the grant.A product containing the RSL10SIP module shall bear a label referring to the enclosed module. The label shall use wordingsuch as: “Contains FCC ID:2APD9 RSL10SIP”The label of the host device shall also contain the following statement. When this is not possible, the information shall beincluded in the User Manual of the host device:“This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:(1) this device may not cause harmful interference, and (2) this device must accept any interference received, includinginterference that may cause undesired operation.Any changes or modifications not expressly approved by onsemi could void the user’s authority to operate the equipment.”WARNING: RF Exposure ComplianceIn order to comply with FCC RF exposure requirements this device must be installed to provide a separation distance of 5 mmor greater between this device and the user.ISED Regulatory and User InformationISED ID 23763 RSL10SIPHVIN RSL10SIPThis device contains licence exempt transmitter(s)/receiver(s) that comply with Innovation, Science and EconomicDevelopment Canada’s licence exempt RSS(s). Operation is subject to the following two conditions:(1) This device may not cause interference.(2) This device must accept any interference, including interference that may cause undesired operation of the device.L’émetteur/récepteur exempt de licence contenu dans le présent appareil est conforme aux CNR d’Innovation, Sciences etDéveloppement économique Canada applicables aux appareils radio exempts de licence. L’exploitation est autorisée aux deuxconditions suivantes: (1) L’appareil ne doit pas produire de brouillage; (2) L’appareil doit accepter tout brouillageradioélectrique subi, même si le brouillage est susceptible d’en compromettre le fonctionnement.Module Usage ConditionsA product containing the RSL10SIP module shall bear a label referring to the enclosed module. The label shall use wordingsuch as: “Contains IC: 23763 RSL10SIP”The label of the host device shall also contain the following statement. When this is not possible, the information shall beincluded in the User Manual of the host device:“This device contains licence exempt transmitter(s)/receiver(s) that comply with Innovation, Science and EconomicDevelopment Canada’s licence exempt RSS(s). Operation is subject to the following two conditions:(1) This device may not cause interference.(2) This device must accept any interference, including interference that may cause undesired operation of the device.”The transmitter module may not be co located with any other transmitter or antenna.Un produit contenant le module RSL10SIP devra porter une étiquette du dispositif qui fait référence au module inclus.L’étiquette du dispositif devra utiliser un libellé tel que: “Contient IC: 23763 RSL10SIP”L’étiquette du dispositif devra également inclure la déclaration ci dessous. Si cela n’est pas possible, cette information devraêtre précisée dans le manuel de l’utilisateur:L’émetteur/récepteur exempt de licence contenu dans le présent appareil est conforme aux CNR d’Innovation, Sciences etDéveloppement économique Canada applicables aux appareils radio exempts de licence. L’exploitation est autorisée aux deuxconditions suivantes: (1) L’appareil ne doit pas produire de brouillage; (2) L’appareil doit accepter tout brouillageradioélectrique subi, même si le brouillage est susceptible d’en compromettre le fonctionnement.Le module émetteur peut ne pas être coïmplanté avec un autre émetteur ou antenne.www.onsemi.com16
RSL10 SIPWARNING: RF Exposure ComplianceIn order to comply with ISED RF exposure requirements this device must be installed to provide a separation distance of 7 mmor greater between this device and the user.Afin de se conformer aux exigences d’exposition ISDE RF, cet appareil doit être installé pour fournir une distance de séparationde 7 mm ou plus entre cet appareil et l’utilisateur.Korean Regulatory and User Information특정 출 ( 터통템 )제 조 자 (제조자): onsemi제조( 지): 캐 제 품 (제품): NCH RSL10 101S51 ACG ( ): RSL10SIP제조 ( 자): 중 장치 전화, Wi Fi 투 장치 ! 통 장치" # %접한 장 &' ( 할 ) *작 -킬 ./0 123 .해5 67 전파혼 ./0 1-89 ; 전 ?@ '7 할 A BC.The following ID information needs to be added to the product package (application and user documentation).Korean KC Mark and Identifier as shown below. Height of KC mark is 5mm minimum. Colour preference is Navy (5PB 2/8color according to KS A 0062). Acceptable other colours are black, gold and silver. Other colours may only be used if preferredcolours are not legible for the mark. The conformity assessment certification number is to be near the KC mark. (usually below).R-CRM-oNs-RSL10SIPEuropean Regulatory and User InformationThis device complies with the essential requirements of the Radio Equipment Directive 2014/53/EU. The following IDinformation needs to be added to the product package (application and user documentation).Japanese Regulatory and User InformationThe following ID information needs to be added to the product package (application and user documentation).ID (209 J00320) and must be combined with the Giteki (MIC) Mark as specified below.www.onsemi.com17
RSL10 SIPDevelopment ToolsExport Control Classification Number (ECCN)RSL10 is supported by a full suite of comprehensive toolsincluding: An easy to use development board Software Development Kit (SDK) including an OxygenEclipse based development environment, Bluetoothprotocol stacks, sample code, libraries, anddocumentationThe ECCN designation for RSL10 is 5A991.g.Company or Product InquiriesFor more information about onsemi products or servicesvisit our Web site at www.onsemi.com.For sales or technical support, contact your localrepresentative or authorized distributor.Bluetooth is a registered trademark of Bluetooth SIG.Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries).www.onsemi.com18
MECHANICAL CASE OUTLINEPACKAGE DIMENSIONSSIP51 8x6CASE 127EYISSUE BDATE 30 JUN 2020GENERICMARKING DIAGRAM*XXXXXXXXXXXXXXXX
RSL10 SIP www.onsemi.com 3 Notice All specifications for the RSL10 System in Package are based on the RSL10 radio SoC. The RSL10 SIP data sheet only contains key parameters. For a full list of RSL10 parameters and specifications, refer to the RSL10 data sheet. Application Board Connection The RSL10 SIP is designed to be reflowed onto low cost
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