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Freescale Semiconductor, Inc.Electrical and Thermal CharacteristicsFigure 3 shows the undershoot and overshoot voltage for the MPC107 memory interface.4VVIHGVDD 5%GVDDGNDGND – 0.3 VVILFreescale Semiconductor, Inc.GND – 1.0 VNot to Exceed 10%of tSDRAM CLKFigure 3. Overshoot/Undershoot VoltageFigure 4 and Figure 5 show the undershoot/overshoot voltage of the PCI interface for 3.3- and 5-V signals,respectively.11 ns(Min) 7.1 V7.1 V p-to-p(Min)OvervoltageWaveform4 ns(Max)0V4 ns(Max)62.5 ns 3.6 V7.1 V p-to-p(Min)UndervoltageWaveform–3.5 VFigure 4. Maximum AC Waveforms for 3.3-V Signaling8MPC107 PCI Bridge/Memory Controller Hardware SpecificationsFor More Information On This Product,Go to: www.freescale.comMOTOROLA

Freescale Semiconductor, Inc.Electrical and Thermal Characteristics11 ns(Min) 7.1 V7.1 V p-to-p(Min)OvervoltageWaveform0V4 ns(Max)4 ns(Max)62.5 ns 3.6 VFreescale Semiconductor, Inc.UndervoltageWaveform7.1 V p-to-p(Min)–3.5 VFigure 5. Maximum AC Waveforms for 5-V Signaling1.4.1.3DC Electrical SpecificationsTable 3 provides the DC electrical characteristics for the MPC107.Table 3. DC Electrical SpecificationsAt recommended operating conditions (See Table 2)Conditions 1CharacteristicsSymbolMinMaxUnitNotes2, 3Input high voltagePCI onlyVIH0.65 OVDDLVDDVInput low voltagePCI onlyVIL—0.3 OVDDVInput high voltageAll other pins (GVDD 3.3 V)VIH2.0—V2All other pins (BVDD 2.5 V)VIH1.7—V2All inputs exceptPCI SYNC INVILGND0.8VPCI SYNC IN input highvoltageCVIH2.4—VPCI SYNC IN input lowvoltageCVILGND0.4VIL— 70µA4IL— 10µA4Input low voltageInput leakage current for0.5 V Vin 2.7 Vpins using DRV PCI driver @ LVDD 4.75 VInput leakage current allothersLVDD 3.6 V (GVDD 3.465 V)Output high voltageIOH driver dependent(GVDD 3.3 V)VOH2.4—V5Output low voltageIOL driver dependent(GVDD 3.3 V)VOL—0.4V5MOTOROLAMPC107 PCI Bridge/Memory Controller Hardware SpecificationsFor More Information On This Product,Go to: www.freescale.com9

Freescale Semiconductor, Inc.Electrical and Thermal CharacteristicsTable 3. DC Electrical Specifications (continued)At recommended operating conditions (See Table 2)CharacteristicsOutput high voltageFreescale Semiconductor, Inc.Output low voltageCapacitanceConditions 1SymbolMinMaxUnitNotesIOH driver dependent(BVDD 2.5 V)All outputs exceptCPU CLK[0:2]VOH1.85—V5IOH driver dependent(BVDD 2.5 V)CPU CLK[0:2] onlyVOH2.0—V5IOL driver dependent(BVDD 2.5 V)All outputs exceptCPU CLK[0:2]VOL—0.4V5IOL driver dependent(BVDD 2.5 V)CPU CLK[0:2] onlyVOL—0.3V5Vin 0 V, f 1 MHzCin—7.0pF6Notes:1. These specifications are for the default driver strengths indicated in Table 4.2. See Figure 17 for pins with internal pull-up resistors.3. The minimum input high voltage is not compliant with the PCI Local Bus Specification (Rev 2.1), which specifies0.5 OVDD for minimum input high voltage.4. Leakage current is measured on input and output pins in the high-impedance state. The leakage current ismeasured for nominal OVDD/LVDD and VDD or both OVDD/LVDD and VDD must vary in the same direction.5. See Table 4 for the typical drive capability of a specific signal pin based on the type of output driver associatedwith that pin as listed in Table 17.6. Capacitance is periodically sampled rather than 100% tested.10MPC107 PCI Bridge/Memory Controller Hardware SpecificationsFor More Information On This Product,Go to: www.freescale.comMOTOROLA

Freescale Semiconductor, Inc.Electrical and Thermal Characteristics1.4.1.4Output Driver CharacteristicsTable 4 provides information on the characteristics of the output drivers referenced in Table 17. The valuesare from the MPC107 IBIS model (v1.1) and are not tested. For additional detailed information, see thecomplete IBIS model listing at http://www.motorola.com/semiconductors.Table 4. Drive Capability of MPC107 Output PinsProgrammableOutput Impedance(Ω)SupplyVoltageIOHIOLUnitNotes20BVDD 3.3 V36.618.1mA2, 5BVDD 2.5 V21.415.6mA3, 6, 7BVDD 3.3 V18.69.2mA2, 5BVDD 2.5 V10.87.9mA3, 6, 725OVDD 3.3 V12.012.4mA1, 450 (default)OVDD 3.3 V6.16.3mA1, 48 (default)GVDD 3.3 V89.042.3mA2, 513.3GVDD 3.3 V55.826.4mA2, 5DRV MEM CLK20GVDD 3.3 V36.618.1mA2, 5DRV PCI CLK40GVDD 3.3 V18.69.2mA2, 520 (default)GVDD 3.3 V36.618.1mA2, 540GVDD 3.3 V18.69.2mA2, 5Driver TypeDRV CPUFreescale Semiconductor, Inc.40 (default)DRV PCIDRV CPU CLKDRV MEM CTRLDRV MEM DATANotes:1. For DRV PCI, IOH read from the IBIS listing in the pull-up mode, I(Min) column, at the 0.33-V label by interpolatingbetween the 0.3- and 0.4-V table entries’ current values which corresponds to the PCI VOH 2.97 0.9 OVDD(OVDD 3.3 V), where table entry voltage OVDD – PCI VOH.2. For all others with GVDD or BVDD 3.3 V, IOH read from the IBIS listing in the pull-up mode, I(Min) column, at the0.9-V table entry which corresponds to the VOH 2.4 V, where table entry voltage G/BVDD – VOH.3. For all others with BVDD 2.5 V, IOH read from the IBIS listing in the pull-up mode, I(Min) column, at the 0.65-Vtable entry by interpolating between the 0.6- and 0.7-V table entries’ current values which corresponds to theVOH 1.85 V, where table entry voltage BVDD – VOH.4. For DRV PCI, IOL read from the IBIS listing in the pull-down mode, I(Min) column, at 0.33 V PCI VOL 0.1 OVDD (OVDD 3.3 V) by interpolating between the 0.3-and 0.4-V table entries.5. For all others with GVDD or BVDD 3.3 V, IOL read from the IBIS listing in the pull-down mode, I(Min) column, atthe 0.4-V table entry.6. For all others with BVDD 2.5 V, IOL read from the IBIS listing in the pull-down mode, I(Min) column, at the 0.4-Vtable entry.7. For BVDD 2.5 V, the IOH and IOL values are estimated from the io mem data XX 2.5 andio mem addr XX 2.5 sections of the IBIS model, where XX driver output impedance (20 or 40 Ω).MOTOROLAMPC107 PCI Bridge/Memory Controller Hardware SpecificationsFor More Information On This Product,Go to: www.freescale.com11

Freescale Semiconductor, Inc.Electrical and Thermal Characteristics1.4.1.5Power CharacteristicsTable 5 provides the preliminary power consumption estimates for the MPC107. Power consumption on thePLL supply pin (AVDD) and the DLL supply pin (LAVDD) 15 mW. This information is based oncharacterization data.Table 5. Power ConsumptionPCI SYNC IN/Core Frequency (MHz)25/50Freescale Semiconductor, Inc.Mode33/3333/6666/100UnitNotes1122mW1, 2915mW1, 6697118636235800350Nap13974493693185420276970mW1, 2Sleep7971845677102841138939mW1, 2Notes:1. Power is measured with VDD 2.625 V, GVDD OVDD BVDD 3.45 V at 0 C and one DIMM populated in testsystem.2. All clock drivers enabled.1.4.1.6Thermal CharacteristicsTable 6 provides the package thermal characteristics for the MPC107. Refer to Section 1.7, “System DesignInformation,” for more details about thermal management.Table 6. FC-PBGA Package Thermal unction-to-ambient natural convection(Single-layer board—1s)RθJA30 C/W1, 2Junction-to-ambient natural convection(Four-layer board—2s2p)RθJMA26 C/W1, 3Junction-to-ambient (@200 ft/min)(Single-layer board—1s)RθJMA25 C/W1, 3Junction-to-ambient (@200 ft/min)(Four-layer board—2s2p)RθJMA22 C/W1, 3Junction-to-boardRθJB20 C/W4Junction-to-caseRθJC 0.1 C/W5Notes:1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)temperature, ambient temperature, airflow, power dissipation of other components on the board, and boardthermal resistance.2. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.3. Per JEDEC JESD51-6 with the board horizontal.4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature ismeasured on the top surface of the board near the package.5. Thermal resistance between the die and the case top surface without thermal grease.12MPC107 PCI Bridge/Memory Controller Hardware SpecificationsFor More Information On This Product,Go to: www.freescale.comMOTOROLA

Freescale Semiconductor, Inc.Electrical and Thermal Characteristics1.4.2AC Electrical CharacteristicsThis section provides the AC electrical characteristics for the MPC107. After fabrication, functional partsare sorted by maximum core frequency as shown in Table 7 and Section 1.4.2.1, “Clock AC Specifications,”and tested for conformance to the AC specifications for that frequency. The core frequency is determinedby the bus (PCI SYNC IN) clock frequency and the settings of the PLL CFG[0:3] signals. Parts are soldby maximum processor core frequency; see Section 1.9, “Ordering Information.”Table 7 provides the operating frequency information for the MPC107.Table 7. Operating Frequency 1At recommended operating conditions (See Table 2) with LVDD 3.3 V 0.3 V66 MHz100 MHzFreescale Semiconductor, Inc.Characteristic 2UnitMinMaxMinMax256625100Core (memory bus/processor bus) frequencyPCI input frequency (PCI SYNC IN)12.5–66MHzMHzNotes:1. See Section 1.9.2, “Part Numbers Not Fully Addressed by This Document,” for information on the 133-MHz partoffering.2. The PCI SYNC IN frequency and PLL CFG[0:3] settings must be chosen such that the resulting peripherallogic/memory bus frequency, CPU (core) frequency, and PLL (VCO) frequencies do not exceed their respectivemaximum or minimum operating frequencies. Refer to the PLL CFG[0:3] signal description in Section 1.6, “PLLConfiguration,” for valid PLL CFG[0:3] settings and PCI SYNC IN frequencies.1.4.2.1Clock AC SpecificationsTable 8 provides the clock AC timing specifications as defined in Section 1.4.2.2, “Input AC TimingSpecifications.” These specifications are for the default driver strengths indicated in Table 4.Table 8. Clock AC Timing SpecificationsAt recommended operating conditions (See Table 2) with LVDD 3.3 V 0.3 VNumCharacteristics and ConditionsMinMaxUnitNotes12.566MHz71aFrequency of operation (PCI SYNC IN)1bPCI SYNC IN cycle time8015ns72,3PCI SYNC IN rise and fall times—2.0ns14PCI SYNC IN duty cycle measured at 1.4 V4060%5aPCI SYNC IN pulse width high measured at 1.4 V69ns25bPCI SYNC IN pulse width low measured at 1.4 V69ns27PCI SYNC IN jitter— 150ps9aPCI CLK[0:4] skew (pin-to-pin)—500ps9bSDRAM CLK[0:3] skew (pin-to-pin)—350ps9cCPU CLK[0:2] skew (pin-to-pin)—350ps9dSDRAM CLK[0:3]/CPU CLK[0:2] jitter—150ps10Internal PLL relock time—100µsMOTOROLAMPC107 PCI Bridge/Memory Controller Hardware SpecificationsFor More Information On This Product,Go to: www.freescale.com2, 3, 513

Freescale Semiconductor, Inc.Electrical and Thermal CharacteristicsTable 8. Clock AC Timing Specifications (continued)At recommended operating conditions (See Table 2) with LVDD 3.3 V 0.3 VFreescale Semiconductor, Inc.NumCharacteristics and ConditionsMinMaxUnitNotes15DLL lock range with DLL STANDARD 1 (default)See Figure 8ns616DLL lock range with DLL STANDARD 0See Figure 9ns617Frequency of operation (OSC IN)1812.566MHz7OSC IN cycle time8015ns719OSC IN rise and fall times—5ns420OSC IN duty cycle measured at 1.4 V4060%21OSC IN frequency stability—100ppmNotes:1. Rise and fall times for the PCI SYNC IN input are measured from 0.4 to 2.4 V.2. Specification value at maximum frequency of operation.3. Relock time is guaranteed by design and characterization. Relock time is not tested.4. Rise and fall times for the OSC IN input are guaranteed by design and characterization. OSC IN input rise andfall times are not tested.5. Relock timing is guaranteed by design. PLL-relock time is the maximum amount of time required for PLL lock aftera stable VDD and PCI SYNC IN are reached during the reset sequence. This specification also applies when thePLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be heldasserted for a minimum of 255 bus clocks after the PLL-relock time during the reset sequence.6. DLL STANDARD is bit 7 of the PMC2 register 72 . N is a non-zero integer (1 or 2). Tclk is the period of oneSDRAM SYNC OUT clock cycle in ns. tloop is the propagation delay of the DLL synchronization feedback loop(PC board runner) from SDRAM SYNC OUT to SDRAM SYNC IN in ns; 6.25 inches of loop length (unloadedPC board runner) corresponds to approximately 1 ns of delay. See Figure 8 and Figure 9 for DLL locking ranges.7. See Table 18 for PCI SYNC IN input frequency range for specific PLL CFG[0:3] settings.14MPC107 PCI Bridge/Memory Controller Hardware SpecificationsFor More Information On This Product,Go to: www.freescale.comMOTOROLA

Freescale Semiconductor, Inc.Electrical and Thermal CharacteristicsFigure 6 shows PCI SYNC IN input clock timing, Figure 7 illustrates how the clock specifications inTable 8 relate to the MPC107 clocking. Figure 8 and Figure 9 shows the DLL locking range loop delay.15a5b23CVIHPCI SYNC INVMVMVMCVILVM Midpoint Voltage (1.4 V)Freescale Semiconductor, Inc.Figure 6. PCI SYNC IN Input Clock Timing DiagramMPC107CPU CLK[0:2]Specs. 15,16DLLSpec. 10PLLSpecs. 9c, 9dSDRAM CLK[0:3]Specs. 9b, 9dSDRAM SYNC OUTSDRAM SYNC INsys logic clkPCI SYNC INSpecs. 1–7PCI SYNC OUTOSC INSpecs. 17–23Spec. 9aCore LogicPCI CLK[0:4]Note: Specification numbers are from Table 8.Figure 7. Clock Subsystem Block DiagramMOTOROLAMPC107 PCI Bridge/Memory Controller Hardware SpecificationsFor More Information On This Product,Go to: www.freescale.com15

Freescale Semiconductor, Inc.Electrical and Thermal CharacteristicsFreescale Semiconductor, Inc.Tclk SDRAM SYNC OUT Period (ns)5045Tclk 1.8 Tloop 27.9 ns403530Tclk 2.2 Tloop 11.88 ns25Tclk 0.6 Tloop 9.27 ns201510Tclk 0.7 Tloop 3.96 ns50051015Tloop Propagation Delay Time (ns)Figure 8. DLL Locking Range Loop Delay (DLL STANDARD 0)Tclk SDRAM SYNC OUT Period (ns)504540353025Tclk 0.9 Tloop 13.95 ns20Tclk 1.1 Tloop 5.94 nsTclk 0.45 Tloop 6.98 ns15105Tclk 0.55 Tloop 2.97 ns0051015Tloop Propagation Delay Time (ns)Figure 9. DLL Locking Range Loop Delay (DLL STANDARD 1)16MPC107 PCI Bridge/Memory Controller Hardware SpecificationsFor More Information On This Product,Go to: www.freescale.comMOTOROLA

Freescale Semiconductor, Inc.Electrical and Thermal Characteristics1.4.2.2Input AC Timing SpecificationsTable 9 provides the input AC timing specifications. See Figure 10 and Figure 11.Table 9. Input AC Timing SpecificationsAt recommended operating conditions (see Table 2) with LVDD 3.3 V 0.3 VFreescale Semiconductor, Inc.NumCharacteristicMinMaxUnitNotes10aPCI input signals valid to PCI SYNC IN (input setup)3.0—ns2, 310bMemory interface signals valid to SDRAM SYNC IN (input setup)2.0—ns1, 310cPIC, misc. debug input signals valid to SDRAM SYNC IN (input setup)2.0—ns1, 310dI2C input signals valid to SDRAM SYNC IN (input setup)2.0—ns1, 310eMode select inputs valid to HRESET (input setup)9 tCLK—ns3, 4, 510f60x processor interface signals valid to SDRAM SYNC IN(input setup)2.0—ns1, 311a1 PCI SYNC IN (SDRAM SYNC IN) to inputs invalid (input hold)1.0—ns2, 311a2 Memory interface signals SDRAM SYNC IN to inputs invalid(input hold)0.5—ns1, 30—ns1, 30—ns1, 3, 511a3 60x processor interface signals SDRAM SYNC IN to inputs invalid(input hold)11bHRESET to mode select inputs invalid (input hold)Notes:1. All memory, processor, and related interface input signal specifications are measured from the TTL level (0.8 or2.0 V) of the signal in question to the VM 1.4 V of the rising edge of the memory bus clock, SDRAM SYNC IN.SDRAM SYNC IN is the same as PCI SYNC IN in 1:1 mode, but is twice the frequency in 2:1 mode(processor/memory bus clock rising edges occur on every rising and falling edge of PCI SYNC IN). SeeFigure 10.2. All PCI signals are measured from OVDD/2 of the rising edge of PCI SYNC IN to 0.4 OVDD of the signal inquestion for 3.3-V PCI signaling levels. See Figure 11.3. Input timings are measured at the pin.4. tCLK is the time of one SDRAM SYNC IN clock cycle.5. All mode select input signal specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in questionto the VM 1.4 V of the rising edge of the HRESET signal. See Figure 12.MOTOROLAMPC107 PCI Bridge/Memory Controller Hardware SpecificationsFor More Information On This Product,Go to: www.freescale.com17

Freescale Semiconductor, Inc.Electrical and Thermal CharacteristicsFigure 10 shows input-output timing referenced to SDRAM SYNC IN and Figure 11 the input-outputtiming referenced to PCI SYNC IN.PCI SYNC INSDRAM SYNC IN(Shown in 2:1 Mode)VMVMVM10b-dFreescale Semiconductor, Inc.13b12b-d11a2.0 V2.0 V0.8 V0.8 V14bMemoryInputs/OutputsInput TimingVM Midpoint Voltage (1.4 V)Output TimingFigure 10. Input-Output Timing Diagram Referenced to SDRAM SYNC INOVDD 2PCI SYNC INOVDD 2OVDD 210a13a12a11aPCIInputs/Outputs14a0.615 OVDD0.4 OVDD0.285 OVDDOutput TimingInput TimingFigure 11. Input-Output Timing Diagram Referenced to PCI SYNC INFigure 12 shows input timing for mode select signals.VMHRESET10e11bMode Pins2.0 V0.8 VVM Midpoint Voltage (1.4 V)Figure 12. Input Timing Diagram for Mode Select Signals18MPC107 PCI Bridge/Memory Controller Hardware SpecificationsFor More Information On This Product,Go to: www.freescale.comMOTOROLA

Freescale Semiconductor, Inc.Electrical and Thermal Characteristics1.4.2.3Output AC Timing SpecificationTable 10 provides the processor bus AC timing specifications for the MPC107. See Figure 10 and Figure 11.Table 10. Output AC Timing SpecificationsAt recommended operating conditions (see Table 2) with LVDD 3.3 V 0.3 VCharacteristic 3, 6NumMinMaxUnitNotesPCI SYNC IN to output valid, 66 MHz PCI, with SDMA4pulled-down to logic 0 state (see Figure 11)—6.0ns2, 4PCI SYNC IN to output valid, 33 MHz PCI, with SDMA4 in thedefault logic 1 state (see Figure 11)—11.0ns2, 412bMemory interface signals, SDRAM SYNC IN to output valid—5.5ns112b1Memory interface signal, CKE (100-MHz device),SDRAM SYNC IN to output valid—5.5ns112b2Memory interface signal, CKE (66-MHz device), SDRAM SYNC INto output

network routers and switches, mass storage subsystems, network appliances, and print and . — PCI 2.1-compliant — PCI 5.0-V tolerance — Support for PCI locked accesses to memory — Support for accesses to PCI memory, I/O, and configuration spaces — Selectable big- or little-endian operation