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Databook.fxp 1/13/99 2:09 PM Page 1SemiconductorDatabookRevised January, 2000InterFET Corporation1000 N. Shiloh Road, Garland, TX 75042(972) 487-1287 FAX (972) 276-3375www.interfet.com
Databook.fxp 1/13/99 2:09 PM Page ii01/99Semiconductor DatabookVolume 4, Number 6Table of ContentsAbout InterFETTerms & ConditionsOptional Hi-Rel Process FlowsAbout InterFET ScientificIFPA300/301 Series Ð JFET ICInterFET Scientific R&DSection ASelection Guide by ApplicationSection BJFET Data SheetsSection CDiode, Regulator & VCR Data SheetsSection DJapanese Equivalent Data SheetsSection ESmall Outline Plastic Package Device DataSection FGeometry & Process Characterization DataSection GPackage InformationSection HApplication Noteswww.interfet.com1000 N. Shiloh Road, Garland, TX 75042(972) 487-1287 FAX (972) 276-3375
Databook.fxp 1/13/99 2:09 PM Page iiii01/99InterFET was founded in 1982 to design and manufacture FieldEffect Transistors. Having only one product has a way of focusingoneÕs attention. ÒGood enoughÓ isnÕt good enough. ÒCloseÓ isnÕtclose at all. That focus has worked for us. Every year we have grown,and every year we have improved our plant, our engineering, ourprocesses, our quality, and our services. We are still focused on FieldEffect Transistors and related devices.InterFET is big enough to competitively supply over 400 standardJFET types. Small enough to craft JFETs to your exact specifications.Big enough to supply national and international leading-edge electronicmanufacturers and laboratories. Small enough for you to talk directlywith the people that engineer and manufacture the product.Every business has a culture, a way of doing business. Ours isÉHow we serve each customer is more important than how manycustomers we serve.1000 N. Shiloh Road, Garland, TX 75042(972) 487-1287 FAX (972) 276-3375www.interfet.com
Databook.fxp 1/13/99 2:09 PM Page iiiiii01/99Minimum Orders 250 per line item (standard product).Cancellation orReschedulingStandard product (databook) orders may be cancelled or rescheduledprior to 30 days of ship date without penalty. No cancellation orrescheduling will be accepted within 30 days of scheduled ship date.Terms & ConditionsNet 30 days on approved credit.Freight ChargesPrepaid and added to the invoice unless otherwise specified.ShippingF.O.B. Garland, Texas, via any carrier you wish, including UPS andFederal Express.SpecificationsInterFET device types are based on JEDEC or EIA registered data orInterFET datasheet specifications. Customer source-control drawingswill be assigned special part numbers proprietary to the customer.Many combinations of selected electrical, process flow, and packageconfigurations may be sourced from standard InterFET products.InterFET Corporation makes no warranty regarding information furnished and reserves the rightto make changes to standard products at any time and without notice. InterFET Corporationdoes not assume any liability arising from the application or use of InterFET data or products.InterFET Corporation does not participate in life support system designs, nor knowingly sellproducts for life-support equipment. InterFET Corporation reserves the right to make changesin any product specifications any time without notice.We have diligently checked and cross-checked the data in this book to coincide with publishedcharts and drawings. Abbreviations have been updated and obvious errors corrected. When therewere conflicts, logic was the prime guide, followed by experience. Printing and typography wasaccommodated in the interest of readability.We suggest that, when ordering from InterFET, you also advise us of your specifications. Often,there are alternative solutions. If so, we want you to know the choices. And that, surely, is toyour advantage.www.interfet.com1000 N. Shiloh Road, Garland, TX 75042(972) 487-1287 FAX (972) 276-3375
Databook.fxp 1/13/99 2:09 PM Page iviv01/99High-Reliability Process FlowsInterFET Corporation has served the military and industrial highreliability junction field effect transistor market since 1984. Thereare standard high-reliability processing options available on mostpackaged and die products and are typically less costly than productssupplied to source control drawing requirements.Option-1 process flow provides most of the 100% screening steps fora MIL-STD-883, Method 5008 Class B die product.Option-2 process flow provides most of the 100% screening steps fora JANTXV type device as defined by MIL-S-19500 requirements.Option-3 process flow provides many of the 100% screening stepsfor a JANS type device as defined by MIL-S-19500 requirements.Should Option-1, Option-2, or Option-3 process flows not meetyour requirements, InterFET Corporation can provide processingbased on your source control drawings and detail specifications. AllMIL-S-19500/MIL-STD-750 requirements through JANS-level typeprocessing can be provided. Manufacturing baseline control can beoffered as an option.We have earned a reputation in the industry for manufacturingHigh-Reliability products for a wide range of military and industrialusers and would be pleased to work with you.1000 N. Shiloh Road, Garland, TX 75042(972) 487-1287 FAX (972) 276-3375www.interfet.com
Databook.fxp 1/13/99 2:09 PM Page vv01/99Option 1 Process Flow Evaluationfor High-Reliability Un-Encapsulated JFET DieScreenMILÐSTDMethodPre–Cap Visual750-2072Condition100% @ 100X minimumPer InterFET PB-IN-GN04SealPer InterFET PB-CW-MC01Initial ElectricalPer InterFET PB-TS-EL00Temperature Cycle750-1051Final ElectricalWire Bond EvaluationQuality Conformancewww.interfet.comCondition D, 20 cycles, –65 to 200 C,15 minutes at extremes, minimumPer InterFET PB-FT-0000883-2011Per InterFET QB-IN-GN041000 N. Shiloh Road, Garland, TX 75042(972) 487-1287 FAX (972) 276-3375
Databook.fxp 1/13/99 2:09 PM Page vivi01/99Option 2 Process Flowfor High-Reliability Metal Case JFETsScreenMILÐSTDMethodPre–Cap Visual750-2072Condition100% @ 100X minumumPer InterFET PB-IN-GN04SealPer InterFET PB-CW-MC01Initial ElectricalPer InterFET PB-TS-EL00Stabilization Bake750-1031200 C for 24 hoursTemperature Cycle750-1051Condition D, 20 cycles,–65 to 200 C, 15 minutesat extremes, minimumConstant Acceleration750-2006Y1 axis only, 20,000gFine Leak750-1071Condition G or H,5E–8 atm/cc–sec maximumGross Leak750-1071Condition CPre–HTRB ElectricalHTRB–ConditioningPer InterFET PB-TS-EL01750-1039Condition A, 150 Cfor 168 hours, minimumPost–HTRB End Point ElectricalPer InterFET PB-FT-0000within 24 hoursFinal ElectricalPer InterFET PB-FT-0000Optional if all customer required electricalparameters are included in Post-HTRBTestQuality ConformancePer InterFET QB-IN-GN041000 N. Shiloh Road, Garland, TX 75042(972) 487-1287 FAX (972) 276-3375www.interfet.com
Databook.fxp 1/13/99 2:09 PM Page viivii01/99Option 3 Process Flowfor Class S High-Reliability Metal Case JFETsScreenMILÐSTDMethodPre–Cap Visual750-2072Condition100% @ 100X minimumPer InterFET PB-IN-GN04SealPer InterFET PB-CW-MC01Initial ElectricalPer InterFET PB-TS-EL00Stabilization Bake750-1031200 C for 24 hoursTemperature Cycle750-1051Condition D, 20 cycles, -65 to 200 C,15 minutes at extremes, minimumConstant Acceleration750-2006Y1 axis only, 20,000gPIND883-2020Condition AFine Leak750-1071Condition G or H, 5E–8 atm/cc–sec, maxGross Leak750-1071Condition CPre–HTRB ElectricalHTRB–ConditioningPer InterFET PB-TS-EL01750-1039Post–HTRB End Point ElectricalCondition A, 150 Cfor 168 hours, minimumPer InterFET PB-FT-0000within 24 hoursRadiography750-2076External Visual750-2071X1 & Y1 DirectionsFinal ElectricalPer InterFET PB-FT-0000Optional if all customer required electricalparameters are included in Post-HTRB TestQuality ConformancePer InterFET QB-IN-GN04www.interfet.com1000 N. Shiloh Road, Garland, TX 75042(972) 487-1287 FAX (972) 276-3375
Databook.fxp 1/13/99 2:09 PM Page viiiviii01/99InterFET ScientificInterFET Scientific has been created to address the specializedneeds of scientists, engineers and designers.We are told that there are few other JFET manufacturers with ourresearch data bank and our willingness to work in the scientific areas.To some, JFETs are a commodity. To InterFET, JFETs are an emerging technologyÑready to contribute to the applications of today andtomorrow.We would be pleased to discuss your specific project or to send youan overview of our capabilities.1000 N. Shiloh Road, Garland, TX 75042(972) 487-1287 FAX (972) 276-3375www.interfet.com
Databook.fxp 1/13/99 2:09 PM Page ixix01/99InterFET ScientificJFET and IC ResearchInterFET and InterFET Scientific haveparticipated in government laboratoryprojects at Brookhaven National Laboratory,Lawrence Berkeley Laboratories, INFN(Italian Nuclear Physics Institute) and others.plus grants from DOE/SBIR and the TexasAdvanced Research Program.InterFET Scientific has substantial experiencepartnering research and development withscientific and commercial customers that needvery low noise, radiation tolerance, cryogenicoperation or other special requirements.New Process JFETIntegrated Circuit TechnologyJFET ICs are very specialized products, capableof meeting performance needs that no other ICtechnology can satisfy. Applications demandingextremely low-noise charge or signal amplification, or needing high tolerance to radiation orESD are well suited to this new technology.InterFET is capable of delivering a turnkeyproduct, or, if you provide CAD layout,InterFET will work with you by providing thefoundry work.Custom Discrete JFET Designs Discrete JFETs with high gain (gm) andhigh gm/Cin ratio using tetrode (or dualgate) designs to allow minimum capacitanceon the input gate. High performance discrete JFET designs toincrease radiation tolerance using very smalland tight design rules. Unusual discrete JFET designs, such as verylarge, high voltage, or other special designconsiderations.InterFET Scientific has developed this customintegrated circuit capability using exclusivelyn-channel JFET active components and onboard MOS capacitors and diffused resistors.This process uses P-well isolation and thesame epitaxially formed channels which providediscrete JFETs their excellent low-noise andradiation-tolerant characteristics. Overallperformance of sensitive preamplifier andamplifier applications is improved overhybrids using discrete JFETs due to reductionof chip and wire parasitics.www.interfet.com1000 N. Shiloh Road, Garland, TX 75042(972) 487-1287 FAX (972) 276-3375
Databook.fxp 1/13/99 2:09 PM Page xx01/99IFPA300, IFPA301Monolithic JFET PreamplifierAbsolute maximum ratings at TA 25 CDescription & FeaturesThe IFPA300 series is an inverting transimpedanceamplifier featuring extremely low noise and a widegain-bandwidth suitable as a charge-sensitive preamplifier for a broad range of applications.All pins (except Input) referenced to Bias 3The monolithic IFPA300 series contain 8 n-channelepitaxial-channel diffused-gate JFETs to achieveoptimally low 1/f noise performance over a widetemperature range (120K-300K).Operating TemperatureDC open loop gainThe 300/301 Series gives more flexibility with respectto output transistor drain.85 dBGBW200 MHzēN @ 10 HzInput to Bias 3ØVPower Dissipation225 mWDerating Factor1.8 mW/ C150 CAt this time, there are two units in this family.3.0 nV/ HzThe 310/311 Series ties the output transistor drain tothe VDD line. 100 mWSimplified Schematic CircuitGeneral SpecificationsPower Dissipation at VDD 12 VInput Leakage Current (T 300 K)10 pAInput-Referred Noise Voltage (f 10 kHz)0.6 nV/ HzInput-Referred Noise Voltage (f 10 Hz)3.0 nV/ HzOutput Range at VDD 12 V85 dBVDDJ44.0 V (5.0 V Max)J7Designed to drive 50Ω load.SubstrateJ3Charge SensitivePreamplifier SpecificationsThe IFPA300 Series is actually tailored to detectorcapacitance in the 100 Ð 1000 pF range.Input Open-Loop Capacitance60 pFRise Time (CD 500 pF, Cf 33 pF)20 nsEquivalent Noise Charge(Measured with semigaussian shaping, peakingtime tp)J8Bias 1J2OpenDrainOutputJ6OpenSourceOutputBias 2InputJ1Bias 3J5VSS4200 e– rms at CD @ 500 pF, tp 0.2 µm3200 e– rms at CD @ 500 pF, tp 1.0 µmPackages & Test Circuit Overside4200 e– rms at CD @ 500 pF, tp 4.0 µm1000 N. Shiloh Road, Garland, TX 75042(972) 487-1287 FAX (972) 276-3375www.interfet.com
Databook.fxp 1/13/99 2:09 PM Page xixi01/99IFPA300, IFPA301Monolithic JFET PreamplifierInput FET J1 selected to thefollowing elecrical parameters.ParameterConditionsMinBVGSSVds 0, Ig 1 µA– 25IGSSVds 0, Vgs – 10 VIDSSVds 0, Vgs 10 VVGS(OFF)Vds 0, Id 1 µAGMVgs 0, Vds 10 VVGSFId 1 µAMaxVDD 12 bstrateJ7120KJ3J8Bias 1J2VoltsJ6ParameterConditionsMinMaxUnitsVDCoutVdd 12 V, – VS – 6 VTest pt #1610VVinVdd 12 V, – VS – 6 VTest pt #2– 0.6– 1.6VVACoutVdd 12 V, – VS – 6 Vt O µsecVACoutVdd 12 V, – VS – 6 Vt 100 µsecInput20KJ1J5Bias 350mV20mVVSSTest Point #22MΩ10pFACInputTest Point #OpenSourceOutputBias 2Test Circuit ReferenceOpenDrainOutput1MΩ10KΩ10pF– Vsupply – 6 V0.165 (4.19)0.185 (4.70)0.335 (8.51)0.370 (9.40)0.305 (7.75)0.335 (8.51)0.010 (0.25)0.040 (1.02)8 Leads - Dia.0.016 (0.41)0.021 (0.53)0.029 (0.74)0.045 (1.14)0.200 (5.08)Basic568 7 6 5Top1 2 3 470.050 (1.27)445 0.010 (0.25)0.040 (1.02)83Standoff 0.110 (2.79)0.160 (4.06)0.500 (12.70)0.244 (6.20)0.158 (4.01) 0.228 (5.79)0.150 (3.81)0.028 (0.71)0.024 (0.61)10.022 (0.56)0.018 (0.0460.018 (0.460.014 (0.36)0.049 (1.24)0.059 (1.50)0.015 (0.37)Min.0.069 (1.75)0.053 (1.35)20.028 (0.71)Bottom View 0.034 (0.86)0.197 (5.00)0.188 (4.78)45 0.009 (0.23)0.007 (0.18)IFPA300 uses TO-99 PackageIFPA301 uses SOIC-8 PackageDimensions in Inches (mm)Dimensions in Inches (mm)Pin ConfigurationPin Configuration1 Bias 3, 2 VSS, 3 Bias 1, 4 VDD /Substrate5 Open Drain Output, 6 Open Source Output, 7 Bias 2, 8 Input1 Bias 2, 2 Input, 3 Bias 3, 4 VSS, 5 Bias 1, 6 VDD/Substrate7 Open Drain Output, 8 Open Source Outputwww.interfet.com1000 N. Shiloh Road, Garland, TX 75042(972) 48
Databook Revised January, 2000 InterFETCorporation 1000 N. Shiloh Road, Garland, TX 75042 (972) 487-1287 FAX(972) 276-3375 www.interfet.com Databook.fxp 1/13/99 2:09 PM Page 1 . Click on the vertical bar to the right of this box to proceed to the Tab le of Contents. The bar may also be underneath this box, depending on th e size of your monitor. Use the bookmarks at left to navigate anywher e .
