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Advanced PackagingEnabling the Post Moore EraEelco BergmanSr. Director, Business DevelopmentSeptember 12, 20191
Contents ASE Introduction Semiconductor Market Heterogeneous Integration Drivers Advanced Packaging Solutions Challenges & Opportunities Summary2
ASE at a GlanceEstablished 1984, production commenced at flagship factory in Kaohsiung, TaiwanAchieved global leadership in IC Assembly, Test & Materials (ATM) in 2003 & maintained#1 OSAT position sinceCompleted acquisition of Universal Scientific Industrial Co. (USI) to expand DMS/EMS/ODMmodule & system manufacturing capabilityCompleted acquisition of SPIL, Ltd. to expand IC assembly & test manufacturing capabilityOperating at 19 facilities worldwide, serving multiple markets, applications & geographies 90K employees: Global team comprises operations, engineering, R&D, sales & marketingASE Technology Holding overall revenue (pro forma) of 13.2B in 201833
ASE OrganizationASE TechnologyHolding, Co.Est. 2018ASESPILUSIIC Assembly, Test &MaterialsEst. 1984IC Assembly & TestDMS/EMS/ODMEst. 1984Est. 19762018 Revenue: 5.3B2018 Revenue: 2.9B2018 Revenue: 5.0B4
ASE in the Electronics Value ChainBridging OSAT and EMSSemiconductorDesign IDM Fabless OEMWafer FabricationPackaging & TestSiP ModulePCBA / System IDM Wafer Foundry IDM OSAT Wafer Foundry OSAT ODM DMS / EMS DMS / EMS ODM IDMASE Group ServiceEngineering TestBumpingAssemblyWafer SortComponent TestSubstrateModule DesignModule AssemblyModule TestComponent SourcingFAE SupportSystem DesignSystem AssemblySystem TestSoftware DevelopmentLogisticsProduct MarketingSales & Support5
Semiconductor Revenue vs. Process GenerationTechnology NodeRevenue US 10 um10000nm(10um)400 B3 um1 um1000nm(1 um)300 B0.35 um90 nm100nm200 B28 nm10nm100 B7 nm3 nm1 nm19701980199020002010202020306
Chip & System Integration10 umDIPSiP: Package IntegrationQFPTechnology Node3 um1 umBGA0.8 umFC BGA2.5D0.35 umSoC: Chip Integration19801990200028 nm20107 nm3 nm20202030HeterogeneousIntegrationComplexity197090 nmModule: System Integration7
Role and Value of Semiconductor Packaging IncreasingTechnology NodePackaging Revenue US 500 um250 umPCB/Substrate100 um50 X60 B50 um10 um10000nm(10um)10 um3 um50 B5 um40 B1 um1000nm(1 um)0.35 um90 nm100nm1600 XValue ofPackaging28 nm30 B20 B7 nm10nmCMOS3 nm10 B1 nm19701980199020002010202020308
Drivers for Heterogeneous Integration Moore’s law slowing Exponential rise in chip development costsChip Development Cost Decreasing number of leading edge fabs SoC scaling cost barriers Increasing cost per transistor on advanced node Increasing SoC die size – wafer yield/die cost impact SoC scaling technology barriers Integration challenges for logic, analog and memorySource: IBS Reduced availability of IP for advanced nodes Opportunity to leverage mature process nodes foranalog and other IP blocks Performance and cost optimized Design re-use / increased flexibility Faster time to market Virtual SoCSource: Intel9
Advanced Integration Solutions - Foundry WLSI – Wafer Level System Integration InFO (Integrated FanOut)InFO PoP (FO Pkg on Pkg)InFO AiP (FO with Antenna in Pkg)MUST (Multi-Stack)InFo oS (FO on Substrate)InFO MS (FO with Memory on Substrate)InFO UHD (FO Ultra High Density)CoWoS (Chip on Wafer on Substrate- 2.5D) ApplicationsMobile AP, RF FEM,Baseband, etc.High PerformanceMobile, Network,AI/HPC, etc.Source: WikiChip (Semicon, July 2019)10
Advanced Integration Solutions - IDM HPC Packaging Toolbox EMIB: Embedded interconnect bridgein organic substrate Foveros: Integration on TSV interposer Co-EMIB: Integration of multipleFoveros structures and memory/IPchiplets using EMIB ODI (Omni Directional Interconnect):Integration on reduced size interposerenabling direct vertical interconnect totop die for power deliverySource: Intel/EE Times (07.09.19)11
Die Level InterconnectsAdvanced Integration Solutions - OSAT Interconnection through post-fabRDL (FanOut) Line/space: 2um100,000’s10,000’s1,000’s Interconnection through organicsubstrate Line/space: 10um2.5DTSV Interconnection through siliconinterposer Line/space: 0.4umFanOutFOCoSPoP, SiPMCM25/2515/1510/105/52/21/10.5/0.5Line / Space (um)12
MCM Die partition or multi device integration on organic substrateHigh performance SoC and IP die (i.e. SERDES) integrationMulti fab/process node device combinationsLow to medium interconnect density: 100’s-1000’sSeparation of digital/analog blocksBenefits Enables IP reuse with advanced wafer node devicesReduced SoC design and validation timeEnable multiple sources for ‘standard’ IP blocks / devicesSmaller SoC die size – increased yield Lower bump/die stress – increased reliabilitySoC 16 chiplets60um die to die spacing min13
FanOut / FOCoS Homogeneous partition Yield & cost optimization Scalable integration Heterogenous die partition28nm Process and performance optimization16nmFan Out Compound Die Medium to high interconnect densityFan Out Hybrid BGA Package 1000’s to 10,000’s Separation of digital/analog/memory Benefits Die size, yield and cost optimizationProcess node / functionality optimizationShort, high density interconnectIncreased reliability2/2 µmLines/Spaces14
2.5D TSV Homogeneous partition Yield & cost optimization Scalable integration Heterogenous die integration SoC, HBM2 & SerDesHBM2 stackSoCHBM2 stack High interconnect density 10,000’s to 100,000 40um microbump pitch Benefits Silicon interconnect performanceHigh bandwidth interface enablementReduced powerSi on Si first level interconnectSystem board size reduction15
Challenges & Opportunities Supply chain Chiplet ecosystem enablement IP chiplet type/functionality development roadmap and prioritiesPin out/interface standards (by chiplet type/function) where possible (eg. JEDEC HMB ‘chiplet’ spec)KGD performance and reliability criteria definition Business model definition and development Who is selling what to whom? What are associated liability limitations? Design & Simulation Co-design flow definition and optimization Development of packaging PDK for various package integration solutions Import and integration capability of multi-device GDS into package design tool Chiplet representation for EDA – ODSA CDX (Chiplet Design Exchange) Multi-physics simulation tools for multi-device integration design validation SiP and virtual SoC system simulation DFT/Test Chiplet KGD testing standards & criteria Debug and final test of multi device SiP or virtual SoC Failure isolation and identification ATE vs. SLT16
SummaryConvergence ofDevice and SystemIntegrationDie DisaggregatonIntegration forPerformance & CostPoP / MCM / FOCoS / 2.5DSystem-in-Package (SiP)System OEM DrivenPCBA Miniaturization17
Thank Youw w w. a s e g l o b a l . c o m18
Advanced Packaging Enabling the Post Moore Era. 2 Contents ASE Introduction Semiconductor Market Heterogeneous Integration Drivers Advanced Packaging Solutions Challenges & Opportunities Summary. 3 ASE at a Glance Established 1984, production commenced at flagship factory in Kaohsiung, Taiwan Achieved global leadership in IC Assembly, Test & Materials (ATM) in 2003 .
