Transcription
Zynq-7000 SoCPackaging and PinoutProduct SpecificationUG865 (v1.9) July 28, 2021
Revision HistoryThe following table shows the revision history for this /20181.8RevisionIn Chapter 6: Updated the top-mark images and descriptions per XCN16014 andXCN19014.Editorial updates only. No technical content updates.In Chapter 1: Revised RSVDGND description in Table 1-5.In Chapter 2: Updated links in Table 2-1.In Chapter 4: In response to XCN16004: Forged to Stamped Lid Conversion forMonolithic FPGA Flip Chip Packages, added Figure 4-13: FFG900 (XC7Z035,XC7Z045, and XC7Z100) Flip-Chip BGA with Stamped Lid Package Specifications.6/14/20171.7Added the XC7Z007S, XC7Z012S, and XC7Z014S devices where applicable.In Chapter 5: Updated the packages and Peak Package Reflow Body Temperature.Other updates to the Support for Thermal Models, Applied Pressure from Heat Sinkto the Package via Thermal Interface Materials, and Conformal Coating sections.In Chapter 6: Updated Figure 6-1 to add the bar code marking and the Pb-freecharacter. Added the Pb-free Character description as outlined in XCN16022:Cross-ship of Lead-free Bump and Substrates in Lead-free (FFG/FBG/SBG) Packages.Revised the Bar Code section of Table 6-1 to include changes outlined in XCN16014:Top Marking change for 7 Series, UltraScale, and UltraScale Products.Updated the Legal Disclaimers on page 124.03/01/20161.6Updated to add RF1156 packages and RoHS compliant options (FFV packages)where applicable.In Table 1-5, updated the PS POR B and SRCC descriptions.Added the XC7Z035 in the FF/FFG/FFV900 package to Table 1-6.Updated many of the drawings in Chapter 4. Replaced the FF/FFG/FFV1156 packagemechanical drawing in Figure 4-15.Completely revised Chapter 5, Thermal Specifications with industry standardguidelines for all sections. Updated the Thermal Interface Material sectionpreviously in Appendix B, and added the Applied Pressure from Heat Sink to thePackage via Thermal Interface Materials.In Appendix B: Moved the Reasons for Thermal Interface Material section toChapter 5. Removed the Package Loading Specifications section.11/17/20141.5Added the XC7Z035 device throughout the specification. Added a discussion onULA materials on page 7. Added Note on page 28. Updated Figure 5-4: ThermalManagement Options for Flip-Chip BGA Packages. In Table 5-2 and Figure 5-7,revised the peak temperature (body) values and the ramp-up rate and ramp-downrate to 2 C/s. Updated the Peak Package Reflow Body Temperature values inTable 5-3 and added Note 1. Updated Soldering Guidelines section. Added PostReflow/Cleaning/Washing and Conformal Coating sections. Updated References.Zynq-7000 SoC Packaging GuideUG865 (v1.9) July 28, 2021www.xilinx.comSend Feedback2
DateVersion06/11/20141.4RevisionAdded the RF900 package for the XQ7Z045 to Table 1-1, Table 1-3, Table 1-4,Table 2-1, Table 3-1, Figure 3-45, Figure 3-46, Figure 3-47, Figure 3-48,Figure 4-18, and Table 5-1.Updated the XC7Z015 bank numbering (Figure 1-2).Added XA7Z030 to Table 1-3, Table 1-4, Table 2-1, Table 3-1, Figure 1-4,Figure 3-25, Figure 3-26, Figure 3-27, Figure 3-28, Figure 4-6, Figure 4-7, andTable 5-1.Updated the PUDC B and PS MIO VREF descriptions in Table 1-5. Added theGTP/GTX XY coordinates to Figure 1-2, Figure 1-4, Figure 1-5, and Figure 1-6.In Chapter 3, updated the memory groupings legend’s DCI pin descriptions.Added the Heat Sink Removal Procedure and Package Pressure Handling Capacitysections. For clarity, updated Figure 5-7 and Table 5-3 with specific deviceinformation.Added Chapter 7, Packing and Shipping.11/12/20131.3Added the CLG485, SBG485, and FFG1156 packages. Added the XC7Z015 andXC7Z100 devices. Added the XA Zynq-7000 SoC devices (XA7Z010 and XA7Z020).Added the Zynq-7000Q SoC devices (XQ7Z020, XQ7Z030, and XQ7Z045) and theRF484 and RF676 packages. Updated the Notice of Disclaimer.Clarified the maximum and available PS I/O pins as 128 in Table 1-1 and Table 1-4.In Table 1-5, updated the PUDC B description.Added Note 1 and updated the data in Table 5-1. Updated the Pb-Free ReflowSoldering in Chapter 5 discussion. Updated the MSL for flip-chip packages inTable 5-3.Removed the engineering sample notation from the top mark drawings inFigure 6-1.Updated Appendix A, Recommended PCB Design Rules.02/14/20131.2Updated VCCPLL in Table 1-5 and added Note 2.Updated Figure 3-8 and Figure 3-16.Revised Figure 4-1, increased the A and A2 maximum dimensions. UpdatedFigure 4-11. Added Figure 4-6, Figure 4-7. Figure 4-9, and Figure 4-12.In Table 5-1, updated thermal resistance data for the XC7Z010 and XC7Z020devices.Updated Appendix B, Heat Sink Guidelines for Lidless Flip-Chip Packages.09/24/20121.1Added the CLG225 throughout document.Clarified RSVDVCC[3:1] and PS MIO VREF in Table 1-5, page 12. Added Note 9 tothe DXN 0 description.Chapter 3: Updated the legends for the pinout diagrams.Chapter 4: Added mechanical drawings.05/08/20121.0Initial Xilinx release.Zynq-7000 SoC Packaging GuideUG865 (v1.9) July 28, 2021www.xilinx.comSend Feedback3
Table of ContentsRevision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Chapter 1: Package OverviewSummary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Device/Package Combinations and Maximum I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Pin Compatibility Between Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Die Level Bank Numbering Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Chapter 2: Zynq-7000 SoC Package FilesAbout ASCII Package Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26ASCII Pinout Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Chapter 3: Device DiagramsSummary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Zynq-7000 SoC Device Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Chapter 4: Mechanical DrawingsSummary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75CLG225 Wire-Bond Chip-Scale BGA(XC7Z007S, XC7Z010, and XA7Z010) (0.8 mm Pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77CLG400 (XC7Z007S, XC7Z010, XA7Z010, XC7Z014S, XC7Z020, and XA7Z020) and CL400 (XQ7Z020)Wire-Bond Chip-Scale BGA (0.8 mm Pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78CLG484 (XC7Z014S, XC7Z020, XA7Z020), CL484 (XQ7Z020) and CLG485 (XC7Z012S and XC7Z015)Wire-Bond Chip-Scale BGA (0.8 mm Pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79SBG485/SBV485 (XC7Z030) Flip-Chip Lidless BGA (0.8 mm Pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . 80FBG484/FBV484 (XC7Z030, XA7Z030, and XQ7Z030) Flip-Chip Lidless BGA (1.0 mm Pitch). . . . . . 82FBG676/FBV676 (XC7Z030, XC7Z035, and XC7Z045) Flip-Chip Lidless BGA (1.0 mm Pitch) . . . . . . 84FFG676/FFV676 (XC7Z030) Flip-Chip BGA(1.0 mm Pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87FFG676/FFV676 Flip-Chip BGA(XC7Z035 and XC7Z045)(1.0 mm Pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88Zynq-7000 SoC Packaging GuideUG865 (v1.9) July 28, 2021www.xilinx.comSend Feedback4
FFG900 (XC7Z035, XC7Z045, and XC7Z100)Flip-Chip BGA (1.0 mm Pitch) with Stamped Lid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .FFG900/FFV900 (XC7Z035, XC7Z045, and XC7Z100) Flip-Chip BGA (1.0 mm Pitch) . . . . . . . . . . . .FFG1156/FFV1156 (XC7Z100)Flip-Chip BGA (1.0 mm Pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .RB484 Ruggedized Flip-Chip BGA (XQ7Z030)(1.0 mm Pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .RF676 (XQ7Z030 and XQ7Z045) andRFG676 (XQ7Z045) Ruggedized Flip-Chip BGA(1.0 mm Pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .RF900 (XQ7Z045 and XQ7Z100)Ruggedized Flip-Chip BGA (1.0 mm Pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .RF1156 (XQ7Z100) Ruggedized Flip-Chip BGA(1.0 mm Pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89909192939495Chapter 5: Thermal SpecificationsSummary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96Thermal Resistance Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97Support for Thermal Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98Thermal Management Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99Thermal Interface Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102Heat Sink Removal Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105Soldering Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110Chapter 6: Package MarkingMarking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111Chapter 7: Packing and ShippingIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114Appendix A: Recommended PCB Design RulesBGA Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115Appendix B: Heat Sink Guidelines for Lidless Flip-Chip PackagesHeat Sink Attachments for Lidless Flip-chip BGA (FB/FBG/FBV) . . . . . . . . . . . . . . . . . . . . . . . . . . 117Types of Heat Sink Attachments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118Appendix C: Additional ResourcesXilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123Zynq-7000 SoC Packaging GuideUG865 (v1.9) July 28, 2021www.xilinx.comSend Feedback5
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124Zynq-7000 SoC Packaging GuideUG865 (v1.9) July 28, 2021www.xilinx.comSend Feedback6
Chapter 1Package OverviewSummaryThis chapter covers the following topics: Introduction Device/Package Combinations and Maximum I/Os Pin Definitions Pin Compatibility Between Packages Die Level Bank Numbering OverviewIntroductionThis section describes the pinouts for the Zynq -7000 SoC available in 0.8 mm pitch wirebond and various 0.8 mm and 1.0 mm pitch flip-chip and fine-pitch BGA packages.Package inductance is minimized as a result of optimal placement and even distribution aswell as an optimal number of Power and GND pins.The FFG, FBG, SBG, and RFG flip-chip packages are RoHS 6 of 6 compliant, with exemption15 where there is lead in the C4 bumps that are used to complete a viable electricalconnection between the semiconductor die and the package substrate. The FFG, FBG, andSBG devices marked with the Pb-free Character are RoHS 6 of 6 compliant (without the useof exemption 15).The FFV, FBV, SBV flip-chip packages are RoHS 6 of 6 compliant (without the use ofexemption 15). The CLG non-flip chip packages are RoHS 6 of 6 compliant. Select packagesinclude a Pb-only option.All of the Zynq-7000 SoC devices supported in a particular package are pinout compatible.Zynq-7000 SoC Packaging GuideUG865 (v1.9) July 28, 2021www.xilinx.comSend Feedback7
Chapter 1: Package OverviewThe Zynq-7000 SoC contains a large number of fixed and flexible I/O. Zynq-7000 SoC has aconstant 128 pins dedicated to memory interfaces (DDR I/O), multiplexed peripherals(MIO), and control. Programmable logic provides additional pins for SelectIO resources(SIO) and multi-gigabit serial transceivers (GTP or GTX) that scale by device as well as fixedpins for configuration and analog-to-digital conversion (XADC). SIO can be used to extendthe MIO to further leverage the fixed peripherals of the processing system (PS).Each device is split into I/O banks to allow for flexibility in the choice of I/O standards (seethe 7 Series FPGAs SelectIO Resources User Guide (UG471). The PS I/Os are described in theZynq-7000 SoC Technical Reference Manual (UG585). Table 1-5 provides definitions for allpin types.Zynq-7000 SoCs flip-chip assembly materials are manufactured using ultra-low alpha (ULA)materials defined as 0.002 cph/cm2 or materials that emit less than 0.002 alpha-particlesper square centimeter per hour.Zynq-7000 SoC Packaging GuideUG865 (v1.9) July 28, 2021www.xilinx.comSend Feedback8
Chapter 1: Package OverviewDevice/Package Combinations and Maximum I/OsTable 1-1 shows the maximum number of user I/Os possible in the Zynq-7000 SoC BGApackages.Table 1-1:Zynq-7000 SoC Package SpecificationsPackage geMaximumMaximumType Pitch (mm) Size (mm) SelectIO Resources(2) PS I/OsBGA0.813 x 135486BGA0.817 x 17125128BGA0.819 x 19200128CL/CLG485BGA0.819 x 19150128SBG/SBV485BGA0.819 x 19150128BGA1.023 x 23163128FB/FBG/FBV676BGA1.027 x 27250128FF/FFG/FFV676BGA1.027 x 27250128BGA1.031 x 31362128BGA1.035 x 35400128BGA1.023 x 23163128BGA1.027 x 27250128BGA1.031 x 31362128BGA1.035 x 00Wire-bondFlip-chip lidlessFlip-chipFF/FFG/FFV1156RuggedizedFlip-Chip pNotes:1. Leaded package options (CLxxx/FFxxx/FBxxx) are available. RoHS compliant options (FFG/FFV, FBG/FBV, SBG/SBV, CLG, andRFG) are described in the Introduction, page 7.2. The maximum I/O numbers do not include pins in the configuration Bank 0 (Table 1-2) or the GT serial transceivers.Table 1-2 lists the 17 dedicated pins.Table 1-2:Zynq-7000 SoC Pins in the Dedicated Configuration Bank (Bank0)DXP 0VCCBATT 0INIT B 0TDO 0TDI 0GNDADC 0DXN 0DONE 0VN 0TCK 0VREFN 0VCCADC 0VP 0TMS 0VREFP 0CFGBVS 0PROGRAM B 0Zynq-7000 SoC Packaging GuideUG865 (v1.9) July 28, 2021www.xilinx.comSend Feedback9
Chapter 1: Package OverviewSerial Transceiver Channels by Device/PackageTable 1-3 lists the quantity of GTX serial transceiver channels for most of the Zynq-7000 SoCdevices. In all devices, a serial transceiver channel is one set of MGTRXP, MGTRXN, MGTTXP,and MGTTXN pins. The XC7Z012S and XC7Z015, in the CLG485 package, have four GTPserial transceiver channels.Table 1-3:Serial Transceiver Channels by Device/PackageGTX (or GTP) Channels by PackageDeviceCL/CLG225FB/FBG/FBV484 FB/FBG/FBV676CL/CLG400 CL/CLG485 SBG/SBV485FF/FFG/FFV676 FF/FFG/FFV900 ––XC7Z012S–4 (GTP)––––XC7Z015–4 6–XQ7Z100––––1616Table 1-4 shows the number of available SelectIO resources (SIO), the number of differentialSIO pairs, and the number of available PS I/Os for each Zynq-7000 SoC device/packagecombination. When applicable, it also lists the number of SIOs in the 3.3V-capablehigh-range (HR) banks and the number of 1.8V-capable high-performance (HP) banks.IMPORTANT: Because of package inductance, each device/package supports a limited number ofsimultaneous switching outputs. Limitations for specific applications can be determined using theVivado Design Suite report ssn tool. See the Simultaneous Switching Outputs section of the 7 SeriesFPGAs SelectIO Resources User Guide (UG471) for more information.Zynq-7000 SoC Packaging GuideUG865 (v1.9) July 28, 2021www.xilinx.comSend Feedback10
Chapter 1: Package OverviewTable 1-4:Available SIO and PS I/O Pins by Device/Package CL484CLG484CLG485CL400CLG400I/O /OI/OI/OI/OI/OI/OI/OHR HPHR HPHR HPHR HPHR HPHR HPHR HPHR HP I/O540Differential 27054XC7Z010 User I/OXA7Z010 Differential 270XC7Z007SUser I/O86 –––––––86 �–––––––––User �–User �–User I/O–––1250128 –––––––––XC7Z020 User I/OXA7Z020 Differential–––1250128 ––––––User I/O–––––––––100 63 128 50 100 128 100 150 �–––48User �–––––User �–User I/O–––––Differential––––User I/O–––Differential––User Z100–2448–4872–––––––100 63 –––100 150 128 212 150 ––––––––––100 150 128 212 150 ��102 ––212 150 128 250 150 �102 –––––––––User I/O–––––––––100 63 128–––100 150 �–––4829––––48––––––User 0 150 128 212 150 �––––––4872–102 72–––User �––212 150 128 250 150 �––––––102 72Zynq-7000 SoC Packaging GuideUG865 (v1.9) July 28, 2021128 20029–www.xilinx.com7272––102 72–––––120 72120 72Send Feedback––11
Chapter 1: Package OverviewPin DefinitionsTable 1-5 lists the pin definitions used in Zynq-7000 SoC packages.Note: There are dedicated general purpose user I/O pins listed separately in Table 1-5. There arealso multi-function pins where the pin names start with either IO LXXY ZZZ # or IO XX ZZZ #,where ZZZ represents one or more functions in addition to being general purpose user I/O. If notused for their special function, these pins can be user I/O.Table 1-5:Zynq-7000 SoC Pin DefinitionsPin NameTypeDirectionDescriptionUser I/O PinsIO LXXY #IO XX #DedicatedInput/OutputMost user I/O pins are capable of differential signalingand can be implemented as pairs. The top and bottom I/Opins are always single ended. Each user I/O is labeledIO LXXY #, where: IO indicates a user I/O pin. L indicates a differential pair, with XX a unique pair inthe bank and Y [P N] for the positive/negative sides ofthe differential pair. # indicates a bank number.Configuration PinsFor more information about these pins, see the Configuration Pin Definitions table in the 7 Series FPGAsConfiguration User Guide (UG470). See also the Boot and Configuration chapter in the Zynq-7000 SoC TechnicalReference Manual (UG585).DONE 0Dedicated (1)BidirectionalActive High, DONE indicates successful completion ofconfiguration.INIT B 0Dedicated (1)Bidirectional(open-drain)Active Low, indicates initialization of configurationmemory.PROGRAM B 0Dedicated (1)InputActive Low, asynchronous reset to configuration logic.TCK 0Dedicated (1)InputJTAG clock.TDI 0Dedicated (1)InputJTAG data input.TDO 0Dedicated (1)OutputJTAG data output.TMS 0Dedicated (1)InputJTAG mode select.InputThis pin selects the preconfiguration I/O standard type forthe dedicated configuration bank 0. If the VCCO for bank 0is 2.5V or 3.3V, then this pin must be connected to V CCO 0.If the V CCO for bank 0 is less than or equal to 1.8V, then thispin should be connected to GND.CFGBVS 0Dedicated (1)Note: To avoid device damage, this pin must beconnected correctly. See the Configuration Bank VoltageSelect section in the 7 Series FPGAs Configuration UserGuide (UG470) for more information.Zynq-7000 SoC Packaging GuideUG865 (v1.9) July 28, 2021www.xilinx.comSend Feedback12
Chapter 1: Package OverviewTable 1-5:Zynq-7000 SoC Pin Definitions (Cont’d)Pin NameTypeDirectionDescriptionPull-Up During Configuration (bar)Active-Low PUDC B input enables internal pull-upresistors on the SelectIO pins after power-up and duringconfiguration.PUDC BMulti-functionInput When PUDC B is Low, internal pull-up resistors areenabled on each SelectIO pin. When PUDC B is High, internal pull-up resistors aredisabled on each SelectIO pin.PUDC B must be tied either directly (or through a 1KΩ orless resistor) to VCCO 34 or GND.CAUTION! Do not allow this pin to float before andduring configuration.Power/Ground PinsGNDDedicatedN/AGround, tied common.VCCPINTDedicatedN/A1.0V logic supply for PS. Independent from PL V CCINTsupply.VCCPAUXDedicatedN/A1.8V auxiliary power supply for PS. Independent from PLV CCAUX supply.VCCO MIO0DedicatedN/A1.8V–3.3V PS I/O supply for MIO bank 500.VCCO MIO1DedicatedN/A1.8V–3.3V PS I/O supply for MIO bank 501.VCCO DDRDedicatedN/A1.2V–1.8V DDR I/O supply.VCCPLL(2)DedicatedN/A1.8V PLL supply for PS. A 0.47 µF to 4.7 µF 0402 capacitormust be placed near the VCCPLL BGA via. In addition, whenpowered by VCCPAUX, the V CCPLL must be filtered througha 120Ω at 100 MHz (size 0603) ferrite bead and a 10 µF(size 0603) decoupling capacitor to minimize PLL jitter.VCCAUXDedicatedN/A1.8V power-supply pins for auxiliary circuits.VCCAUX IO G#(3)DedicatedN/A1.8V/2.0V power-supply pins for auxiliary I/O circuits.VCCINTDedicatedN/A1.0V power-supply pins for the internal core logic.VCCO #(4)DedicatedN/APower-supply pins for the output drivers (per bank).VCCBRAMDedicatedN/A1.0V power-supply pins for the PL block RAM.VCCBATT 0DedicatedN/ADecryptor key memory backup supply; this pin should betied to the appropriate VCC or GND when not used.(5)Multi-functionN/AThese are input threshold voltage pins. They become userI/Os when an external threshold voltage is not needed(per bank).RSVDVCC[3:1]DedicatedN/AReserved pins—must be tied to V CCO 0.RSVDGNDDedicatedN/AReserved pins—do not connect.VREFZynq-7000 SoC Packaging GuideUG865 (v1.9) July 28, 2021www.xilinx.comSend Feedback13
Chapter 1: Package OverviewTable 1-5:Zynq-7000 SoC Pin Definitions (Cont’d)Pin NameTypeDirectionDescriptionPS MIO PinsPower on reset. The PS POR B must be asserted to GNDduring the power-on sequence until VCCPINT, V CCPAUX, andV CCO MIO0 have reached the minimum operating levelsand the PS CLK reference is within specification. Whendeasserted, the PS begins the boot process. Before V CCPINTreaches 0.80V, at least one of these four conditions isrequired during the power-off stage:PS POR BDedicatedInput The PS POR B input is asserted to GND. The reference clock to the PS CLK input is disabled. V CCPAUX is lower than 0.70V. V CCO MIO0 is lower than 0.90V.To ensure PS eFUSE integrity, the applicable conditionmust be held until V CCPINT reaches 0.40V.See the Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S,Z-7010, Z-7015, and Z-7020) Data Sheet: DC and ACSwitching Characteristics (DS187) and Zynq-7000 SoC(Z-7030, Z-7035, Z-7045, and Z-7100) Data Sheet: DC andAC Switching Characteristics (DS191) for more informationon the power-on sequence.PS CLKDedicatedInputSystem reference clock. PS CLK must be between 30 MHzand 60 MHz.PS SRST BDedicatedInputSystem reset. For use with debuggers. When 0, forces thePS to enter the system reset sequence.The PS MIO VREF provides a reference voltage for theRGMII input receivers.If an RGMII interface is not being used, the PS MIO VREFpin can be left to float.PS MIO VREFDedicatedVoltageReferenceIf an RGMII interface is being used, tie this pin to a voltageequal to ½ VCCO MIO1 .Example: When using a HSTL18 RGMII interface theV CCO MIO1 is set to 1.8V. The PS MIO VREF must be set to0.9V.A resistor divider can be used to generate thePS MIO VREF.See the Zynq-7000 SoC PCB Design Guide (UG933) fordecoupling recommendations.PS MIO[53:0]Multiuse I/O. Multiuse I/O can be configured to supportmultiple I/O interfaces. These interfaces include SPI andMulti-function Input/OutputQuad-SPI flash, NAND, USB, Ethernet, SDIO, UART, SPI, andGPIO interfaces.Zynq-7000 SoC Packaging GuideUG865 (v1.9) July 28, 2021www.xilinx.comSend Feedback14
Chapter 1: Package OverviewTable 1-5:Zynq-7000 SoC Pin Definitions (Cont’d)Pin NameTypeDirectionDescriptionPS DDR CKPDedicatedOutputDDR differential clock positive.PS DDR CKNDedicatedOutputDDR differential clock negative.PS DDR CKEDedicatedOutputDDR clock enable.PS DDR CS BDedicatedOutputDDR chip select.PS DDR RAS BDedicatedOutputDDR RAS control signal.PS DDR CAS BDedicatedOutputDDR CAS control signal.PS DDR WE BDedicatedOutputDDR write enable signal.PS DDR BA[2:0]DedicatedOutputDDR bank address.PS DDR A[14:0]DedicatedOutputDDR row and column address.PS DDR ODTDedicatedOutputDDR termination control.PS DDR DRST BDedicatedOutputDDR reset signal for DDR3 devices.PS DDR DQ[31:0]DedicatedPS DDR DM[3:0]DedicatedPS DDR DQS P[3:0]DedicatedInput/Output DDR differential data strobe positive.PS DDR DQS N[3:0]DedicatedInput/Output DDR differential data strobe negative.PS DDR PinsPS DDR VRPInput/Output DDR data.OutputDedicatedDDR data mask.OutputDDR DCI voltage reference positive. Used to calibrate DDRI/O drive strength. Connect to a resistor to GND. The valueof the resistor should be twice the DDR termination andtrace impedance.DDR DCI voltage reference negative. Used to calibrateDDR I/O drive strength. Connect to a resistor to VCCO DDR.The value of the resistor should be twice the DDRtermination and trace impedance.PS DDR VRNDedicatedOutputPS DDR VREF[1:0]DedicatedVoltageReferenceVoltage reference for the DDR interface.Analog to Digital Converter (XADC) PinsFor more information, see the XADC Package Pins table in the 7 Series FPGAs and Zynq 7000 SoC XADC Dual12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480).VCCADC 0 (6)DedicatedN/AXADC analog positive supply voltage.GNDADC 0 (6)DedicatedN/AXADC analog ground reference.VP 0(6)DedicatedInputXADC dedicated differential analog input (positive side).VN 0 (6)DedicatedInputXADC dedicated differential analog input (negative side).DedicatedN/A1.25V reference input.DedicatedN/A1.25V reference GND reference.VREFP 0 (6)VREFN0 (6)AD0P through AD15PMulti-functionAD0N through AD15NZynq-7000 SoC Packaging GuideUG865 (v1.9) July 28, 2021InputXADC (analog-to-digital converter) differential auxiliaryanalog inputs 0–15.www.xilinx.comSend Feedback15
Chapter 1: Package OverviewTable 1-5:Zynq-7000 SoC Pin Definitions (Cont’d)Pin NameTypeDirectionDescriptionMulti-gigabit Serial Transceiver Pins (GTXE2 and GTPE2)For more information on the GTXE2 pins see the Pin Description and Design Guidelines section in the 7 SeriesFPGAs GTX/GTH Transceivers User Guide (UG476). The GTPE2 pins are described in the Pin Description and DesignGuidelines section of the 7 Series FPGAs GTP Transceivers User Guide (UG482).MGTXRXP[0:3] orPositive differential receive dicatedOutputMGTAVCC G#(7)DedicatedInput1.0V analog power-supply pin for the receiver andtransmitter internal circuits.MGTAVTT G#(7)DedicatedInput1.2V analog power-supply pin for the transmit driver.MGTVCCAUX G# (7)DedicatedInput1.8V auxiliary analog Quad PLL (QPLL) voltage supply forthe GTXE2 transceivers only.MGTREFCLK0/1PDedicatedInputPositive differential reference clock for the transceivers.MGTREFCLK0/1NDedicatedInputNegative differential reference clock for the transceivers.MGTPRXP[0:3]MGTXRXN[0:3] orMGTPRXN[0:3]MGTXTXP[0:3] orMGTPTXP[0:3]MGTXTXN[0:3] orMGTPTXN[0:3]Negative differential receive port.Positive differential transmit port.Negative differential transmit port.MGTAVTTRCALDedicatedN/AGTXE2 precision reference resistor pin for internalcalibration termination. Not used for the XC7Z007S,XC7Z010, XC7Z012S, XC7Z014S, XC7Z015, or XC7Z020devices.MGTRREFDedicatedInputPrecision reference resistor pin for internal calibrationtermination.InputThese are the clock capable I/Os driving BUFRs, BUFIOs,BUFGs, and MMCMs/PLLs. In addition, these pins can drivethe BUFMR for multi-region BUFIO and BUFR sup
XC7Z100 devices. Added the XA Zynq-7000 SoC devices (XA7Z010 and XA7Z020). Added the Zynq-7000Q SoC devices (XQ7Z020, XQ7Z030, and XQ7Z045) and the RF484 and RF676 packages. Updated the Notice of Disclaimer. Clarified the maximum and ava ilable PS I/O pins as 128 in Table 1-1 and Table 1-4 . In Table 1-5 , updated the PUDC_B description.
