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Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)X5R Dielectric, 4 – 50 VDC (Commercial Grade)Table 3 – Chip Capacitor Land Pattern Design Recommendations per IPC–7351EIASizeCodeMetricSizeCode0201Density Level A:Maximum (Most)Land Protrusion (mm)Density Level B:Median (Nominal)Land Protrusion (mm)Density Level C:Minimum (Least)Land Protrusion ly for capacitance values 22 µFDensity Level A: For low-density product applications. Recommended for wave solder applications and provides a wider process window for reflowsolder processes. KEMET only recommends wave soldering of EIA 0603, 0805 and 1206 case sizes.Density Level B: For products with a moderate level of component density. Provides a robust solder attachment condition for reflow solder processes.Density Level C: For high component density product applications. Before adapting the minimum land pattern variations the user should performqualification testing based on the conditions outlined in IPC Standard 7351 (IPC–7351).1Image below based on Density Level B for an EIA 1210 case size.V1YYXXCCV2Grid Placement Courtyard KEMET Electronics Corporation P.O. Box 5928 Greenville, SC 29606 864-963-6300 www.kemet.comC1006 X5R SMD 11/15/20169

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)X5R Dielectric, 4 – 50 VDC (Commercial Grade)Soldering ProcessRecommended Soldering Technique: Solder wave or solder reflow for EIA case sizes 0603, 0805 and 1206 All other EIA case sizes are limited to solder reflow onlyRecommended Reflow Soldering Profile:KEMET’s families of surface mount multilayer ceramic capacitors (SMD MLCCs) are compatible with wave (single or dual),convection, IR or vapor phase reflow techniques. Preheating of these components is recommended to avoid extreme thermalstress. KEMET’s recommended profile conditions for convection and IR reflow reflect the profile conditions of the IPC/J-STD-020 standard for moisture sensitivity testing. These devices can safely withstand a maximum of three reflow passesat these conditions.Termination FinishSnPbTP100% Matte SnPreheat/SoakTemperature Minimum (TSmin)Temperature Maximum (TSmax)Time (tS) from TSmin to TSmax100 C150 C60 – 120 seconds150 C200 C60 – 120 secondsRamp-Up Rate (TL to TP)3 C/secondmaximum3 C/secondmaximumLiquidous Temperature (TL)183 C217 CTime Above Liquidous (tL)60 – 150 seconds60 – 150 secondsPeak Temperature (TP)235 C260 CTime Within 5 C of MaximumPeak Temperature (tP)20 secondsmaximum30 secondsmaximumRamp-Down Rate (TP to TL)6 C/secondmaximum6 C/secondmaximumTLTemperatureProfile FeaturetPMaximum Ramp Up Rate 3ºC/secMaximum Ramp Down Rate 6ºC/sectLTsmaxTsmin25ts25ºC to PeakTimeTime 25 C to Peak6 minutes8 minutesTemperaturemaximummaximumNote 1: All temperatures refer to the center of the package, measured on thecapacitor body surface that is facing up during assembly reflow. KEMET Electronics Corporation P.O. Box 5928 Greenville, SC 29606 864-963-6300 www.kemet.comC1006 X5R SMD 11/15/201610

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)X5R Dielectric, 4 – 50 VDC (Commercial Grade)Table 4 – Performance & Reliability: Test Methods and ConditionsStressReferenceTest or Inspection MethodTerminal StrengthJIS–C–6429Appendix 1, Note: Force of 1.8 kg for 60 seconds.Board FlexJIS–C–6429Appendix 2, Note: Standard termination system – 2.0 mm (minimum) for all except 3 mm forC0G. Flexible termination system – 3.0 mm (minimum).Magnification 50 X. Conditions:SolderabilityJ–STD–002a) Method B, 4 hours at 155 C, dry heat at 235 Cb) Method B at 215 C category 3c) Method D, category 3 at 260 CTemperature CyclingBiased HumidityMoisture ResistanceThermal ShockHigh Temperature LifeJESD22 Method JA–104MIL–STD–202 Method103MIL–STD–202 Method106MIL–STD–202 Method107MIL–STD–202 Method108/EIA–198Storage LifeMIL–STD–202 Method108VibrationMIL–STD–202 Method204Mechanical ShockResistance to SolventsMIL–STD–202 Method213MIL–STD–202 Method2151,000 Cycles ( 55 C to 125 C). Measurement at 24 hours / 4 hours after test conclusion.Load Humidity: 1,000 hours 85 C/85% RH and rated voltage. Add 100 K ohm resistor.Measurement at 24 hours / 4 hours after test conclusion.Low Volt Humidity: 1,000 hours 85 C/85% RH and 1.5 V. Add 100 K ohm resistor.Measurement at 24 hours / 4 hours after test conclusion.t 24 hours/cycle. Steps 7a and 7b not required.Measurement at 24 hours / 4 hours after test conclusion. 55 C/ 125 C. Note: Number of cycles required – 300. Maximum transfer time – 20seconds. Dwell time – 15 minutes. Air – Air.1,000 hours at 85 C with 2 X rated voltage applied excluding the following:Case SizeCapacitance0402 0.22 µF0603 1.0 µF0805 4.7 µF1206 2.2 µF1210 10 µFApplied Voltage1.5 X150 C, 0 VDC for 1,000 hours.5 g's for 20 minutes, 12 cycles each of 3 orientations. Note: Use 8" X 5" PCB 0.031" thick7 secure points on one long side and 2 secure points at corners of opposite sides. Partsmounted within 2" from any secure point. Test from 10 – 2,000 HzFigure 1 of Method 213, Condition F.Add aqueous wash chemical, OKEM Clean or equivalent.Storage and HandlingCeramic chip capacitors should be stored in normal working environments. While the chips themselves are quite robust inother environments, solderability will be degraded by exposure to high temperatures, high humidity, corrosive atmospheres,and long term storage. In addition, packaging materials will be degraded by high temperature–reels may soften or warpand tape peel force may increase. KEMET recommends that maximum storage temperature not exceed 40ºC and maximumstorage humidity not exceed 70% relative humidity. Temperature fluctuations should be minimized to avoid condensation onthe parts and atmospheres should be free of chlorine and sulfur bearing compounds. For optimized solderability chip stockshould be used promptly, preferably within 1.5 years of receipt. KEMET Electronics Corporation P.O. Box 5928 Greenville, SC 29606 864-963-6300 www.kemet.comC1006 X5R SMD 11/15/201611

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)X5R Dielectric, 4 – 50 VDC (Commercial Grade)Construction (Typical)Detailed Cross SectionDielectric Material(BaTiO3)Barrier Layer(Ni)TerminationFinish(100% Matte Sn)DielectricMaterial (BaTiO3)End Termination/External Electrode(Cu)Inner Electrodes(Ni)End Termination/External Electrode(Cu)Barrier Layer(Ni)TerminationFinish(100% Matte Sn)Inner Electrodes(Ni) KEMET Electronics Corporation P.O. Box 5928 Greenville, SC 29606 864-963-6300 www.kemet.comC1006 X5R SMD 11/15/201612

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)X5R Dielectric, 4 – 50 VDC (Commercial Grade)Capacitor Marking (Optional):These surface mount multilayer ceramic capacitors arenormally supplied unmarked. If required, they can bemarked as an extra cost option. Marking is availableon most KEMET devices but must be requested usingthe correct ordering code identifier(s). If this option isrequested, two sides of the ceramic body will be lasermarked with a “K” to identify KEMET, followed by twocharacters (per EIA–198 - see table below) to identify thecapacitance value. EIA 0603 case size devices are limitedto the “K” character only. X7R dielectric products in capacitance values outlinedbelowMarking appears in legible contrast. Illustrated below is anexample of an MLCC with laser marking of “KA8”, whichdesignates a KEMET device with rated capacitance of 100 µF.Orientation of marking is vendor optional.KEMETIDLaser marking option is not available on: C0G, Ultra Stable X8R and Y5V dielectric devices EIA 0402 case size devices EIA 0603 case size devices with Flexible Terminationoption. KPS Commercial and Automotive Grade stacked devices.EIA Case SizeMetric Size 5160820123216322545204532456456505664 170 pF 150 pF 910 pF 2,000 pF 3,900 pF 6,700 pF 0.018 µF 0.027 µF 0.033 µF KEMET Electronics Corporation P.O. Box 5928 Greenville, SC 29606 864-963-6300 www.kemet.com2-DigitCapacitanceCodeC1006 X5R SMD 11/15/201613

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)X5R Dielectric, 4 – 50 VDC (Commercial Grade)Capacitor Marking (Optional) cont’dAlphaCharacterCapacitance (pF) For Various Alpha/Numeral IdentifiersNumeral9012345678100,000,000Capacitance 0,000,000900,000,000 KEMET Electronics Corporation P.O. Box 5928 Greenville, SC 29606 864-963-6300 www.kemet.comC1006 X5R SMD 11/15/201614

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)X5R Dielectric, 4 – 50 VDC (Commercial Grade)Tape & Reel Packaging InformationKEMET offers multilayer ceramic chip capacitors packaged in 8, 12 and 16 mm tape on 7" and 13" reels in accordance withEIA Standard 481. This packaging system is compatible with all tape-fed automatic pick and place systems. See Table 2 fordetails on reeling quantities for commercial chips.Bar Code LabelAnti-Static Reel Embossed Plastic* orPunched Paper Carrier.ETKEMChip and KPS Orientation in Pocket(except 1825 Commercial, and 1825 and 2225 Military)Sprocket HolesEmbossment or Punched Cavity8 mm, 12 mmor 16 mm Carrier Tape178 mm (7.00")or330 mm (13.00")Anti-Static Cover Tape(.10 mm (.004") Maximum Thickness)*EIA 01005, 0201, 0402 and 0603 case sizes available on punched paper carrier only.Table 5 – Carrier Tape Configuration, Embossed Plastic & Punched Paper (mm)EIA Case SizeTapeSize(W)*Embossed Plastic7" Reel13" ReelPitch (P1)*Punched Paper7" Reel13" ReelPitch (P1)*01005 – 0402822060382/42/40805844441206 – 1210844441805 – 18081244 18121288KPS 12101288KPS 1812 & 2220161212Array 0508 & 0612844*Refer to Figures 1 & 2 for W and P1 carrier tape reference locations.*Refer to Tables 6 & 7 for tolerance specifications.New 2 mm Pitch Reel Options*PackagingOrdering Code(C-Spec)Packaging Type/OptionsC-3190C-3191C-7081C-7082Automotive grade 7" reel unmarkedAutomotive grade 13" reel unmarkedCommercial grade 7" reel unmarkedCommercial grade 13" reel unmarked* 2 mm pitch reel only available for 0603 EIA case size.2 mm pitch reel for 0805 EIA case size under development.Benefits of Changing from 4 mm to 2 mm Pitching Spacing Lower placement costs Double the parts on each reel results in fewer reelchanges and increased efficiency Fewer reels result in lower packaging, shipping andstorage costs, reducing waste KEMET Electronics Corporation P.O. Box 5928 Greenville, SC 29606 864-963-6300 www.kemet.comC1006 X5R SMD 11/15/201615

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)X5R Dielectric, 4 – 50 VDC (Commercial Grade)Figure 1 – Embossed (Plastic) Carrier Tape DimensionsP2TT2ØDo[10 pitches cumulativetolerance on tape 0.2 mm]PoE1AoFKoB1E2BoS1WP1T1Center Lines of CavityØDCover TapeB 1 is for tape feeder reference only,including draft concentric about Bo.1EmbossmentFor cavity size,see Note 1 Table 4User Direction of UnreelingTable 6 – Embossed (Plastic) Carrier Tape DimensionsMetric will governConstant Dimensions — Millimeters (Inches)Tape SizeD08 mm12 mm1.5 0.10/-0.0(0.059 0.004/0.0)16 mmD1 MinimumNote 11.0(0.039)1.5(0.059)R Reference S1 MinimumTNote 2Note 3Maximum25.0(0.984)1.75 0.104.0 0.102.0 0.050.6000.600(0.069 0.004) (0.157 0.004) (0.079 0.004)Variable Dimensions — Millimeters (Inches)Tape SizePitch8 mmSingle (4 mm)12 mmSingle (4 mm) &Double (8 mm)16 mmTriple (12 mm)B1 MaximumNote 46)10.25(0.404)14.25(0.561)FP13.5 0.054.0 0.10(0.138 0.002) (0.157 0.004)5.5 0.058.0 0.10(0.217 0.002) (0.315 0.004)7.5 0.0512.0 0.10(0.138 0.002) (0.157 mum8.3(0.327)12.3(0.484)16.3(0.642)A0,B0 & K0Note 51. The embossment hole location shall be measured from the sprocket hole controlling the location of the embossment. Dimensions of embossmentlocation and hole location shall be applied independent of each other.2. The tape with or without components shall pass around R without damage (see Figure 6).3. If S1 1.0 mm, there may not be enough area for cover tape to be properly applied (see EIA Standard 481 paragraph 4.3 section b).4. B1 dimension is a reference dimension for tape feeder clearance only.5. The cavity defined by A0, B0 and K0 shall surround the component with sufficient clearance that:(a) the component does not protrude above the top surface of the carrier tape.(b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed.(c) rotation of the component is limited to 20 maximum for 8 and 12 mm tapes and 10 maximum for 16 mm tapes (see Figure 3).(d) lateral movement of the component is restricted to 0.5 mm maximum for 8 and 12 mm wide tape and to 1.0 mm maximum for 16 mm tape (seeFigure 4).(e) for KPS Series product, A0 and B0 are measured on a plane 0.3 mm above the bottom of the pocket.(f) see Addendum in EIA Standard 481 for standards relating to more precise taping requirements. KEMET Electronics Corporation P.O. Box 5928 Greenville, SC 29606 864-963-6300 www.kemet.comC1006 X5R SMD 11/15/201616

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)X5R Dielectric, 4 – 50 VDC (Commercial Grade)Figure 2 – Punched (Paper) Carrier Tape DimensionsTPoØDo[10 pitches cumulativetolerance on tape 0.2 mm]A0FP1T1T1Top Cover TapeWE2B0Bottom Cover TapeE1GCavity Size,SeeNote 1, Table 7Center Lines of CavityBottom Cover TapeUser Direction of UnreelingTable 7 – Punched (Paper) Carrier Tape DimensionsMetric will governConstant Dimensions — Millimeters (Inches)Tape SizeD0E1P0P2T1 MaximumG Minimum8 mm1.5 0.10 -0.0(0.059 0.004 -0.0)1.75 0.10(0.069 0.004)4.0 0.10(0.157 0.004)2.0 0.05(0.079 0.002)0.10(0.004)MaximumR ReferenceNote 20.75(0.03

DWV is the voltage a capacitor can withstand (survive) for a short period of time. It exceeds the nominal and continuous working voltage of the capacitor. 3 . Capacitance and dissipation factor (DF) measured under the following conditions: 1 kHz 50 Hz and 1.0 0.2 Vrms if capacitance 10 µF