WIXLIB

“The Role of Flip ChipBonding in AdvancedPackaging”David PedderDavid Pedder AssociatesStanford in the ValeFaringdonOxfordshire

“The Role of Flip Chip Bonding in AdvancedPackaging” OutlineFlip Chip DefinitionsFlip Chip TechnologiesFlip Chip PropertiesFlip Chip ApplicationsFlip Chip – The FutureSummary & Conclusions

Flip Chip Definitions * Flip“ A mixture of beer & spiritssweetened with sugar and heatedwith a hot iron” Chip“ A counter used in games of chance” Bond“ in a state of serfdom or slavery”or .* Shorter Oxford English Dictionary, Vol. 1, 1970

Flip Chip Definitions * Flip Chip Bonding - The connection of a device,bond pads face down, onto a substrate with amatching array of bond pads

Flip chip bonding history 1960– IBM develops Solid Logic Technology 1964– Totta and Miller develop the C4 process– C4 Controlled Collapse Chip ConnectionIBMCorporationIBM Corporation

Flip chip bonding evolution 3 bonds/chip1964Cu balltransistor 10-30 bonds/chip 1970C4SSIC 120 bonds/chip1980C4LSI 354 bonds/chip1985C4VLSI 2100 bonds/chip2000C4SoC

Flip chip bonding advantages Very high interconnection densityArea array and peripheral bonds possibleFine pitch (50 m) connections possible Improved high frequency/speedperformancePac Tech GmbHShort/repeatable connection lengthReduced electrical parasitics Minimal component footprintTrue chip scale packageNational Semiconductor Corp

Flip chip bonding technologies Solder flip chip Adhesive flip chip Solid phase flip chip

Solder flip chip bonding Common usesFlip chip on board (FCOB)Flip chip in package (FCIP)System in package (SiP)Hybrid modules Solder advantagesSelf aligning ( 1 m)Typical flip chip in package

Solder flip chip bondingBondingBumpingDevicereflowedAs depositedPbCrCu/CuSnoxideAlSipassivationDevice Controlled dewetting CrCuAu wettable metal 95Pb5Sn solderSubstrate Limited wettable areas Surface tension controlledalignmentstand-off

Solder flip chip bond designmg/nS p.ASSubstrate Balance of surface tension & gravitational forcesConservation of volume allows joint designSurface tension dominatesDouble truncated sphere approximationSets solder uniformity requirements, mixed bond design

Solder flip chip bond design 0o 180oPerimeter volume Solder volume uniformity requirements

Solder flip chip bond designAs 83.0 Matched 18 & 70 m bond design

Solder flip chip bond alignment Solder vernier structure Alignment 2 m vernier resolution

Solder bumping Wafer level processing Under bump metallisation (UBM)Ohmic contactAdhesion/barrier between the pad and the bumpWettable surface Common UBM deposition techniquesPlatingEvaporationSputtering Typical UBMsNi/AuCr/CrCu/Cu/AuNiV/CuTiWIC Interconnect

Solder bumping Typical solder alloysHigh melting point Lead/Tin (95/5) solderEutectic Tin/Lead (63/37) solderLead-free solder: Tin/Copper/Silver etcEutectic Gold/Tin (80/20) solder Common solder deposition techniquesEvaporationPlatingStencil printingLaser dispenseMould transferIC Interconnect

Solder bumping underfill Required for flip chip on board (FCOB) reliability Underfill processunderfill dispenseunderfill cureDispense needleFlip Chip Integrated CircuitLaminate Printed Circuit BoardUnderfill drawnunder die by capillaryaction

Solder bumping reliabilitySisoldersubstrate Factorshd Low cycle thermal fatigueCycle amplitudeChip sizeCTE mismatchSolder alloyBond geometryUse of underfill

Adhesive flip chip bonding Common usesChip on glass (COG)Chip on flex (COF) Adhesive advantagesFine pitch (50µm)Low temperature processNo separate underfill required (Anisotropic Conductive Adhesive)Lead-free

Adhesive flip chip wafer bumping Wafer level processing Common bump deposition techniquesGold stud bumps formed with a gold ball bonderElectroless plated nickel bumps/thin immersion goldElectrolytic plated gold bumps, typically on a TiW UBMPolymer bumps (selectively placed conducting adhesive)Hesse & KnippsCitizen Watch Co., Ltd.

Adhesive flip chip bondingHeated pick-uptoolAnisotropicConductive Film(conductive particlesin a non-conductiveadhesive)Integrated Circuit DieSubstrate

Adhesive flip chip bonding

Solid phase flip chip bonding Common usesFlip chip on board (FCOB)Flip chip in package (FCIP)System in package (SIP)Hybrid modules Die pads require bumpingGold stud bumpsElectroplated gold bumpsHesse & Knipps

Solid phase bonding processesHeat, compressionHeat, compression,ultrasonic vibrationHesse & KnippsThermocompressionThermosonicHesse & Knipps

Solid phase bump coiningIndividual/gang coining

Solder flip chip bond propertiesBonding ParameterMaterial(s)Melting temperature, oCTypical bond geometryTypical pitch, mBond strength, gramsBond resistance, m.ohmsInterbond capacitance, pFBond inductance, nHThermal resistanceoC/mW per bondNo. of I/Os per chip4mm chip size8mm chip sizeWire BondAlAu660106425 m diameterx 2.5mm length100 m 100 m tape x2.5mm length200 m perimeter50170.0062.18Flip ChipPb-Sn310 or 183100 m diameter80 m height200 m area201.20.001 0.20.5160320801604001600160320

Flip chip industry infrastructure Wafer bumpingOver 20 companies established Flip chip substrates 20 companies established Flip chip equipmentOver 20 manufacturers established Flip chip assembly servicesOver 30 subcontractorsTyco Electronics

Flip chip applications Silicon devicesDiscretesRFICs - SiGeASICs, Microprocessors & System-on-Chip GaAs devicesIntegrated Passive Devices (IPDs)System-in-Package (SiPs)3D IntegrationPhotonics Assembliesdevice and substrate alignmentspatial light modulator SensorsUncooled, cooled IR sensorsHDD readers

Flip chip discretesSource: National Semiconductor.

Flip chip on leadSOT23MLPSource: Carsem.

Flip chip RFICBluetooth Radio ModuleRF IC: 46 flip chip bonds at 200 m pitchThin film integrated passives substrate40 BGA balls at 0.80mm pitchSource: Intarsia.

Flip chip CPU ICPentium II chip : 2100 flip chip bonds at 250 m pitchBGA substrate570 BGA balls at 1.27mm pitchmini-cartridge substrate240 way connectorSource: Intel

Flip chip GaAsSource:GMMT

Flip chip IPDsSource:CMDSource: Telephus

Flip chip SiPsSource: Intarsia.Source: STMicroelectronics

Flip chip SiP utilisationSiP technologies - die level20181614121086420bare CSP Otherdiedie packaging2D3Ddie placementwirebondflip solder TSVchip balldie interconnectionSource: eKTN

Flip chip 3D integrationSource: iNEMI, IMEC

Flip chip 3D integrationSource: iNEMI, Renesas

Flip chip 3D integrationTSV16Gbmemory(8 x 2Gb)560μmMicrobump50μm thick ChipLaserdrilledviaSource: iNEMI, Samsung

Flip chip photonics devicesSource: GMMT

Flip chip IR sensor devicesSource: Irisys

Flip chip hard disc sensor devicesSource: Seagate

Flip Chip Trends Much wider uptake2% to 10% all devicesIPDs & high I/O devicesGrowth of infrastructure New technologies Cu pillar bumpingSource: TechSearch International, Inc.Lower cost processes Finer pitch Chip-to-chip bonding Improved reliabilityFlip Chip BondingSource: ChipWorks

Flip Chip Futures Flip chip usage will continue to grow DriversHigh I/O applicationsWhere size is criticalHigh frequency/speed applicationsIPDs, SiPs, 3D integrationFlip Chip Bonding

Thank you for your attentionDavid PedderDavid Pedder Associates18, Ock Meadow, Stanford in the ValeFaringdon, Oxfordshire SN7 8LNDJPedderDPA@aol.com 44 (0)1367 718420 44 (0)7899 952230

Solder bumping underfill Required for flip chip on board (FCOB) reliability Underfill process. underfill dispense underfill cure. Flip Chip Integrated Circuit. Laminate Printed Circuit Board. Dispense needle. Underfill drawn. under die by capillary. action