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FDXcellerator and the growing 22FDX ecosystemDr. Gerd Teepe, Director Marketing for Europe
Technology Effects are Accelerating 2017 GLOBALFOUNDRIES2
GLOBALFOUNDRIES Dual Track RoadmapMarkets High PerformanceComputingWireless,Battery-powered ComputingMarketsPremium Tier Low & mid-endsmartphones Wireless IoT Autonomous vehicles Mobile camerasFeaturesVolume TierServersHPC / core networkingGraphicsHigh-end smartphonesEUVeNVM7nmFinFET High performance Balanced cost12FDXTM7.5TRFAutoeNVM12/14nmFinFET22FDX 28nm40/55nm 2017 GLOBALFOUNDRIESFeatures Low powerCost-effective performanceRFEmbedded memory3
22FDX Markets: Targeted To Serve Key SegmentsMobilityIoTRF & mmWaveAutomotiveAP/MPU/AIBLE / NB-IoT / GPS / NFC5G / LTE / WiFiMCU/Radar/ADAS/IVIBody-bias equivalent to 1 node Cortex -A53 w/ 40% lower powervs. 28HKMG Roadmap to 7nm perf. w/12FDX Natural migration from 55/40nm Lower active (-80%) and standby(1pA/cell) power than 40nm PA, Switch, PMIC, eMRAM Only 36 masksEnables new RF architectures Highest ft/fmax Up to 30-50% area savings vs.28nm mmWave PA via SOI-stackingIntegration for car of tomorrow MCU w/ integrated eMRAM and5v MOS device for ADC mmWave for long-range radar Low power ADASValue Extends Across Multiple Product Lines 2017 GLOBALFOUNDRIES4
Digital Reference Flows, PDK Enablement with Foundation IPCadence Certified Reference FlowSynopsys Certified Reference FlowPlace & RouteSYNTHESISFORMALVERIFICATIONDesign CompilerLVSAnsysFormalityPEXCadence(RTL vs Gate Netlist)MentorDRCPLACE & ROUTEIC Compiler, IC Compiler IIIC Validator EFill(Gate \vs Routed Netlist)*Some by request*Additional vendorsupport availableEM/IRStarRCPEXCustom DesignSYNTHESISGenusFORMALVERIFICATION(RTL vs Gate Netlist)PLACE & ROUTEInnovusPVS (In-design)FORMALVERIFICATIONPEXConformal(Gate vs Routed Netlist)QuantusTempusPrimeTimeSTAStd cell libTape-outproven FlowColor-AwarePDKGF Digital Design es sample block tested at allRTL-to-GDS steps with eConformalPath Depth7LP7LP, 14LPP,22FDX 12FDX 22FDX 12FDX 7LP, 14LPP,22FDX 12FDX 7LP, 14LPP,22FDX 12FDX 7LP, 14LPP,22FDX 12FDX 5
AMS Reference FlowPre-Layout Functional VerificationCustom LayoutAccelerated Custom LayoutAMS Design CapabilitiesADE-XL/MMSIM, HspicePrelayout -XLLayout-LDELayout-EADCustom LayoutVirtuosoMSOA InteroperabilityVirtuoso/INNOVUSPhysical VerificationCalibre, PVS, ICVParasitic ExtractionStarRC, QRC, xRC*Post-Layout Functional VerificationEM/IRFill, DFMADE-XL/MMSIM, HspiceTotem, Voltus-FiCadenceMentorSynopsysMSOA InteropPhysical Verification*Some by request*Additional vendorsupport availableParas ExtractionPost Layout FunctionalVerEMIRFILL, DFMCalibre, PVS, ICV 2017 GLOBALFOUNDRIES6
Ecosystem Partnering for GrowthReduce time to marketand facilitate FDX SoC product design Easy access to plug andplay solutions Minimizes customerdevelopment costs Lowers barriers ofmigration 2017 GLOBALFOUNDRIESEDAOSATDesignServicesIPASICEmbedded SystemSoftwareIP7
Building Global Scale for FDX From Substrates to FabsBernin, France FD-SOI substrates 400kw/ year capacity Already qualified, in mass productionDresden, Germany Fab 1 Expanding 22FDX FD-SOIcapacity by 40% by 2020 Developing 12FDX FD-SOItechnologyGF and SOITEC Partnership Multi-fab sourcing Multiple substrate supply Long term supply agreementPasir Ris, Singapore FD-SOI substrates SOI HVM qualified in 2007 FD-SOI production line started End customer qual, in 1H 2019 Full capacity of 800kw/ yearChengdu, China Fab 11 New 300mm fab Partnership w/ ChengduMunicipal Government Existing 180 / 130nm nodes,22FDX ramp in 2H 2019GLOBALFOUNDRIES Confidential8
Manufacturing Strength: Europe’s Largest & Most Advanced FabPhase 5Phase 3 12.000 m²(2011)Phase 2 2.500 m²(2002) 14.000 m²(1999) 14.000 m²(2005) 3,400 employees 2x indirect jobs regionallyMain engine of “Silicon Saxony“ ClusterPhase 1 Phase 4 10.000 m²(2007)Investment of 12B since 1996 6B invested from 2009 aloneExtensive R&D network 2017 GLOBALFOUNDRIES9
FDXTM Ecosystem: Collaborative European Supply Chain ModelDesign & EDA PartnersDesignMask SetsMemory & OSAT PartnersSubstratesWafer FabBumpProbe 2017 GLOBALFOUNDRIESThin, BSIAssembly &Test10
Summary Market: Growing Client Device Data Traffic requires next Generation Technologies GLOBALFOUNDRIES Dual Roadmap Design Readiness and -Ecosystem 22FDX Supply Chain 2017 GLOBALFOUNDRIES11
Thank youThe information contained herein is the property of GLOBALFOUNDRIES and/or its licensors.This document is for informational purposes only, is current only as of the date of publication and is subject to change by GLOBALFOUNDRIES at any time without notice.GLOBALFOUNDRIES, the GLOBALFOUNDRIES logo and combinations thereof are trademarks of GLOBALFOUNDRIES Inc. in the United States and/or other jurisdictions.Other product or service names are for identification purposes only and may be trademarks or service marks of their respective owners. GLOBALFOUNDRIES Inc. 2017. Unless otherwise indicated, all rights reserved. Do not copy or redistribute except as expressly permitted by GLOBALFOUNDRIES.
Formality (RTL vs Gate Netlist) Formality (Gate \vs Routed Netlist) StarRC PrimeTime . SADP-Aware 7LP, 14LPP, 22FDX 12FDX Ansys Cadence (RTL vs Gate Netlist) Mentor Synopsys Place & Route LVSSYNTHESIS PEX DRC SPICE Fill EM/IR Custom Design *Some by request *Additional vendor support available FORMAL VERIFICATION PLACE & ROUTE FORMAL .
